JP2002151664A - Manufacturing method for semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique, capable of reducing generation of recesses, preventing the generation of the kink phenomenon of an MISFET formed on an element formation area and reducing leakage current. SOLUTION: After depositing a silicon oxide film (TEOS film), using ozone and tetraethoxysilane inside a groove formed in the element separation area of a semiconductor substrate 1, heat treatment is executed, and thus element separation (TEOS film 106a) is formed. As a result, the etching speed of the silicon oxide film (TEOS film 106a) is reduced, and the generation of the recesses is reduced. Further, when forming the MISFET on an element formation area surrounded by such a silicon oxide film (TEOS film 106a), the generation of the kink phenomenon is prevented and the leakage current is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to a method for manufacturing a fine semiconductor integrated circuit device.

[0002]

2. Description of the Related Art As an element isolation technique in an LSI manufacturing process, a selective oxidation (Local Oxidization of Silicon;
The LOCOS method has been widely used, but with the miniaturization of semiconductor elements, the introduction of element isolation technology using element isolation grooves has been promoted.

In this method, an insulating film such as a silicon oxide film is formed inside a groove formed in a semiconductor substrate, and the silicon oxide film outside the groove is removed by etching to form a shallow groove isolation (SGI). However, since this is used for isolation between elements, there are advantages such that the element isolation interval can be reduced and the element isolation film thickness can be easily controlled.

[0004]

However, in such element isolation, when the silicon oxide film outside the trench is wet-etched, a so-called recess occurs in which the edge of the silicon oxide film is etched more and recedes. .

Further, CMP (Chemical Mechanical Polishing: Chemical
Even after the silicon oxide film outside the groove is polished by using a mechanical polishing method, a recess is generated due to wet etching, cleaning, resist ashing, and the like during the subsequent element forming process.

In particular, CVD (Chemical Vapor depositio)
The silicon oxide film formed by the method n) has a high wet etching rate and is easily recessed.

When this recess occurs, when the MISFET is formed on the element forming region, the electric field concentrates on the recessed portion, and the sub-threshold characteristic of the MISFET (gate voltage (horizontal axis) vs. drain current (vertical axis)) (Kink phenomenon) in which the drain current increases in a region where the gate voltage is small.

As a result, the leakage current increases and the MISFE
Problems such as variations in the characteristics of T occur.

An object of the present invention is to provide a technique for preventing the occurrence of a recess at an end of a silicon oxide film formed on the inner wall of an element isolation groove.

Another object of the present invention is to provide a technique for improving the characteristics of a MISFET by preventing the occurrence of a recess.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of typical inventions disclosed in the present application.

The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of (a) selectively forming an insulating film on an element forming region of a semiconductor substrate; and (b) using the insulating film as a mask.
Forming a groove in the device isolation region of the semiconductor substrate by etching the device isolation region of the semiconductor substrate; and (c) forming a silicon oxide film on the device isolation region and the device formation region of the semiconductor substrate. Forming a silicon oxide film by a reaction between ozone and tetraethoxysilane; (d) heat-treating the silicon oxide film; and (e) forming the silicon oxide film on the surface of the semiconductor substrate. Flattening until exposed,
Having. This heat treatment step is performed, for example, at 1000 ° C. to 1 ° C.
Performed at 200 ° C. The silicon oxide film has, for example, a flow rate ratio of ozone to tetraethoxysilane of 0.07.
And a film formation temperature of 380 ° C. to 700 ° C.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, there are provided (a) a step of selectively forming an insulating film on an element forming region of a semiconductor substrate; and (b) a thermal process using the insulating film as a mask. Forming a thermal oxide film in the device isolation region of the semiconductor substrate by oxidizing; and (c) etching the device isolation region of the semiconductor substrate using the insulating film as a mask, thereby forming a device on the semiconductor substrate. Forming a groove in the isolation region, and (d) forming a silicon oxide film on the device isolation region and the device formation region of the semiconductor substrate, wherein the silicon oxide film is formed by a reaction between ozone and tetraethoxysilane. (E) heat-treating the silicon oxide film; and (f) flattening the silicon oxide film until the surface of the semiconductor substrate is exposed. .

Further, the method for manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a step of selectively forming an insulating film on an element forming region of a semiconductor substrate; and (b) a step of forming a side wall on the side wall of the insulating film. Forming a wall film; and (c) forming a groove in the device isolation region of the semiconductor substrate by etching the device isolation region of the semiconductor substrate using the insulating film and the sidewall film as a mask. (D) a step of removing the sidewall film, and (e) a step of forming a silicon oxide film on the element isolation region and the element formation region of the semiconductor substrate, wherein the silicon oxide film reacts with ozone and tetraethoxysilane. Forming a silicon oxide film; (f) heat treating the silicon oxide film; and (g) planarizing the silicon oxide film until the surface of the semiconductor substrate is exposed. It has a that step.

[0016]

(Embodiment 1) A method of manufacturing a semiconductor integrated circuit device according to Embodiment 1 of the present invention will be described in the order of steps with reference to FIGS.

As shown in FIG. 1, a thin pad oxide film 101 is formed by thermal oxidation on a semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm. Next, a silicon nitride film 102 (an insulating film described in the claims) is formed on the pad oxide film 101.

Next, as shown in FIG. 2, a photoresist film 103 having an opening on an element isolation region of the semiconductor substrate 1 is formed on the silicon nitride film 102, and using the photoresist film 103 as a mask. Silicon nitride film 10
2 and the pad oxide film 101 are etched.

Next, the photoresist film 103 is removed, and the semiconductor substrate 1 is etched using the silicon nitride film 102 as a mask, as shown in FIG.
A groove 104 having a depth of about 8 μm and a depth of about three times the width (aspect ratio 3) is formed.

Thereafter, as shown in FIG.
Is thermally oxidized to form a thin silicon oxide film 105 on the inner wall of the groove.

Next, as shown in FIG. 5, a silicon oxide film 106 having a thickness of about 450 to 700 nm is deposited on the semiconductor substrate 1 including the inside of the trench 104. This silicon oxide film 106 is formed by a CVD method using ozone (O ₃ ) and tetraethoxysilane. Hereinafter, this silicon oxide film 106 is referred to as a TEOS film 106. Here, the flow rate ratio (TEO) between ozone (O ₃ ) and tetraethoxysilane
(S / O ₃ ) was 0.32, and the film formation temperature was 570 ° C.

Next, an oxygen atmosphere (O ₂ : about 200 pp)
m) heat treatment under 1000 ° C. This heat treatment is
This is performed to remove impurities such as moisture and carbon compounds taken in the EOS film 106 when the EOS film 106 is formed. As a result, the film quality of the TEOS film 106 is improved, and a more dense film (106a) is obtained (FIG. 6).

Next, as shown in FIG. 7, a photoresist film 107 is formed on the wide element isolation region. This photoresist film 107 has TE on the narrow element isolation region.
While the OS film 106a is formed thick, the TEOS film 106a over a wide element isolation region is thin, so that it is formed to correct this difference in film thickness. Next, using the photoresist film 107 as a mask, the TEOS film 106a is etched to form the TEOS film 106a on the narrow element isolation region.
The thickness is almost equal to the TEOS film 106a over a wide element isolation region.

Next, as shown in FIG. 8, the TEOS film 106a is polished by the CMP method until the surface of the silicon nitride film 102 is exposed. This silicon nitride film functions as an oxidation-resistant mask during the previous thermal oxidation, and also functions as a stopper film during polishing. Next, as shown in FIG. 9, the silicon nitride film 102 and the pad oxide film 101 are removed.

Through the above steps, the TEOS film 106a
An element formation region separated by (element separation) is completed. At this time, the element isolation region protrudes from the element formation region by the thickness of the silicon nitride film 102 and the pad oxide film 101 (see FIG. 9). However, as described above, an element such as a MISFET is formed on the element formation region. The surface of the element formation region gradually recedes due to wet etching, washing, resist ashing, and the like during the process. In particular, since the TEOS film is etched from its side, the above-described recess is likely to occur as shown in FIG.

However, in the present embodiment,
After the TEOS film 106 was formed by a CVD method using ozone and tetraethoxysilane, a heat treatment was performed at 1000 ° C. in an oxygen atmosphere (O ₂ : about 200 ppm), so that impurities in the TEOS film were removed.
The OS film can be densified.

As a result, the etching rate of the TEOS film 106a can be reduced, and the occurrence of recess can be reduced. For example, in the case of a TEOS film that is not subjected to a heat treatment, the etching rate is about five times as high as that of a thermal oxide film, whereas the TEOS film 106a used in this embodiment is used.
The etching rate was 1.7 times that of the thermal oxide film, and the etching rate could be reduced. The etching rate was calculated by wet etching using a hydrofluoric acid-based etchant.

As described above, in this embodiment, since the occurrence of the recess can be reduced, the occurrence of the kink phenomenon of the MISFET formed on the element formation region can be prevented, and the leakage current can be reduced. it can. Also,
Variations in the characteristics of these MISFETs can be reduced.

That is, when an information transfer MISFET constituting a DRAM memory cell and an n-channel MISFET and a p-channel MISFET constituting a logic circuit are formed on an element formation region, the leakage current of these MISFETs is reduced. MISFE such as threshold voltage
Variations in the characteristics of T can be reduced.

Subsequently, the MI formed on the element formation region
As an example of the SFET, an outline of a process of forming an information transfer MISFET constituting the above-described DRAM memory cell will be described with reference to FIGS.

First, the TEOS film 106a (element isolation) embedded in the trench 104 is formed by the method described above.
Here, as shown in FIG. 26, a plurality of element forming regions L surrounded by the TEOS film 106a are formed. Two MISFETs Qs for information transfer sharing one of the source and the drain are formed in each of the element forming regions L. Note that, for example, FIG. 9 corresponds to a cross-sectional view taken along the line AA of FIG.

Next, as shown in FIG.
A p-type well 3 is formed by ion-implanting B (boron) into the well, and then the surface of the p-type well 3 is
After cleaning with a (hydrofluoric acid) -based cleaning solution, the semiconductor substrate 1 is thermally oxidized to form a p-type well 3 (element formation region L).
A gate insulating film 5 having a thickness of about 6 nm is formed on the surface of the substrate.

Next, a gate electrode 6 is formed on the gate insulating film 5. The gate electrode 6 is, for example, a gate insulating film 5
N-type polycrystalline silicon film (thickness: about 70 nm) doped with P (phosphorus) or the like, WN (tungsten nitride)
Alternatively, a barrier metal film (thickness: about 5 nm to 10 nm) made of TiN (titanium nitride), a W film (100 nm thick)
About) and silicon nitride film 7 (about 150 nm thick)
Are sequentially deposited, and these films are formed by dry etching using a photoresist film as a mask. This gate electrode 6 functions as a word line (WL).

Next, As (arsenic) or P (phosphorus) is ion-implanted into the p-type well 3 and the n-type semiconductor region 8 (source, drain) is formed in the p-type well 3 on both sides of the gate electrode 6.
To form By the steps up to this point, the MIS for information transfer
The FET Qs is substantially completed.

Next, a silicon nitride film 9 (50 nm thick) and a silicon oxide film 10 are formed on the semiconductor substrate 1 by CVD.
(Thickness: about 600 nm) is deposited. Subsequently, after the surface of the silicon oxide film 10 is flattened by a chemical mechanical polishing method, the silicon oxide film 10 and the silicon nitride film 9 are dry-etched using a photoresist film (not shown) as a mask, so that information transfer is performed. Contact holes 11 and 12 are formed above the n-type semiconductor region 8 (source and drain) of the MISFET Qs. The etching of the silicon oxide film 10 is performed under the condition that the selectivity to the silicon nitride film is large, and the etching of the silicon nitride film 9 is performed under the condition that the etching selectivity to the silicon or the silicon oxide film is large. As a result, the contact holes 11 and 12 are formed in a self-alignment (self-alignment) with the gate electrode 6 (word line).

Next, a plug 13 is formed inside the contact holes 11 and 12. To form the plug 13,
A P-doped n-type polycrystalline silicon film is deposited on the silicon oxide film 10 by a CVD method to bury the n-type polycrystalline silicon film inside the contact holes 11 and 12. The n-type polycrystalline silicon film outside 12 is removed by a chemical mechanical polishing method (or etch back).

Next, CVD is performed on the silicon oxide film 10.
After a silicon oxide film 14 (about 150 nm in thickness) is deposited by a method, the silicon oxide film 14 above the contact hole 11 is dry-etched using a photoresist film (not shown) as a mask to form a through hole 15. Form.

Next, the plug 1 is inserted into the through hole 15.
6 is formed. To form the plug 16, a Ti film and a T film are formed on the silicon oxide film 14 by, for example, a sputtering method.
After depositing a barrier metal film composed of a laminated film with an iN film, and subsequently depositing a W film on the barrier metal film by a CVD method, these films are buried inside the through-holes 15 to form a through-hole. These films outside of 15 are removed by chemical mechanical polishing. These plugs 16 and 13
, The n-type semiconductor region 8 (source, drain) of the information transfer MISFET Qs is connected to a bit line BL described later.

Next, the silicon oxide film 14 and the plug 1
6, a bit line BL is formed. To form the bit line BL, for example, a TiN film (about 10 nm in thickness, not shown) is deposited on the silicon oxide film 14 by a sputtering method, and then a W film (film) is formed on the TiN film by a CVD method. Thickness 5
(About 0 nm), these films are dry-etched using a photoresist film (not shown) as a mask.

Next, a silicon oxide film 17 (thickness: about 300 nm) is deposited on the bit line BL by a CVD method, and then its surface is planarized by a chemical mechanical polishing method. Next, the silicon nitride film 1 is formed on the silicon oxide film 17 by CVD.
8 (thickness: about 50 nm) is deposited, and then the silicon nitride film 18 and the silicon oxide film 17 are dry-etched to form a through hole 19 above the contact hole 12 in which the plug 13 is embedded.

The through hole 19 is formed such that its diameter is smaller than the diameter of the contact hole 12 thereunder.

Next, the plug 2 is inserted into the through hole 19.
Form 2 To form the plug 22, first, an n-type polycrystalline silicon film doped with P is deposited on the silicon nitride film 18 by a CVD method to form the through hole 1.
After the n-type polycrystalline silicon film is buried in 9, the n-type polycrystalline silicon film outside through hole 19 is removed by a chemical mechanical polishing method (or etch back). At this time, n
By overpolishing (overetching) the type polycrystalline silicon film, a space for embedding a barrier layer 23 described later is secured. The barrier layer 23 is formed by depositing a tantalum nitride film on the silicon nitride film 18 by a sputtering method so that the tantalum nitride film is buried in the space above the plug 22 and then the tantalum nitride film outside the space is chemically removed. It is formed by removing by a mechanical polishing method (or etch back).

Next, a silicon oxide film 24 is deposited on the barrier layer 23 and the silicon nitride film 18, and then the silicon oxide film 24 and the silicon nitride film 18 are dry-etched to form a deep hole (recess) 27. I do. The bottom of the deep hole (recess) 27 has a through hole 19
The surface of the barrier layer 23 inside is exposed.

Next, a Ru film 30 (thickness: 30 n) is formed on the silicon oxide film 24 and inside the holes 27 by CVD.
m).

Next, a photoresist film (not shown) is applied on the Ru film 30, the entire surface is exposed, and development is performed, so that the photoresist film (not shown) remains in the holes 27. Next, the lower electrode 30a is formed by removing the Ru film 30 on the silicon oxide film 24 by performing dry etching using the photoresist film as a mask. Next, the photoresist film in the hole 27 is removed.

Next, the hole 27 in which the lower electrode 30a is formed
A tantalum oxide film 32 serving as a capacitor insulating film is deposited inside and on the silicon oxide film 24. The tantalum oxide film 32 is made of pentaethoxy tantalum (Ta (OC ₂ H ₅ ) ₅ ).
And oxygen are used as a raw material for deposition.

Next, an upper electrode 33 is formed on the tantalum oxide film 32. The upper electrode 33 is, for example, a Ru film (about 70 nm thick) on the tantalum oxide film 32 by a CVD method.
And a W film (having a thickness of about 100 nm). The W film is used to reduce the contact resistance between the upper electrode 33 and the upper wiring. Next, the tantalum oxide film 32 and the upper electrode 33 are patterned (not shown).

By the steps up to this point, the information storage capacitive element C composed of the lower electrode 30a made of the Ru film 30, the capacitor insulating film made of the tantalum oxide film 32, and the upper electrode 33 made of the W film / Ru film is completed. Then, a DRAM memory cell including the information transfer MISFET Qs and the information storage capacitor C connected in series to the MISFET Qs is substantially completed.

FIG. 28 is a plan view of the semiconductor integrated circuit device after the formation of the information storage capacitive element C. FIG. 27 corresponds to, for example, a cross-sectional view taken along a line BB in FIG.

Thereafter, an interlayer insulating film made of a silicon oxide film or the like is formed on the information storage capacitive element C, and about two layers of Al wiring are formed on this interlayer insulating film, and the uppermost layer Al wiring is formed. A passivation film is formed on the upper portion, but these are not shown.

As described in detail above, according to the present embodiment, since the occurrence of the recess can be reduced, the information transfer MISFET Q formed on the element formation region L can be reduced.
The occurrence of the kink phenomenon of s can be prevented, and the leak current can be reduced. Further, variation in characteristics of the information transfer MISFET Qs can be reduced.

(Embodiment 2) FIGS. 11 to 18 are cross-sectional views of essential parts of a substrate showing a method of manufacturing a semiconductor integrated circuit device according to Embodiment 2 of the present invention.

As shown in FIG. 11, for example, 1 to 10 Ωcm
A thin pad oxide film 101 is formed on a semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance by thermal oxidation. Next, a silicon nitride film 102 is formed on the pad oxide film 101.

Next, on this silicon nitride film 102,
A photoresist film 103 having an opening is formed on an element isolation region of the semiconductor substrate 1, and the silicon nitride film 102 and the pad oxide film 10 are formed using the photoresist film as a mask.
By etching 1, the surface of the element isolation region of the semiconductor substrate 1 is exposed.

Next, the surface of the semiconductor substrate 1 is thermally oxidized using the silicon nitride film 102 as a mask to form a thermal oxide film 101a. At this time, a bird's beak occurs at the end of the silicon nitride film 102, and the thermal oxide film 1 extends to a lower portion of the silicon nitride film 102 (pad oxide film 101).
01a has a shape in which the end is sunk.

Next, the photoresist film 103 is removed, and the semiconductor substrate 1 is etched using the silicon nitride film 102 as a mask, as shown in FIG.
A groove 104 having a thickness of 18 μm and a depth of about three times the width (aspect ratio 3) is formed.

After that, as shown in FIG. 13, the semiconductor substrate 1 is thermally oxidized to form a thin silicon oxide film 105 on the inner wall of the groove.

Next, as shown in FIG. 14, a silicon oxide film 106 having a thickness of about 450 to 700 nm is deposited on the semiconductor substrate 1 including the inside of the trench 104. This silicon oxide film 106 is formed by a CVD method using ozone (O ₃ ) and tetraethoxysilane. Hereinafter, this silicon oxide film 106 is referred to as a TEOS film 106. here,
Ozone (O ₃ ) and tetraethoxysilane flow rate ratio (TE
OS / O ₃ ) was 0.34, and the film formation temperature was 570 ° C.

Next, an oxygen atmosphere (O ₂ : about 200 pp)
m) under 1150 ° C. This heat treatment is
This is performed to remove impurities such as moisture and carbon compounds taken in the EOS film 106 when the EOS film 106 is formed. As a result, the quality of the TEOS film 106 is improved, and the TEOS film 106 becomes a denser film (106a) (FIG. 15).

Next, as shown in FIG. 16, a photoresist film 107 is formed on a wide element isolation region. This photoresist film 107 has a T
The EOS film 106a is formed to be thick, whereas the TEOS film 106a over a wide element isolation region is thin. Therefore, the TEOS film 106a is formed to correct this difference in film thickness. Then, using the photoresist film 107 as a mask, the TEOS film 106a is etched to form the TEOS film 106a on the narrow element isolation region.
Has a thickness substantially equal to that of the TEOS film 106a on the wide element isolation region.

Then, as shown in FIG. 17, the TEOS film 106a is exposed until the surface of the silicon nitride film 102 is exposed.
Is polished by a CMP method. This silicon nitride film functions as an oxidation-resistant mask during the previous thermal oxidation, and also functions as a stopper film during polishing. Next, the silicon nitride film 102 and the pad oxide film 101 are removed.

Through the above steps, the TEOS film 106a
An element formation region separated by (element separation) is completed.

In this element formation region, for example, a DRAM
Although a memory cell is formed, the formation step has been described in Embodiment 1 and will not be described.

As described above, in the present embodiment, T
After forming the EOS film 106, an oxygen atmosphere (O2: about 2
00 ppm), the heat treatment at 1150 ° C.
The impurities in the EOS film are removed, and the TEOS film can be densified.

As a result, the etching rate of the TEOS film 106a can be reduced, and the occurrence of recess can be reduced. TEOS film 10 used in this embodiment
The etching rate of 6a was 1.1 times that of the thermal oxide film, and the etching rate was further reduced as compared with the case of the first embodiment. Note that this etching rate was calculated by wet etching using a hydrofluoric acid-based etchant, as in the first embodiment.

Since the occurrence of the recess can be reduced, the kink phenomenon of the MISFET formed on the element formation region can be prevented and the leakage current can be reduced as in the first embodiment. Can be. Also, M
Variations in ISFET characteristics can be reduced.

Further, in this embodiment, due to the bird's beak of the thermal oxide film 101a, the end of the element forming region becomes a gentle curved surface (FIG. 18), and the concentration of the electric field can be reduced. As a result, the characteristics of the MISFET formed on the element formation region can be improved.

(Embodiment 3) FIGS. 19 to 25 are cross-sectional views of essential parts of a substrate showing a method of manufacturing a semiconductor integrated circuit device according to Embodiment 3 of the present invention.

As shown in FIG. 19, for example, 1 to 10 Ωcm
A thin pad oxide film 101 is formed on a semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance by thermal oxidation. Next, a silicon nitride film 102 is formed on the pad oxide film 101.

Next, on this silicon nitride film 102,
A photoresist film (not shown) having an opening is formed on an element isolation region of the semiconductor substrate 1, and the silicon nitride film 102 and the pad oxide film 101 are etched using the photoresist film as a mask, thereby forming a semiconductor substrate. The surface of one element isolation region is exposed.

Next, a silicon oxide film 102a is deposited on the semiconductor substrate 1 including the silicon nitride film 102 by a CVD method. Next, the silicon oxide film 102a is anisotropically etched to form the silicon nitride film 102a.
And a sidewall film 1 on the side wall of the pad oxide film 101.
02Sa is formed.

Next, as shown in FIG. 20, the semiconductor substrate 1 is etched using the silicon nitride film 102 and the side wall film 102Sa as a mask to form the trench 104.
To form

Thereafter, as shown in FIG. 21, the silicon nitride film 102 and the sidewall film 102Sa remaining on the side walls of the pad oxide film 101 are removed. Next, a thin silicon oxide film 105 is formed on the inner wall of the groove by thermally oxidizing the semiconductor substrate 1.

Next, as shown in FIG. 22, a silicon oxide film 106 having a thickness of about 450 to 700 nm is deposited on the semiconductor substrate 1 including the inside of the trench 104. This silicon oxide film 106 is formed by a CVD method using ozone (O ₃ ) and tetraethoxysilane. Hereinafter, this silicon oxide film 106 is referred to as a TEOS film 106. here,
Ozone (O ₃ ) and tetraethoxysilane flow rate ratio (TE
OS / O ₃ ) was 0.27, and the film formation temperature was 450 ° C. Here, in the present embodiment, since the width of the groove 104 is smaller by the side wall film 102Sa, TE
In order to sufficiently bury the OS film 106, it is necessary to lower the film formation temperature.

Next, in an oxygen atmosphere (O ₂ : about 200 pp)
m) under 1150 ° C. This heat treatment is
This is performed to remove impurities such as moisture and carbon compounds taken in the EOS film 106 when the EOS film 106 is formed. As a result, the film quality of the TEOS film 106 is improved, and a more dense film (106a) is obtained (FIG. 23).

Next, as shown in FIG. 24, a photoresist film 107 is formed on a wide element isolation region. This photoresist film 107 has a T
The EOS film 106a is formed to be thick, whereas the TEOS film 106a over a wide element isolation region is thin. Therefore, the TEOS film 106a is formed to correct this difference in film thickness. Then, using the photoresist film 107 as a mask, the TEOS film 106a is etched to form the TEOS film 106a on the narrow element isolation region.
Has a thickness substantially equal to that of the TEOS film 106a on the wide element isolation region.

Next, as shown in FIG. 25, until the surface of the silicon nitride film 102 is exposed,
Is polished by a CMP method. This silicon nitride film functions as an oxidation-resistant mask during the previous thermal oxidation, and also functions as a stopper film during polishing. Next, the silicon nitride film 102 and the pad oxide film 101 are removed.

Through the above steps, the TEOS film 106a
An element formation region separated by (element separation) is completed.

Next, as in the first embodiment, a DRAM memory cell or an n-channel M
A logic circuit composed of an ISFET and a p-channel MISFET is formed, but the description is omitted.

As described above, in the present embodiment, T
After forming the EOS film 106, an oxygen atmosphere (O ₂ : about 2
00 ppm), the heat treatment at 1150 ° C.
The impurities in the EOS film are removed, and the TEOS film can be densified.

As a result, the etching rate of the TEOS film 106a can be reduced, and the occurrence of recess can be reduced. TEOS film 10 used in this embodiment
The etching rate of 6a was 1.1 times that of the thermal oxide film, and the etching rate was further reduced as compared with the case of the first embodiment. Note that this etching rate was calculated by wet etching using a hydrofluoric acid-based etchant, as in the first embodiment. Further, by performing a heat treatment at 1150 ° C. even though the film formation temperature was lowered to 450 ° C. as compared with Embodiment 2,
An etching rate 1.1 times that of the thermal oxide film (about the same as that of the second embodiment) could be maintained.

Since the occurrence of the recess can be reduced, the kink phenomenon of the MISFET formed on the element formation region can be prevented and the leakage current can be reduced as in the first embodiment. Can be. Further, variations in the characteristics of these MISFETs can be reduced.

Further, in this embodiment, a sidewall film 102Sa is formed on the side walls of the silicon nitride film 102 and the pad oxide film 101, and the silicon nitride film 10
Since the trench 104 is formed by etching the semiconductor substrate 1 using the second and sidewall films 102Sa as a mask, a trench having a smaller width than in the first embodiment can be formed.

As described above, the present invention made by the inventor
Although a specific description has been given based on the embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various changes can be made without departing from the scope of the invention.

In particular, in the first embodiment, the above-mentioned DRA is used as the MISFET formed on the element formation region.
Although the example of the information transfer MISFET forming the M memory cell has been described, the n-channel MISFET and the p-channel MISFET forming the logic circuit are formed on the element formation region.
May be formed, or the DRAM memory cell and the logic circuit may be formed over the same substrate.

[0086]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In the manufacturing method of the present invention, a heat treatment is performed after forming a silicon oxide film (TEOS film 106) using ozone and tetraethoxysilane in the element isolation region, so that impurities in the silicon oxide film are removed. In addition, the silicon oxide film can be densified.

As a result, the silicon oxide film (TEOS film 1
06a), the etching rate can be reduced, and the occurrence of recesses can be reduced.

Further, when the MISFET is formed on the element isolation region, since the occurrence of the recess can be reduced, the occurrence of the kink phenomenon can be prevented, and the leak current can be reduced. Further, variations in the characteristics of these MISFETs can be reduced.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to Embodiment 1 of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view of a main part of the substrate for describing the occurrence of a recess.

FIG. 11 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 17 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;

FIG. 20 is an essential part cross sectional view of the substrate for illustrating the method for manufacturing the semiconductor integrated circuit device of Embodiment 3 of the present invention.

FIG. 21 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;

FIG. 22 is an essential part cross sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of Embodiment 3 of the present invention.

FIG. 23 is an essential part cross sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of Embodiment 3 of the present invention.

FIG. 24 is an essential part cross sectional view of the substrate for illustrating the method for manufacturing the semiconductor integrated circuit device of Embodiment 3 of the present invention.

FIG. 25 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;

FIG. 26 is a plan view of a principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 27 is an essential part cross sectional view of the substrate for illustrating the method for manufacturing the semiconductor integrated circuit device of the first embodiment of the present invention.

FIG. 28 is a main-portion plan view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 3 p-type well 5 gate insulating film 6 gate electrode 7 silicon nitride film 8 n-type semiconductor region 9 silicon nitride film 10 silicon oxide film 11 contact hole 13 plug 14 silicon oxide film 15 through hole 16 plug 17 silicon oxide film 18 Silicon nitride film 19 Through hole 22 Plug 23 Barrier layer 24 Silicon oxide film 27 Hole 30 Ru film 30a Lower electrode 32 Tantalum oxide film 33 Upper electrode 101 Pad oxide film 101a Thermal oxide film 102 Silicon nitride film 102Sa Side wall film 102a Silicon oxide film 103 Photoresist film 104 Groove 105 Silicon oxide film 106 TEOS film 106a TEOS film 107 Photoresist film BL Bit line C Information storage capacitor L Element formation region Qs Information transfer MI FET

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/768 H01L 21/90 C 5F083 27/08 331 27/10 621C 29/78 29/78 301R (72 ) Inventor Katsuhiko Hotta 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Super-LSI Systems Co., Ltd. (72) Inventor Norio Suzuki 5--20, Josuihoncho, Kodaira-shi, Tokyo No. 1 F-term in Hitachi, Ltd. Semiconductor Group (reference) QQ37 QQ48 RR04 RR06 SS11 TT02 TT07 VV16 WW03 WW06 XX00 XX31 5F040 DA15 DB09 EA08 EC02 EC04 EC07 EC12 EH03 EH08 EK05 FA18 FC10 FC28 5F048 AA04 AA0 7 AB01 AC01 AC03 AC10 BA01 BB06 BB09 BB13 BE03 BF04 BG13 BG14 DA27 5F058 BA02 BD04 BF02 BF25 BF29 BH01 BH11 BJ06 5F083 AD31 GA06 JA06 JA38 JA39 JA40 KA05 MA02 MA06 MA17 MA20 NA01 PR05 PR07 PR10 PR12 PR21 PR12 PR21 PR12 PR12 PR21 PR12 PR21 PR12 PR21 PR12 PR21 PR12 PR21 PR12 PR21

Claims (5)

[Claims] 1. A method according to claim 1, wherein: (a) on an element forming region of the semiconductor substrate,
(B) forming a groove in the element isolation region of the semiconductor substrate by etching the element isolation region of the semiconductor substrate using the insulating film as a mask; c) forming a silicon oxide film on the element isolation region and the element formation region of the semiconductor substrate, wherein the silicon oxide film is formed by a reaction between ozone and tetraethoxysilane; and A method for manufacturing a semiconductor integrated circuit device, comprising: a step of heat-treating a silicon film; and (e) a step of flattening the silicon oxide film until the insulating film is exposed. 2. The heat treatment step is performed at 1000 ° C. to 120 ° C.
2. The method according to claim 1, wherein the method is performed at 0 [deg.] C. 3. The silicon oxide film according to claim 1, wherein the flow ratio of ozone to tetraethoxysilane is 0.07 to 1.0 and the film formation temperature is 380 to 700 ° C. A method for manufacturing a semiconductor integrated circuit device according to claim 1. 4. A method according to claim 1, wherein: (a) on an element forming region of the semiconductor substrate,
Selectively forming an insulating film; (b) forming a thermal oxide film in an element isolation region of the semiconductor substrate by thermally oxidizing the insulating film as a mask; Forming a groove in the device isolation region of the semiconductor substrate by etching the device isolation region of the semiconductor substrate on the mask; and (d) forming silicon oxide on the device isolation region and the device formation region of the semiconductor substrate. A step of forming a film, a step of forming a silicon oxide film by a reaction between ozone and tetraethoxysilane,
(E) heat-treating the silicon oxide film;
Flattening the silicon oxide film until the insulating film is exposed. 5. A semiconductor device according to claim 1, wherein:
Selectively forming an insulating film; (b) forming a sidewall film on a side wall of the insulating film; and (c) using the insulating film and the sidewall film as a mask to form an element isolation region of the semiconductor substrate. Forming a groove in an element isolation region of the semiconductor substrate by etching
(D) removing the sidewall film; and (e).
Forming a silicon oxide film on the device isolation region and the device formation region of the semiconductor substrate, wherein the silicon oxide film is formed by a reaction between ozone and tetraethoxysilane; and (f) the silicon oxide film And (g) flattening the silicon oxide film until the insulating film is exposed.