JP2002151522A - Active matrix substrate and its manufacturing method and display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix substrate where a thin film transistor array is made on a plastic substrate. SOLUTION: This active matrix substrate is equipped with a plastic substrate 1, a plurality of scanning wires 2 which are made on the plastic substrate 1, a plurality of signal wires 5 which cross the scanning wires 2 through an insulating film, and a plurality of thin film transistors 10 which are made on the plastic substrate 1 and operate in answer to the scanning signal on the corresponding scanning wire 2, and a plurality of picture element electrodes 14 which are electrically connected with the signal wires 5 through the thin film transistor 10. The corresponding picture element electrode 14 and the thin film transistor 10 are connected with each other by conductive member 9, and the picture element electrode 14 and the conductive member 9 cross severally adjacent different scanning wires.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an active matrix substrate and a method of manufacturing the same, and a display device using the active matrix substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been used not only as image display elements of desktop computers and television devices used indoors, but also as mobile phones, notebook or laptop personal computers, portable televisions, digital cameras. It is widely used as an information display element in various portable electronic devices such as digital camcorders, and also on-vehicle electronic devices such as car navigation devices.

[0003] Among various liquid crystal display devices, a liquid crystal display device driven by a matrix electrode is roughly classified into a display device operated by passive matrix driving and a display device operated by active matrix driving. Among them, in the active matrix type display device, a switching element is provided for each pixel arranged in a matrix composed of a row and a column, and a plurality of signal wirings arranged so as to intersect each other. In addition, the switching element is controlled using the scanning wiring, and a desired signal charge (data signal) can be given to the selected pixel electrode.

First, a conventional active matrix display device will be described with reference to FIGS. 43 and 44. FIG. 43 shows a schematic configuration of a liquid crystal display device, and FIG. 44 shows a cross-sectional configuration of a typical liquid crystal panel.

As shown in FIG. 43, the liquid crystal display device has a liquid crystal panel 50 for spatially modulating light, a gate drive circuit 51 for selectively driving switching elements in a liquid crystal panel, and a liquid crystal panel 50. Source drive circuit 52 for applying a signal to each pixel electrode of
It comprises a source driver 53 and the like.

As shown in FIG. 44, a liquid crystal panel 50 has a pair of transparent insulating substrates 54 and 55 made of glass, and a liquid crystal layer (for example, a twisted nematic liquid crystal layer) sandwiched between these substrates 54 and 55. ) 38
And a pair of polarizers 56 disposed outside these.

A plurality of pixel electrodes 114 are arranged in a matrix on the side surface of the liquid crystal layer of the substrate 54.
4 and the common transparent electrode 36 on the counter substrate 55, a desired voltage can be applied to a selected portion of the liquid crystal layer 38. The pixel electrode 114 is connected to the source drive circuit 52 via a thin film transistor 110 formed on the substrate 54 and a signal wiring (not shown). The switching operation of the thin film transistor 110 is controlled by the scan wiring formed on the substrate 54. This scanning wiring is connected to the gate driver circuit 51.

On the other hand, a black matrix 35, color filters (R, G, B),
And a common transparent electrode 36.

The liquid crystal layer sides of the substrate 54 and the substrate 55 are both covered with an alignment film 37, and spacers 40 having a diameter of several μm are dispersed in the liquid crystal layer 38.

[0010] The substrate 54 having the above configuration is generally called an "active matrix substrate". On the other hand, the substrate 55 is called a “counter substrate”.

The structure of a conventional active matrix substrate will be described below.

FIG. 45A shows a layout of a unit pixel region in a conventional active matrix substrate, and FIG. 45B shows a cross section taken along line AA '.

In the illustrated example, the glass substrate 121
A plurality of scanning wirings 102 and a plurality of signal wirings 105 intersecting the scanning wirings 102 are provided thereon. The scanning wiring 102 and the signal wiring 105 are located at different layers (layers), and are separated by an insulating film 104 arranged in an intermediate layer between them.

In a rectangular area surrounded by the scanning wiring 102 and the signal wiring 105, a pixel electrode 114 made of a transparent conductive film or the like is formed. The pixel electrode 114 receives a signal charge from the signal wiring 105 via a thin film transistor 110 formed near a portion where the scanning wiring 102 and the signal wiring 105 intersect. An auxiliary capacitance line 113 parallel to the scanning line 102 is formed below the pixel electrode 114, and forms an auxiliary capacitance between the pixel electrode 114 and the auxiliary capacitance line 113.

The thin film transistor 110 is connected to the scanning wiring 10
2, a branch line (gate electrode 103) protruding vertically from the gate electrode 103, a gate insulating film 104 covering the gate electrode 103, an intrinsic semiconductor layer 106 overlapping with the gate electrode 103 via the gate insulating film 104, and on the intrinsic semiconductor layer 106. And a source electrode 108 and a drain electrode 109 connected to the source / drain region of the intrinsic semiconductor layer 106 via the impurity-added semiconductor layer 107. The source electrode 108 is a branch line vertically projecting from the signal wiring 105, and
And are formed integrally with it.

The drain electrode 109 is a conductive member that electrically connects the drain region of the thin film transistor 110 and the pixel electrode 114, and is formed together with the signal wiring 105 and the source electrode 108 by patterning a metal film. That is, in this example, the signal wiring 10
5, the source electrode 108 and the drain electrode 109
They belong to the same layer, and their mutual arrangement is defined by a mask pattern used in a photolithography process.

The source electrode 108 and the drain electrode 109 are connected via a channel region of the intrinsic semiconductor layer 106.
03 is controlled by the potential. Thin film transistor 11
In the case where 0 is an n-channel type, the thin film transistor 110 is turned on by increasing the potential of the gate electrode 103 beyond the inversion threshold of the transistor. At this time, since the source electrode 108 and the drain electrode 109 are electrically connected, electric charges are exchanged between the signal wiring 105 and the pixel electrode 114.

In order for the thin film transistor 110 to operate normally, at least a part of the source electrode 108 and the drain electrode 109 need to overlap the gate electrode 103. Since the line width of the gate electrode 103 is about 10 μm or less, the signal line 105 and the source electrode 10
8 and in the photolithography process for forming the drain electrode 109, it is necessary to perform positioning with respect to the gate electrode 103 already formed on the substrate 121 (hereinafter referred to as "alignment") with high accuracy. is there. Usually, alignment accuracy of ± several μm or less is required.

The gate electrode 103 and the drain electrode 1
09, the area of the overlap region defines the gate-drain capacitance C _gd that affects the display characteristics. If the size of the gate-drain capacitance C _gd varies in the substrate surface, the display quality deteriorates. I do. For this reason, in the actual production process, the alignment accuracy of the exposure apparatus is controlled to ± 1 μm or less, and the alignment deviation is kept as small as possible.

As described above, the alignment accuracy required for manufacturing an active matrix substrate in recent years is extremely high, and an exposure apparatus that meets this requirement has been developed and put into practical use. However, before an exposure device with high alignment accuracy was put to practical use, in order to improve the manufacturing yield,
Devise the layout of the active matrix substrate,
The alignment margin was increased.

FIG. 46 shows a layout of an active matrix substrate proposed in an era when the alignment accuracy of the exposure apparatus was poor. In the illustrated configuration, the drain electrode 109 extends from the pixel electrode 114 in parallel with the signal wiring 105 and crosses the scanning wiring 102. The thin film transistor 110 includes a signal wiring 105 and a scanning wiring 102.
Are formed at and around the intersections of. In this example, neither the scanning wiring 102 nor the signal wiring 105 has a branch line, and the scanning wiring 102 itself functions as a gate electrode, and a part of the signal wiring 105 functions as a source electrode 108.

The active matrix substrate having the above configuration is manufactured as follows.

First, a transparent conductive film 1 is formed on a glass substrate 101.
After sequentially depositing the impurity-added semiconductor layer 107 and the impurity-added semiconductor layer 107, the impurity-added semiconductor layer 107 and the transparent conductive film 161 are patterned using the first mask, and the signal wiring 1
05, a drain electrode 109, and a pixel electrode 114 are formed.

Next, after the intrinsic semiconductor layer 106, the gate insulating film 104, and the metal thin film 102 are sequentially laminated, the second
Metal thin film 102, gate insulating film 10
4 and the intrinsic semiconductor layer 106 are sequentially patterned. Thus, the scanning wiring 102 and the auxiliary capacitance wiring 113 are formed from the metal thin film 102.

According to such a method, even if the position of the later-formed scanning wiring 102 is slightly shifted with respect to the signal wiring 105 and the drain electrode 109 formed first,
Overlapping of the signal wiring 105 and the scanning wiring 102, and
The overlap between the drain electrode 109 and the scanning wiring 102 can be ensured, and the variation of the gate-drain capacitance C _gd can be suppressed.

However, in the structure of FIG. 46, the intrinsic semiconductor layer 106 exists at the lower level of the scanning wiring 102,
It extends linearly so as to cross all the signal lines 105. For this reason, a scanning signal (selection signal) for turning on the thin film transistor 110 is supplied to the scanning wiring 10.
5, the drain electrode 109 shown in FIG.
The semiconductor layer 106 between the drain electrode 109 and the signal wiring 105 located on the left side in the figure not only functions as a channel region of the thin film transistor 110 but also is located on the right side of the drain electrode 109 and the drain electrode 109 in the figure. Semiconductor layer 1 between signal wiring 105
06 also functions as a channel region of the parasitic transistor. For this reason, crosstalk occurs between adjacent pixels on the left and right, and it is not possible to achieve a high display contrast characteristic of an active matrix liquid crystal display device.

In order to solve the above problem, an active matrix substrate having a configuration as shown in FIG. 47 has been proposed (Japanese Patent Application Laid-Open No. 61-108171). The basic structure of this active matrix substrate is the same as the basic configuration of the active matrix substrate shown in FIG. The difference is that the scanning wiring 102 is not provided with a branch line (gate electrode 103), the scanning wiring 102 itself extending linearly functions as a gate electrode, and the drain electrode 109 is parallel to the signal wiring 105. It is at the point where it extends. By employing such a configuration, even if a slight misalignment occurs, the thin film transistor 110 operates normally, and the area of the overlapping region between the drain electrode 109 and the scanning wiring 102 does not change, so that the capacitance C _gd varies. Can be suppressed.

According to the structure of FIG. 47, the alignment margin can be expanded to about 10 to 20 μm. However, most of the exposure apparatuses currently used for manufacturing the active matrix substrate have achieved an alignment accuracy within ± 1 μm.
The structure shown in FIG. 45 is often employed for the purpose of improving the aperture ratio and facilitating correction when a defect occurs, for example, without using the structure of FIG.

A structure has also been proposed in which a pixel electrode is provided on an interlayer insulating film, the pixel electrode and the signal wiring are formed in separate layers, and the pixel electrode is overlaid on the signal wiring (Japanese Patent Laid-Open No. 63-2).
79228 publication). In such a configuration, the pixel electrode and the signal wiring are formed in different layers, and the gap between the pixel electrode and the signal wiring can be eliminated, so that the area (aperture ratio) of the pixel electrode can be increased. The power consumption of the liquid crystal display device can be reduced.

[0030]

In recent years, in order to reduce the weight of electronic equipment, it has been attempted to manufacture a liquid crystal display device using a plastic substrate lighter than a glass substrate instead of a glass substrate.

However, the dimensions of the plastic substrate greatly change during the manufacturing process, and the amount of the change also varies depending on the process, which is a great obstacle to practical use.

The dimensional change rate in the direction parallel to the main surface of the plastic substrate (hereinafter referred to as “substrate expansion / contraction rate”).
Is strongly affected by the processing temperature during the manufacturing process and the amount of moisture absorbed by the plastic substrate. For example, in the case of a glass substrate, the substrate expansion / contraction ratio due to temperature is 3 to 5 ppm /
° C, whereas 50 to 1 for plastic substrates
00 ppm / ° C. In the case of a plastic substrate, the expansion and contraction rate of the substrate due to moisture absorption reaches 3000 ppm.

The substrate expansion / contraction ratio of as much as 3000 ppm is the maximum value that can be generated through all the steps in the manufacturing process. In order to evaluate the actual deviation amount of the mask alignment in the photolithography process, the present inventor actually performs a process of manufacturing a thin film transistor on a plastic substrate, and measures a substrate expansion / contraction ratio generated between two photolithography processes. did. As a result, it was found that substrate expansion and contraction of about 500 to 1000 ppm occurred between photolithography steps requiring mask alignment.

When such expansion and contraction of the substrate occurs on a plastic substrate having a diagonal width of 5 inches, the substrate size becomes 64 μm.
m to 128 μm. If the substrate size fluctuates in such a range, the conventional active matrix substrate manufacturing method cannot manufacture a normally operating thin film transistor.

The present inventor has evaluated the alignment margin which can be realized by the conventional structure shown in FIG. FIG. 48 shows a layout in the case where an alignment margin corresponding to the line width of the signal wiring 105 is given to the basic structure of FIG. Based on this layout, the amount of substrate expansion / contraction that can be handled by the active matrix substrate (diagonal 5 inches) having the conventional structure shown in FIG. 47 was determined by computer simulation. The results are shown in Table 1 below.

[0036]

[Table 1]

As can be seen from Table 1, for example, in an active matrix substrate having pixels with a pixel pitch of 250 μm, only an alignment margin of ± 14 μm or less can be obtained. With such an alignment margin, it is possible to cope only with a substrate expansion / contraction ratio of 220 ppm or less.

As can be seen from the above, as long as the conventional configuration is employed, an active matrix substrate cannot be manufactured using a plastic substrate, and is not easily affected by impact.
The only option is to manufacture an active matrix substrate using a glass substrate whose weight is difficult to reduce.

The present invention has been made in view of the above-mentioned points, and a main object of the present invention is to provide an active matrix substrate which does not cause a problem due to misalignment even when a substrate having a large expansion and contraction rate such as a plastic substrate is used. And a method for manufacturing the same.

Another object of the present invention is to provide an active matrix substrate in which a thin film transistor array is integrated on a plastic substrate.

Still another object of the present invention is to provide a display device manufactured using the above active matrix substrate.

[0042]

An active matrix substrate according to the present invention comprises: a substrate; a plurality of scanning wirings formed on the substrate; a plurality of signal wirings intersecting the scanning wirings via an insulating film; A plurality of thin film transistors formed on the substrate and operating in response to a scan signal on a corresponding scan line; and a plurality of pixel electrodes that can be electrically connected to the corresponding signal line via the thin film transistor. In an active matrix substrate, each pixel electrode and its corresponding thin film transistor are interconnected by a conductive member, and each of the pixel electrode and the conductive member intersects a different adjacent scan line. .

Another active matrix substrate according to the present invention includes a substrate, a plurality of scanning lines formed on the substrate, a plurality of auxiliary capacitance lines, and intersections with the scanning lines and the auxiliary capacitance lines via an insulating film. A plurality of signal wirings, a plurality of thin film transistors formed on the substrate, which operate in response to signals applied to the corresponding scanning wirings, and can be electrically connected to the corresponding signal wirings via the thin film transistors. An active matrix substrate including a plurality of pixel electrodes, each pixel electrode, and a thin film transistor corresponding thereto are connected to each other by a conductive member, the pixel electrode and the conductive member,
It intersects with different adjacent scanning lines and also intersects with different adjacent storage capacitance lines.

An active matrix substrate according to the present invention comprises: a substrate; a plurality of scanning lines formed on the substrate; a plurality of auxiliary capacitance lines; and the scanning line and the auxiliary capacitance line via a first insulating film. A plurality of intersecting signal wires;
A plurality of thin film transistors formed on the substrate and operating in response to a signal applied to a corresponding scan line, and a plurality of lower pixel electrodes that can be electrically connected to the corresponding signal line via the thin film transistor, An active matrix substrate comprising: a plurality of upper pixel electrodes that are disposed on the lower pixel electrode via a second insulating film and are electrically connected to the lower pixel electrode via a contact hole; The signal wiring, the conductive member, and the lower pixel electrode are all formed by patterning the same conductive film, and each pixel electrode and the corresponding thin film transistor are interconnected by a conductive member. The lower pixel electrode and the conductive member each intersect with a different adjacent scanning line, and Intersects with different storage capacitor lines that.

An active matrix substrate according to the present invention comprises: a substrate; a plurality of scanning lines formed on the substrate; a plurality of signal lines intersecting the scanning lines via a first insulating film; A plurality of thin film transistors that are formed in the semiconductor device and operate in response to a signal applied to the corresponding scan wiring; a plurality of lower pixel electrodes that can be electrically connected to the corresponding signal wiring via the thin film transistor; An active matrix substrate, comprising: a plurality of upper pixel electrodes disposed on an upper layer of the lower pixel electrode via an insulating film and electrically connected to the lower pixel electrode via a contact hole; The wiring, the conductive member, and the lower pixel electrode are all formed by patterning the same conductive film, and the lower pixel electrode and the upper pixel The pixel electrode constituted by the poles and the corresponding thin film transistor are connected to each other by the conductive member, and the lower-layer pixel electrode and the conductive member intersect with different adjacent scanning wirings, respectively. .

An active matrix substrate according to the present invention comprises a substrate, a plurality of scanning lines formed on the substrate, a plurality of auxiliary capacitance lines, and a plurality of lines intersecting the scanning lines and the auxiliary capacitance lines via an insulating film. A plurality of thin film transistors formed on the substrate and operating in response to a signal applied to a corresponding scan line, and a plurality of thin film transistors that can be electrically connected to the corresponding signal line via the thin film transistor. An active matrix substrate including a lower pixel electrode and a plurality of upper pixel electrodes that are disposed on the lower pixel electrode via an insulating film and are electrically connected to the lower pixel electrode via a contact hole. So,
The signal wiring, the conductive member, and the lower pixel electrode,
Both are formed by patterning the same conductive film, and the pixel electrode composed of the lower pixel electrode and the upper pixel electrode, and the corresponding thin film transistor are connected to each other by a conductive member, One of the adjacent scanning lines and the auxiliary capacitance lines intersects the lower pixel electrode, and the other intersects the conductive member.

In a preferred embodiment, a source electrode branched from the signal wiring and crossing the scanning wiring is provided, and an intersection between the conductive member and the scanning wiring is formed at an intersection between the signal wiring and the scanning wiring. Portion and the intersection of the source electrode and the scanning line.

In a preferred embodiment, a distance between the signal wiring and the conductive member is substantially equal to a distance between the conductive member and the source electrode.

In a preferred embodiment, the channel portion of the thin film transistor is located substantially at the center of the adjacent signal wiring.

In a preferred embodiment, a channel portion of the thin film transistor is covered by the upper pixel electrode.

In a preferred embodiment, a semiconductor layer of each thin film transistor is formed in a self-aligned manner with respect to the scanning wiring, and the signal wiring and the conductive member are arranged so as to intersect the semiconductor layer. I have.

In a preferred embodiment, the signal wiring and the conductive member are arranged so as to extend over the semiconductor layer, and a channel region of the semiconductor layer is formed in a self-aligned manner with respect to the scanning wiring. Channel is covered by a protective layer.

In a preferred embodiment, of the side surfaces of the channel protective layer, a side surface parallel to a direction in which the signal wiring and the conductive member extend is aligned with a side surface outside the signal wiring and the conductive member.

In a preferred embodiment, of the side surfaces of the channel protective layer, a distance between two side surfaces parallel to a direction in which the scanning wiring extends is smaller than a line width of the scanning wiring.

In a preferred embodiment, the conductive member extends in a direction parallel to the signal wiring from a pixel electrode connected to the conductive member, and extends from the tip of the conductive member to the conductive member. The distance to the opposite end of the pixel electrode connected to is longer than one time of the scanning wiring interval and less than twice the scanning wiring interval.

In a preferred embodiment, the signal wiring, the conductive member, and the pixel electrode all include a conductive layer formed by patterning the same conductive film.

In a preferred embodiment, each of the signal wiring, the conductive member, and the pixel electrode includes a transparent conductive layer formed by patterning the same transparent conductive film. A film having a light-shielding property is arranged on the transparent conductive layer included in the above.

In a preferred embodiment, the light-shielding film is formed of a metal having a lower electrical resistivity than the transparent conductive layer.

In a preferred embodiment, the scanning wiring and the signal wiring do not have a portion projecting in an orientation parallel to the surface of the substrate in the display area.

In a preferred embodiment, the scanning wiring is formed of a light-shielding metal.

[0061] In a preferred embodiment, each of the plurality of scanning lines has a slit-shaped opening through which light can be transmitted, at least in a region where the thin film transistor is formed.

In a preferred embodiment, each of the plurality of scanning wirings is separated into a plurality of wiring portions at least in a region where the thin film transistor is formed.

In a preferred embodiment, the line width of each of the plurality of wiring portions is determined by irradiating the substrate with light from the back side of the substrate after forming a negative photosensitive resin layer covering the scanning wiring. Thereby, when exposing a part of the negative photosensitive resin layer, substantially all of the negative photosensitive resin layer located on the plurality of wiring portions can be exposed by the light diffraction. It is size.

In one preferred embodiment, the substrate and the signal wiring are arranged such that the expansion and contraction of the substrate in a direction parallel to the signal wiring is smaller than the expansion and contraction of the substrate in a direction perpendicular to the signal wiring. Is defined.

In a preferred embodiment, the plurality of scanning wirings extend outside a display area,
The length of the extension of each scanning line is larger than the scanning line pitch.

In a preferred embodiment, a color filter is formed on the pixel electrode.

[0067] In a preferred embodiment, the substrate is formed of plastic.

An active matrix substrate according to the present invention comprises a plastic substrate, a first scanning line formed on the plastic substrate, and a parallel line formed on the plastic substrate and parallel to the first scanning line. And a third scanning line formed on the plastic substrate and arranged in parallel with the second scanning line.
Scan wiring, a signal wiring intersecting with the first to third scanning wirings via an insulating film, a first pixel electrode crossing the first scanning wiring, and a second wiring crossing the second scanning wiring. 2
Pixel electrode, a first thin film transistor formed in self-alignment with the second scan line, and a second thin film transistor formed in self-alignment with the third scan line. The first pixel electrode is connected to the first thin film transistor by a first conductive member that traverses the second scan line, and the second pixel electrode is connected to a second traverse line that crosses the third scan line. Are connected to the second thin film transistor.

A display device according to the present invention includes: the active matrix substrate according to any one of the above, a substrate facing the active matrix substrate, and a light modulation layer positioned between the active matrix substrate and the counter substrate. Have.

A portable electronic device according to the present invention includes the display device.

In the method of manufacturing an active matrix substrate according to the present invention, a step of forming a plurality of scanning lines on a substrate, a step of forming an insulating film covering the scanning lines, and forming a semiconductor layer on the insulating film Forming a positive resist layer on the semiconductor layer, irradiating the substrate with light from the back side of the substrate, thereby exposing the positive resist layer, and then developing the scanning wiring Forming a first resist mask above the scanning wiring, and removing a portion of the semiconductor layer that is not covered by the first resist mask, thereby forming a portion functioning as a semiconductor region of the thin film transistor. Forming a linear semiconductor layer including the self-alignment with respect to the scanning wiring, and removing the first resist mask;
Depositing a conductive film so as to cover the linear semiconductor layer, and patterning the conductive film using a second resist mask to form a signal wiring and a pixel electrode that intersect with the scanning wiring, Extending from the pixel electrode in parallel to the signal wiring, forming a conductive member that intersects with the scanning wiring adjacent to the scanning wiring where the pixel electrode intersects, and further, by patterning the linear semiconductor layer, Forming a semiconductor region of the thin film transistor below the signal wiring and the conductive member.

In a preferred embodiment, the step of forming a semiconductor region of the thin film transistor comprises the step of:
Forming a resist pattern having a relatively thick portion defining the signal wiring and the conductive member and a relatively thin portion defining a gap region between the signal wiring and the conductive member as a resist mask of And a step of etching a portion of the conductive film and the linear semiconductor layer that is not covered with the resist pattern; a step of removing a relatively thin portion of the resist pattern; Etching the portion covered by the relatively thin portion of the resist pattern to form the signal wiring and the conductive member.

Another method for manufacturing an active matrix substrate according to the present invention includes a step of forming a plurality of scanning lines on a substrate, a step of forming an insulating film covering the scanning lines, and forming a semiconductor layer on the insulating film. Forming, and forming a positive resist layer on the semiconductor layer, and irradiating the substrate with light from the back side of the substrate, thereby exposing the positive resist layer, by development, Forming a first resist mask matching the scanning wiring above the scanning wiring, and removing a portion of the semiconductor layer that is not covered by the first resist mask to function as a semiconductor region of the thin film transistor Forming a linear semiconductor layer including a portion in a self-aligned manner with respect to the scanning wiring; removing the first resist mask; Depositing a transparent conductive film so as to cover the transparent conductive film, depositing a light-shielding film on the transparent conductive film, and patterning the light-shielding film and the transparent conductive film using a second resist mask. A signal line and a pixel electrode that intersect with the line are formed, and a conductive member that extends from the pixel electrode in parallel with the signal line and intersects with a scan line adjacent to the scan line with which the pixel electrode intersects is formed. Forming a semiconductor region of the thin film transistor below the signal wiring and the conductive member by patterning the linear semiconductor layer, and applying a negative photosensitive resin material on the substrate; By irradiating the substrate with light from the back side of the substrate, thereby exposing the negative photosensitive resin material, and then developing the non-photosensitive portion Removed by It comprises a step of forming a black matrix.

In a preferred embodiment, when exposing the negative photosensitive resin material, light is transmitted through an area where the scanning wiring and the light-shielding film are not formed.
The negative-type photosensitive resin material located on the signal wiring, the conductive member, and the semiconductor region of the thin film transistor is exposed to light, thereby covering the region where the pixel electrode is not formed with the black matrix.

In a preferred embodiment, a portion of the light shielding film which is not covered by the black matrix is etched to form a light transmitting region on the pixel electrode.

In a preferred embodiment, the step of forming a semiconductor region of the thin film transistor includes the step of:
Forming a resist pattern having a relatively thick portion defining the signal wiring and the conductive member and a relatively thin portion defining a gap region between the signal wiring and the conductive member as a resist mask of And a step of etching a portion of the conductive film and the linear semiconductor layer that is not covered with the resist pattern; a step of removing a relatively thin portion of the resist pattern; Etching the portion covered by the relatively thin portion of the resist pattern to form the signal wiring and the conductive member.

In the method of manufacturing an active matrix substrate according to the present invention, a step of forming a plurality of scanning lines on a substrate, a step of forming an insulating film covering the scanning lines, and forming a semiconductor layer on the insulating film And a step of forming a channel protection layer on the semiconductor layer, a step of forming a first positive resist layer on the channel protection layer, and irradiating the substrate with light from the back side of the substrate, Thereby exposing the first positive resist layer, forming a first resist mask matching the scanning wiring above the scanning wiring by development, and forming the first resist mask over the scanning wiring. Removing a portion not covered by the resist mask, and forming a channel protection layer having a line width smaller than the line width of the scanning wiring in a self-aligned manner with respect to the scanning wiring. Depositing a contact layer so as to cover the channel protective layer and the semiconductor layer, forming a second positive resist layer on the contact layer, and irradiating the substrate with light from the back side of the substrate. Exposing the second positive resist layer thereby,
Forming, by development, a second resist mask aligned with the scanning wiring above the scanning wiring, removing portions of the contact layer and the semiconductor layer that are not covered by the second resist mask, Forming a linear contact layer and a linear semiconductor layer including a portion functioning as a semiconductor region of a thin film transistor in a self-aligned manner with respect to the scanning wiring; removing the second resist mask; Depositing a conductive film so as to cover the contact layer, and patterning the conductive film using a third resist mask to form a signal wiring and a pixel electrode that intersect with the scanning wiring, and Extending from the electrode in parallel with the signal wiring,
By forming a conductive member that intersects with a scanning line adjacent to the scanning line where the pixel electrode intersects, and further patterning the linear contact layer, the channel protective layer, and the semiconductor layer, the signal line and the conductive layer are formed. Forming a semiconductor region of the thin film transistor whose upper surface is partially covered with the channel protective film below the member.

In a preferred embodiment, the step of forming a semiconductor region of the thin film transistor includes the third step.
Forming a resist pattern having a relatively thick portion defining the signal wiring and the conductive member and a relatively thin portion defining a gap region between the signal wiring and the conductive member as a resist mask of And etching a portion of the conductive film, the linear contact layer, the linear channel protective layer, and the linear semiconductor layer that are not covered with the resist pattern, and forming a relatively thin portion of the resist pattern. Removing a portion of the conductive film and the contact layer that is covered by a relatively thin portion of the resist pattern to separate and form the signal wiring and the conductive member. I do.

In the method of manufacturing an active matrix substrate according to the present invention, a step of forming a plurality of scanning lines on a substrate, a step of forming an insulating film covering the scanning lines, and forming a semiconductor layer on the insulating film A step of forming a channel protective layer on the semiconductor layer, a step of forming a positive resist layer on the channel protective layer, and irradiating the substrate with light from the back side of the substrate, thereby Forming a first resist mask aligned with the scanning wiring by development after exposing the positive resist layer, and covering the first resist mask of the channel protection layer with the first resist mask. Forming a channel protection layer in a self-aligned manner with respect to the scanning wiring, and removing a contour so as to cover the channel protection layer and the semiconductor layer. Depositing a conductive layer so as to cover the contact layer, patterning the conductive film using a second resist mask, and forming a signal wiring and a signal wiring crossing the scanning wiring. Forming a pixel electrode, extending from the pixel electrode along the signal wiring, forming a conductive member that intersects with a scanning wiring adjacent to the scanning wiring where the pixel electrode intersects, further comprising the contact layer, Forming a semiconductor region of the thin film transistor whose upper surface is covered with the channel protective film below the signal wiring and the conductive member by patterning the channel protective layer and the semiconductor layer.

In a preferred embodiment, the step of forming a semiconductor region of the thin film transistor includes the step of:
Forming a resist pattern having a relatively thick portion defining the signal wiring and the conductive member and a relatively thin portion defining a gap region between the signal wiring and the conductive member as a resist mask of And etching the portion of the conductive film, the contact layer, the channel protection layer, and the semiconductor layer that is not covered with the resist pattern, and removing a relatively thin portion of the resist pattern; Etching a portion of the conductive film and the contact layer which is covered by the relatively thin portion of the resist pattern to separate and form the signal wiring and the conductive member.

In a preferred embodiment, before forming the contact layer, the semiconductor layer is formed in a self-aligned manner with respect to the scanning wiring by a backside exposure method.

In a preferred embodiment, after removing a relatively thin portion of the resist pattern, a portion of the conductive film and the contact layer which is covered by the relatively thin portion of the resist pattern is etched. Then, the exposed portion of the semiconductor layer is etched to leave a semiconductor region of the thin film transistor below the channel protective layer.

According to still another method of manufacturing an active matrix substrate according to the present invention, there are provided a step of forming a semiconductor film on a substrate, a step of forming a first conductive film on the semiconductor film, By patterning the semiconductor film, a plurality of signal wirings, a plurality of pixel electrodes, and a conductive member extending along the signal wiring from each pixel electrode are formed, and a region between the signal wiring and the conductive member is formed. Leaving the semiconductor film located without removing it, forming an insulating film on the substrate, forming a second conductive film on the insulating film, and patterning the second conductive film. Forming a plurality of scanning wirings intersecting the signal wiring, the pixel electrode and the conductive member, and forming the plurality of scanning wirings in a region between the signal wiring and the conductive member. Chi, comprising a step of etching portions other than the portion located below the scanning line.

In a preferred embodiment, the step of patterning the first conductive film and the semiconductor film includes forming a relatively thick portion defining the signal wiring, the pixel electrode, and the conductive member; Forming a resist mask having a relatively thin portion that defines a region between the conductive member and etching a portion of the first conductive film and the semiconductor film that is not covered with the resist mask; Removing the relatively thin portion from the resist mask, and etching a portion of the first conductive film that is covered by the relatively thin portion of the resist mask. .

The method for manufacturing the active matrix substrate is as follows.
Forming a gate electrode on the substrate, forming a gate insulating film covering the gate electrode, forming a semiconductor layer on the gate insulating film, and forming a positive resist layer on the semiconductor layer And irradiating the substrate with light from the back surface side of the substrate, thereby exposing the positive resist layer, and then developing, by developing, a first resist mask aligned with the gate electrode above the gate electrode. And removing a portion of the semiconductor layer that is not covered by the first resist mask to form a semiconductor layer including a portion functioning as a semiconductor region of the thin film transistor in a self-aligned manner with respect to the gate electrode. Forming; a step of removing the first resist mask; a step of depositing a conductive film so as to cover the semiconductor layer;
By patterning the conductive film using the resist mask, a source electrode and a drain electrode that intersect with the gate electrode are formed, and further by patterning the semiconductor layer, the source electrode and the drain electrode are formed below the source electrode and the drain electrode. Forming a semiconductor region of the thin film transistor.

In a preferred embodiment, the step of forming a semiconductor region of the thin film transistor includes the step of:
Forming a resist pattern having a relatively thick portion defining the source electrode and the drain electrode and a relatively thin portion defining a gap region between the source electrode and the drain electrode as a resist mask of And a step of etching a portion of the conductive film and the semiconductor layer that is not covered with the resist pattern,
Removing the relatively thin portion of the resist pattern, and etching the portion of the conductive film that was covered by the relatively thin portion of the resist pattern to form the source electrode and the drain electrode And

In a preferred embodiment, the source electrode is a part of a signal line extending linearly so as to intersect with the scanning line, and the drain electrode is formed in parallel from the pixel electrode along the signal line. Extending.

According to still another method of manufacturing an active matrix substrate according to the present invention, a step of forming a gate electrode on a substrate, a step of forming a gate insulating film covering the gate electrode, and a step of forming a semiconductor layer on the gate insulating film Forming a channel protective layer on the semiconductor layer; forming a first positive resist layer on the channel protective layer; and applying light to the substrate from the back side of the substrate. Irradiating, thereby exposing the first positive-type resist layer, and then, by developing, the first positive resist layer aligned with the gate electrode.
Forming a resist mask above the gate electrode, removing a portion of the channel protection layer that is not covered by the first resist mask, and self-aligning the channel protection layer with the gate electrode. Arranging, a step of depositing a contact layer so as to cover the channel protective layer and the semiconductor layer, a step of forming a second positive resist layer on the contact layer, and After irradiating the substrate with light and thereby exposing the second positive resist layer, by development,
Forming a second resist mask aligned with the gate electrode above the gate electrode; removing a portion of the contact layer and the semiconductor layer that is not covered by the second resist mask; A step of forming a channel protective layer and a semiconductor layer including a portion functioning as a semiconductor region of the thin film transistor in a self-aligned manner with respect to the gate electrode; a step of removing the second resist mask; and a step of covering the contact layer Forming a conductive film and patterning the conductive film using a third resist mask to form a source electrode and a drain electrode that intersect with the gate electrode. The source electrode and the drain electrode are patterned by patterning the layer and the semiconductor layer. Encompassing a step of the upper surface in the channel protective layer downward to form a partially covered semiconductor region of the thin film transistor was.

In a preferred embodiment, the step of forming a semiconductor layer of the thin film transistor includes forming a relatively thick portion defining the source electrode and the drain electrode as the third resist mask, the source electrode and the drain A step of forming a resist pattern having a relatively thin portion defining a region of a gap between the electrode and
Etching a portion of the conductive film, the contact layer, and the semiconductor layer that is not covered with the resist pattern; removing a relatively thin portion of the resist pattern; Etching a portion of the resist pattern that was covered by a relatively thin portion to separate and form the source electrode and the drain electrode.

In a preferred embodiment, the width of the channel protective layer is set smaller than the width of the semiconductor region.

In the method of manufacturing an active matrix substrate according to the present invention, a step of forming a gate electrode on a substrate, a step of forming a gate insulating film covering the gate electrode, and a step of forming a semiconductor layer on the gate insulating film A step of forming a channel protective layer on the semiconductor layer, a step of forming a positive resist layer on the channel protective layer, and irradiating the substrate with light from the back side of the substrate, thereby Forming a first resist mask aligned with the gate electrode above the gate electrode by developing after exposing the positive resist layer; and covering the channel protective layer with the first resist mask. Removing the unprotected portion and disposing the channel protective layer in a self-aligned manner with respect to the gate electrode; Depositing a contact layer so as to cover the contact layer, depositing a conductive film so as to cover the contact layer, and patterning the conductive film using a second resist mask to intersect the gate electrode. By forming a source electrode and a drain electrode, and further patterning the contact layer, the channel protective layer, and the semiconductor layer, the upper surface was partially covered with the channel protective film below the source electrode and the drain electrode. Forming a semiconductor region of the thin film transistor.

In a preferred embodiment, the step of forming a semiconductor region of the thin film transistor includes the step of:
Forming a resist pattern having a relatively thick portion defining the source electrode and the drain electrode and a relatively thin portion defining a gap region between the source electrode and the drain electrode as a resist mask of Etching a portion of the conductive film, the contact layer, and the semiconductor layer that is not covered by the resist pattern; removing a relatively thin portion of the resist pattern; Etching a portion of the layer that is covered by a relatively thin portion of the resist pattern to separate and form the signal wiring and the conductive member.

In a preferred embodiment, before forming the contact layer, the semiconductor layer is formed in a self-aligned manner with respect to the gate electrode by a backside exposure method.

In a preferred embodiment, after removing a relatively thin portion of the resist pattern, a portion of the conductive film and the contact layer which is covered by the relatively thin portion of the resist pattern is etched. Then, the exposed portion of the semiconductor layer is etched to leave a semiconductor region of the thin film transistor below the channel protective layer.

A thin film transistor according to the present invention is formed over a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and above the gate electrode via the gate insulating film. Semiconductor layer, a source electrode formed to intersect with the semiconductor layer, and a drain electrode formed to intersect with the semiconductor layer, of the side surface of the semiconductor layer, the source electrode and The side surface parallel to the direction in which the drain electrode extends matches the outer side surface of the source electrode and the drain electrode.

In a preferred embodiment, of the side surfaces of the semiconductor layer, a side surface parallel to a direction in which the gate electrode extends is aligned with a side surface of the gate electrode.

In a preferred embodiment, a contact layer is provided between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer.

A thin film transistor according to the present invention is formed above a gate electrode via a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and the gate insulating film. Semiconductor layer, a channel protection layer formed on the semiconductor layer, a source electrode formed to intersect the channel protection layer, and a drain electrode formed to intersect the channel protection layer. And a side surface of the side surface of the channel protective layer parallel to a direction in which the source electrode and the drain electrode extend is aligned with a side surface outside the source electrode and the drain electrode.

In a preferred embodiment, of the side surfaces of the channel protective layer, a distance between two side surfaces parallel to a direction in which the gate electrode extends is smaller than a line width of the gate electrode.

In a preferred embodiment, of the side surfaces of the semiconductor layer, a side surface parallel to a direction in which the gate electrode extends is aligned with a side surface of the gate electrode.

In a preferred embodiment, of the side surfaces of the semiconductor layer, a side surface parallel to a direction in which the source electrode and the drain electrode extend is aligned with a side surface outside the source electrode and the drain electrode.

In a preferred embodiment, a contact layer is provided between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer.

[0103]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of an active matrix substrate according to the present invention will be described with reference to FIGS.

First, reference is made to FIG. FIG. 1 is a plan view schematically showing a layout configuration of an active matrix substrate 100 in the present embodiment.

This active matrix substrate 100
It has an insulating substrate (hereinafter, referred to as a “plastic substrate”) 1 made of a plastic material such as polyethersulfone (PES), and a thin film transistor array structure formed on the plastic substrate 1.

On the plastic substrate 1, a plurality of scanning lines 2 and signal lines 5 are arranged so as to be orthogonal to each other. The scanning wiring 2 and the signal wiring 5 belong to different layers, and are electrically insulated and separated by an insulating film provided in an intermediate layer. FIG. 1 shows seven scanning lines 2 and eight signal lines 5 for simplicity, but a large number of scanning lines 2 and signal lines 5 are actually arranged.

In a region where the scanning wiring 2 and the signal wiring 5 intersect, a thin film transistor not shown in FIG. 1 is formed. The pixel electrode 14 electrically connected to the signal wiring 5 via the thin film transistor is arranged so as to pass over the scanning wiring 2.

Next, reference is made to FIG. FIG. 2 is a layout diagram in which a part of the display area of the active matrix substrate 100 is enlarged, and shows two pixel areas belonging to the same pixel column.

The conductive member 9 extends from the pixel electrode 14 arranged so as to pass over the scanning wiring 2 in a direction parallel to the signal wiring 5 (Y-axis direction). The conductive member 9 functions as a drain electrode of the thin film transistor 10, and the pixel electrode 14 and the thin film transistor 10
And are electrically interconnected.

In this embodiment, each thin film transistor 10
Are formed in a self-aligned manner with respect to the scanning wiring 2, and the signal wiring 5 and the conductive member (drain electrode) 9 are arranged so as to extend over the semiconductor layer. A drain electrode 9 connected to an arbitrary thin film transistor 10 and a pixel electrode 14 connected to the drain electrode 9 traverse adjacent separate scanning lines 2. In the example shown in FIGS. 1 and 2,
When the scanning wiring 2 is selectively driven sequentially from the + Y side to the −Y side, the pixel electrode 14 is disposed at a position intersecting the scanning wiring 2 which is first selectively driven. The extended drain electrode 9 is arranged so as to intersect the scanning wiring 2 that is to be selectively driven next. In this case, an auxiliary capacitance is formed between the pixel electrode 14 and the scanning wiring 2 overlapping therewith. The driving method of the scanning wiring is not limited to the line-sequential driving that proceeds from the + Y side to the -Y side. For example, the interlaced driving that proceeds from the + Y side to the -Y side, or the A line-sequential drive that proceeds toward the center may be employed.

Next, reference will be made to FIGS. 3 (a) to 3 (c). FIG. 3A is a sectional view taken along line AA ′ of FIG.
FIG. 3B is a sectional view taken along line BB ′ of FIG. 2. FIG. 3 (c)
3 is a perspective view schematically showing a scanning wiring 2 and semiconductor layers 6 and 7 of a thin film transistor 10 located thereon.

As shown in FIG. 3A, the thin film transistor 10 of this embodiment has a scanning line 2 functioning as a gate electrode, a gate insulating film 4,
It has a stacked structure including an intrinsic semiconductor layer 6 and an impurity-added semiconductor layer 7. Intrinsic semiconductor layer 6 of the present embodiment
Is made of non-doped amorphous silicon, and the impurity-doped semiconductor layer 7 is made of n ⁺ microcrystalline silicon doped with an n-type impurity such as phosphorus (P) at a high concentration. The signal wiring 5 and the drain electrode 9 are electrically connected to the source region and the drain region of the semiconductor layer 6 via the impurity-added semiconductor layer 7 functioning as a contact layer, respectively. As is clear from this, in the present embodiment, a part of the signal wiring 5 extending linearly (a part intersecting with the scanning wiring 2) functions as the source electrode 8 of the thin film transistor 10.

As shown in FIG. 3C, the semiconductor layer 6
Region 3 between source region S and drain region D
1 functions as a channel region, and the impurity-added semiconductor layer 7 does not exist on the upper surface of the channel region 31. In the present embodiment, a channel-etch type bottom gate thin film transistor is employed, and the upper surface of the channel portion of the semiconductor layer 6 is thinly etched when the impurity-added semiconductor layer 7 is removed.

In this embodiment, of the side surfaces of the semiconductor layers 6 and 7, the side surface parallel to the direction in which the scanning wiring 2 extends is “aligned” with the side surface of the scanning wiring 2. Such a configuration can be realized by a self-alignment process performed using a backside exposure method, as described later. Further, it is “matched” with the other side surfaces of the semiconductor layers 6 and 7, the side surfaces outside the signal wiring 5 and the drain electrode 9. Such a configuration can be realized by patterning the signal wiring 5 and the drain electrode 9 and patterning the underlying semiconductor layers 6 and 7 using the same mask, as described later. Note that “matching” in the present specification is not only when the position of a pattern edge belonging to a certain layer completely coincides with the position of a pattern edge belonging to another layer, but also when the position is shifted to some extent. Is widely included. This “displacement” does not occur due to misalignment of the mask. For example, when a pattern of a plurality of layers is sequentially formed using a common mask (such as a resist mask), the side etch amount in each layer is reduced. It can be caused by changing.

In consideration of the above, “matching” in this specification means a state in which patterns belonging to different layers have an arrangement relationship that is not affected by misalignment of the mask.

FIG. 3 is a sectional view taken along the line BB 'of FIG.
Referring to (b), it can be seen that the semiconductor layers 6 and 7 also exist on the scanning wiring 2 in the region where the pixel electrode 14 is formed. However, the semiconductor layers 6 and 7 in the region where the pixel electrode is formed are the same as those in FIG.
As is apparent from FIG. 3C, the semiconductor layers 6 and 7 constituting the thin film transistor 10 are separated from each other and do not perform the transistor operation. Therefore, crosstalk does not occur between pixels belonging to the same row (scanning wiring).

In the present embodiment, the signal wiring 5, the drain electrode 9, and the pixel electrode 14 are all formed of a transparent conductive layer obtained by patterning a single transparent electrode film. 9 and all of the pixel electrodes 14 belong to the same layer. The signal line 5, the drain electrode 9, and the pixel electrode 14 are covered with a protective insulating film 11, and a color filter 33 is provided thereon.
Is provided.

Referring back to FIG.

The drain electrode 9 connecting the pixel electrode 14 to the thin film transistor 10 is connected to the pixel electrode 1 as described above.
4 extends in parallel with the signal wiring 5 and intersects with the scanning wiring 2 for selectively driving (switching) the thin film transistor 10 to be connected to the drain electrode 9. The drain electrode 9 is laid out so as not to intersect with the corresponding scanning line other than the scanning line 2. That is, the tip of the drain electrode 9 (the end on the −Y direction side in FIG. 2).
The distance between the pixel electrode 14 and the opposite edge of the pixel electrode 14 (the end on the + Y direction side in FIG. 2) is set to be longer than one time and less than twice the scanning wiring distance. On the other hand, in the conventional active matrix substrate, as shown in FIG. 27A, the distance between the tip of the drain electrode 9 and the opposite edge of the pixel electrode 14 is not more than one time the scanning wiring interval.

Next, the configurations of the drain electrode 9 and the pixel electrode 14 will be described in more detail with reference to FIG.

The illustrated drain electrode 9 has a portion (connecting portion 15) that protrudes short from the −X side and −Y side corner of the pixel electrode 14 toward the signal wiring 5, and a connecting portion 15.
And a portion (extended portion 16) extending long in a direction parallel to the signal wiring 5 (-Y side). If the distance between the −Y side end of the drain electrode 9 and the −Y side end of the pixel electrode 14 connected to the drain electrode 9 is defined as “the length (L _d ) of the drain electrode 9”, the drain electrode the length L _d of 9 is shown as equation 1 below. L _d = P _pitch −DD _gap −Y _con (Equation 1) Here, P _pitch is a pixel pitch, DD _gap is a _gap between drain electrodes, and Y _con is a width of the connection portion 15.

After a plurality of scanning wirings 2 are formed at a predetermined interval on the plastic substrate 1, even if the plastic substrate 1 greatly expands and contracts and the actual scanning wiring pitch shows an unpredictable fluctuation, the configuration shown in FIG. According to the signal wiring 5,
When the drain electrode 9 and the pixel electrode 14 are patterned, they can be aligned so as to intersect the scanning wiring 2 reliably.

The scanning wiring 2 and the drain electrode 9 (the pixel electrode 1
4) The margin required for the alignment between
The length L of the electrode 9_dThe larger the is, the wider it is. Pixel pick
Chi-P_{p itch}Assuming a constant
Length L of pole 9_dIn order to increase_gapAnd Y
_conShould be as small as possible. But DD_gapAnd
Y_conThe lower limit of the
Specified and limited by lithography and etching techniques
There is a world. Each of the pixel electrodes 14 is reliably separated, and
In order to avoid narrowing or disconnection of the connection portion 15, use
It is necessary to secure a sufficient etching margin in the
is there.

Normally, the gap between pixel electrodes (PP _gap )
Is to be set as small as possible in view of aperture ratio improvement, to maximize the length L _d of the drain electrode 9, the drain electrode gap DD _gap between the pixel electrode gap P
What is necessary is _just to set it as the magnitude _| size equal to P _gap . When set as described above, the following equation 2 is established. L _d = P _pitch −PP _gap −Y _con (Equation 2)

FIG. 2 shows a layout in the case where Equation 2 is substantially satisfied.
_d does not need to have a value determined by Expression 2, but may have a value that can secure a necessary alignment margin.

The size Y _pix of the pixel electrode 14 measured along the X axis is expressed by the following equation (3). Y _pix = P _pitch -PP _gap (Equation 3)

In the case of FIG. 2, the following equation 4 is established from the equations 2 and 3. L _d = Y _pix −Y _con (Equation 4)

The scanning wiring 2 and the drain electrode 9 (the pixel electrode 1
4) is equal to the scanning margin 2
Where G _width is G _width , it is expressed by the following equation 5. ΔY = L _d -PP _gap -G _width (Equation 5)

After performing the step of forming the scanning wiring 2,
Until the lithography process for forming the drain electrode 9 (pixel electrode 14) is performed, the plastic substrate 1
If it is known whether or not is stretched or shrunk, it is preferable to give the largest alignment margin to the pixel located at the end (upper end or lower end) in the display area.

FIG. 4A shows an example of the arrangement when the plastic substrate 1 extends. In the arrangement example of FIG. 4A, the thin film transistor 10 and the scanning wiring 2 of the pixel located at the end on the −Y side in the display area overlap with the vicinity of the edge 9E of the drain electrode 9. In the case of FIG. 4A, since the scanning wiring pitch becomes larger than the pixel pitch due to the extension of the plastic substrate 1, the intersection of the scanning wiring 2 and the drain electrode 9 is closer to the pixel located in the + Y direction, and the corresponding drain It shifts away from the edge 9E of the electrode 9. However, according to the configuration of the present embodiment,
Since a sufficient alignment margin ΔY is provided to absorb the shift at the intersection, the scanning line 2 and the drain electrode 9 (pixel electrode 14) are not connected to the pixel (not shown) located at the + Y side end in the display area. A proper intersection is ensured between.

On the other hand, FIG. 4B shows an example of the arrangement when the plastic substrate shrinks. In the arrangement example of FIG. 4B, the scanning wiring 2 of the pixel located at the end on the −Y side in the display area is overlapped with the vicinity of the edge 14 </ b> E of the pixel electrode 14. In the case of FIG. 4B, since the scanning wiring pitch becomes smaller than the pixel pitch due to the contraction of the substrate, the intersection between the scanning wiring 2 and the pixel electrode 14 is closer to the pixel located in the + Y direction. 14 away from the edge 14E. However, according to the configuration of the present embodiment, a sufficient alignment margin ΔY for absorbing the shift at the intersection is provided, so that + Y in the display area is provided.
Also at the pixel (not shown) located at the side end, a proper intersection between the scanning wiring 2 and the drain electrode 9 (pixel electrode 14) is ensured.

In order to cope with both expansion and contraction of the plastic substrate 1, as shown in FIG. 5, near the center of the plastic substrate 1, the center of the drain electrode 9 and the center line of the scanning wiring are arranged. And try to match as much as possible. This makes it possible to cope with both expansion and contraction of the plastic substrate 1.

At this time, the alignment margin ± Δy
Is represented by Equation 6 below. ± Δy = ± (ΔY / 2−dY) (Equation 6) Here, dY is the alignment accuracy of the exposure apparatus.

As described above, according to the layout adopted in the present embodiment, even if the scanning wiring pitch increases / decreases due to expansion and contraction of the plastic substrate 1, there is a large alignment margin that can cope with this. The thin film transistor 10 can be manufactured at any position on the upper side, and variations in transistor characteristics and parasitic capacitance in the substrate can be reduced.

As described above, since the signal wiring 5, the drain electrode 9, and the pixel electrode 14 are all formed by patterning the same transparent conductive film, the signal wiring 5, the drain electrode 9, and the Pixel electrode 14
It is not necessary to consider the misalignment of the arrangement relationship.

In a conventional active matrix substrate, in order to reduce the parasitic capacitance at the intersection between the scanning wiring 2 and the signal wiring 5, it is general to provide a constriction at the intersection of the wiring as shown in FIG. . However, in the present embodiment, as shown in FIG. 2, a configuration is employed in which the concave portions and the convex portions are not provided on the side surfaces of the scanning wiring 2 and the signal wiring 5 in the display area. By doing so, even if the misalignment occurs between the scanning wiring 2 and the signal wiring 5, the gate-drain capacitance C _{gd of} the thin film transistor 10, the ON current, the capacitance at the intersection of the scanning wiring and the signal wiring, and the auxiliary capacitance And other characteristic changes.

Next, a method for manufacturing the active matrix substrate 100 will be described in detail with reference to FIG. 6 and FIGS. 7A to 7C. 6 is a plan view showing two pixel regions in main process steps, and FIGS. 7A and 7B are process cross-sectional views showing a cross section taken along line AA ′ and a cross section taken along line BB ′ of FIG. .

First, as shown in FIG. 6A and FIG. 7A, a plurality of scanning lines 2 are formed on a plastic substrate 1.
To form The scanning wiring 2 is formed by using a sputtering method or the like.
For example, it is obtained by depositing a tantalum (Ta) film having a thickness of about 200 nm on the plastic substrate 1 and then patterning the Ta film by a photolithography and etching process. The pattern of the scanning wiring 2 is defined by a mask (first mask) used in the photolithography. The width of the scanning wiring 2 is indicated by the above G _width ,
For example, it can be set to about 4.0 to 20 μm. On the other hand, the pitch of the scanning lines 2 (scanning line pitch) can be set to, for example, about 150 to 400 μm in the above-described photolithography step. It should be noted that the scanning wiring pitch is not changed during the subsequent manufacturing process.
Expands and contracts under the influence of heat and moisture.
Until a photolithography step for forming the above is performed, the set value fluctuates by about 500 to 1000 ppm.

Next, as shown in FIG. 7B, a gate insulating film (thickness: 200 to 50) made of silicon nitride (SiN _x ) is formed by chemical vapor deposition (CVD).
4) is deposited on the plastic substrate 1 to completely cover the scanning wiring 2 and then a non-doped amorphous silicon layer (intrinsic semiconductor layer, thickness of about 100 to 200 nm) 6 and n-type such as P (phosphorus) An impurity-doped semiconductor layer (with a thickness of about 10 to 50 nm) 7 doped with an impurity is laminated on the gate insulating film 4. The intrinsic semiconductor layer 6 may be formed from polycrystalline silicon, microcrystalline silicon, or the like, instead of being formed from amorphous silicon. Further, a small amount of impurities may be inevitably mixed into the semiconductor layer 6.

Next, as shown in FIG. 7C, a positive resist film 90 is applied on the impurity-added semiconductor layer 7 by a photolithography process, and then the resist film 90 is applied from the back side of the plastic substrate 1 to the resist film 90. Irradiate light (backside exposure). At this time, since the scanning wiring 2 having a light shielding function functions as one kind of optical mask, the resist film 90 is formed.
Of the portion located directly above the scanning wiring 2 is not exposed,
A portion located above a region where the scanning wiring 2 does not exist is exposed. Thereafter, by performing development, a resist mask 90 having a plane layout similar to the plane layout of the scanning wiring 2 is formed on the scanning wiring 2 as shown in FIG. 7D. By sequentially etching the impurity-added semiconductor layer 7 and the intrinsic semiconductor layer 6 using the resist mask 90, the semiconductor layers 6 and 7 can be formed on the scanning wiring 2 in a self-aligned manner (FIG. 7A).
(E)).

FIG. 6B shows an upper surface shape of the impurity-added semiconductor layer 7 formed on the scanning wiring 2. The intrinsic semiconductor layer 6 and the scanning wiring 2 Is located. At this stage, the semiconductor layers 6 and 7 are not divided for each pixel, and extend in a straight line on the scanning wiring 2. It should be noted that a difference between the width of the scanning wiring 2 and the width of the semiconductor layers 6 and 7 can be given by adjusting the exposure conditions and the etching conditions.

In this embodiment, since the semiconductor layer is patterned by using the above-described backside exposure method, the thin film transistor 10 is arranged on the scanning wiring 2 (FIG. 2).
reference). Normally, when a semiconductor layer for a thin film transistor is formed after forming a scanning wiring, alignment of the semiconductor layer pattern with respect to the scanning wiring needs to be performed with high accuracy. It is difficult to produce a thin film transistor array on a plastic substrate. On the other hand, if the backside exposure method is adopted as in the present embodiment, the alignment between the pattern of the semiconductor layer 6 and the scanning wiring 2 becomes unnecessary, so that it is not necessary to consider the alignment margin.

The scanning wiring material of this embodiment is not limited to Ta, but may be any conductive material having a light-shielding property. The light-shielding property is necessary to adopt the backside exposure method. As a scanning wiring material other than Ta, the electric resistance is relatively low and the compatibility with the manufacturing process is excellent,
Al, Mo / Al, TiN / Al / Ti, TaN / Ta
A laminated film such as / TaN or an Al-based alloy can be suitably used.

Next, after removing the resist film 90 on the impurity-added semiconductor layer 7, as shown in FIG. 7A, a transparent substrate made of indium-tin-oxide (ITO) is formed on the uppermost surface of the plastic substrate 1. A conductive film 91 is deposited.
The material of the transparent conductive film 91 is not limited to ITO, and may be any conductive material that can sufficiently transmit visible light. For example, a transparent conductive film made of IXO may be used.

Thereafter, by patterning the transparent conductive film 91 in a photolithography and etching process, the signal wiring 5, the drain electrode 9,
And a pixel electrode 14 are formed. The layout of the signal wiring 5, the drain electrode 9, and the pixel electrode 14 is defined by a mask (second mask) used in the photolithography process. Hereinafter, the patterning process performed using the second mask will be described in detail.

First, in the photolithography step, FIG.
A resist mask 92 as shown in FIG. 7C and FIG. 7B (b) is formed. The illustrated resist mask 92
Indicates a relatively thick resist portion (thickness: 1.5 to 5) that defines the shapes of the signal wiring 5, the drain electrode 9, and the pixel electrode 14.
(A thickness of about 3.0 μm) 92 a and a relatively thin resist portion (thickness: about 0.3 to 1.0 μm) 92 b that defines a region between the signal wiring 5 and the drain electrode 9.

The structure of the resist mask 92 will be described in more detail with reference to FIGS. FIG.
(A) is a partially enlarged view showing a part of the resist mask 92, and shows an enlarged region including the signal wiring 5, the end of the drain electrode 9, and the corner of the pixel electrode 14. 8 (b), (c) and (d) correspond to FIG.
It is CC 'line sectional drawing, DD' line sectional drawing, and EE 'line sectional drawing of (a). FIG. 9 is a schematic perspective view of the resist mask shown in FIG.

The resist mask 92 irradiates an appropriate amount of light to a portion of the resist film located in a region between the signal wiring 5 and the drain electrode 9 when exposing the resist film applied to the substrate 1 to light. (Half exposure method). Such exposure can be realized by using a light interference effect if a slit pattern is formed at an appropriate position on the optical mask.

In this embodiment, first, the transparent conductive film 9 is formed by using the resist mask 92 having such a special shape.
1. The impurity-added semiconductor layer 7 and the intrinsic semiconductor layer 6 are sequentially etched. FIG. 7C shows a cross section at the stage when this etching is completed. At this stage, since the channel region 31 of the thin film transistor 10 is covered with the relatively thin portion 92b of the resist mask 92, the transparent conductive film 91 and the impurity-added semiconductor layer 7 on the channel region 31 are not etched at all. Therefore, the semiconductor layer 6 which has been in a line shape is separated into islands by the above-described etching.
In the transparent conductive film 91, the part to be the signal wiring 5 and the part to be the drain electrode 9 remain unseparated.

Next, the resist mask 92 is thinned by, for example, ashing (ashing) the surface portion of the resist mask 92 using oxygen plasma, and the channel portion of the thin film transistor 10 is formed as shown in FIG. The resist portion 92b that covers 31 is removed. When oxygen plasma ashing is performed to reduce the thickness of the resist mask 92, the side surfaces of the resist mask 92 are also ashed to the extent of the thickness of the thin resist portion 92b. However, since the thickness of the thin resist portion 92b is about 0.3 to 1.0 μm, the dimension shift amount due to ashing is also 0.3 to 1.0.
It is about 0 μm. Since the variation in the dimension shift amount within the substrate surface is about ± 20% or less, the variation of the finished dimension is also about ± 0.2 μm at the maximum, but the channel width of the transistor is about 5 to 10 μm. Has little effect on properties. FIG. 10 is a partial perspective view of the resist mask 92 after ashing.

After removing the thin resist portion 92b covering the channel region 31 of the thin film transistor 10, the transparent conductive film 91 and the impurity-added semiconductor layer 7 are etched again. From this, FIG.
And the structure shown in FIG. 7B (e) can be obtained. This etching removes an intermediate portion of the transparent conductive film 91 between the portion to be the signal wiring 5 and the portion to be the drain electrode 9, so that the separated signal wiring 5 and drain electrode 9 are transparent. Conductive film 91
Formed from During this etching, the impurity-added semiconductor layer 7 located on the channel region 31 is also removed, and the exposed surface of the intrinsic semiconductor layer 6 is also partially etched. Thereafter, when the resist mask 92 (92a) is removed, a configuration shown in FIG. 7C (a) is obtained (FIG. 3).
(C)).

In the present embodiment, as described above, first, when patterning the transparent conductive film 91, the linear (linear) semiconductor layers 6 and 7 located in the intermediate layer between the transparent conductive film 91 and the scanning wiring 2 are formed. Each pixel is separated and patterned into an island shape (FIG. 6C). Then, the signal wiring 5 and the drain electrode 9 are completely separated by a self-aligned process, and the thin film transistor 10 is completed. By employing such a method, the semiconductor layers 6 and 7 can be self-aligned with the signal wiring 5 and the drain electrode 9, and the mask layer and the semiconductor layer that define the signal wiring 5 and the drain electrode 9 can be formed. 6 does not need to be aligned with the mask layer that defines 6.

Next, as shown in FIG. 7B, after covering the thin film transistor 10 with the protective film 11, a color filter 33 is formed on the pixel electrode 14 by an electrodeposition method.
When a color filter is formed on the counter substrate side as in the related art, the position of the color filter with respect to the pixel electrode 14 is greatly shifted due to expansion and contraction of the plastic substrate, so that a normal image cannot be displayed. In this embodiment,
In order to solve such a problem, the color filter 33 is formed on the pixel electrode 14 in a self-aligned manner. Hereinafter, FIG.
The electrodeposition formation of the color filter performed in the present embodiment will be described with reference to FIG.

In order to form three color filters of red (R), green (G), and blue (B) by the electrodeposition method, it is necessary to perform three electrodeposition steps for different colors. is there.
In the present embodiment, the switching circuit 57 shown in FIG. 11 is arranged in the periphery of the display area of the active matrix substrate, and the switching circuit 57 is used to selectively perform electrodeposition for each color. The switching circuit 57 includes a thin film transistor and a wiring, which are manufactured by using a process for manufacturing a wiring and a thin film transistor in a display region.

First, the case where a red color filter is electrodeposited will be described. In this case, an on signal (for example, “logic High”) of the thin film transistor is input to the control signal line Rs of the switching circuit 57, and the other control signal line B
An off signal (for example, “logic low”) is input to s and Gs. Then, a voltage V for causing an electrodeposition reaction is applied to the switching circuit 57. At this time, a signal for turning on the thin film transistor in the display area is input to each scanning wiring 2 in advance. As a result, the voltage V is applied to the array 58 of the pixel electrodes for displaying red, and the red paint is electrodeposited on the pixel electrodes in the array 58. At this time, the color filter 33 is also formed on the signal wiring 5 and the drain electrode 9 to which the voltage V is applied.
(B)).

For the color filters of other colors, by repeating the same steps as the electrodeposition step, the green paint is electrodeposited on the pixel electrodes of the array 59 for displaying green, and blue should be displayed. A blue paint is electrodeposited on the pixel electrodes of the array 60. Thus, three color filters can be formed in a self-aligned and selective manner with respect to the pixel electrode 14. According to this method, the color filters 33 of three colors are arranged in a stripe shape.

When the color filter 33 is formed from an insulating material, the effective voltage that can be applied to the liquid crystal layer during operation of the liquid crystal display device decreases. In order to prevent such a decrease in the effective voltage, in the present embodiment, a color filter is formed from a conductive material.

As described above, in this embodiment, the number of photolithography steps requiring mask alignment is reduced to two by employing many self-alignment processes. Therefore, the influence of the expansion and contraction of the substrate affects only the mask alignment in the subsequent photolithography step with respect to the pattern formed in the previous photolithography step in the two photolithography steps. Then, by making the structures of the drain electrode 9 and the pixel electrode 14 novel as shown in FIG. 2, even when the plastic substrate 1 expands and contracts greatly, the connection between the semiconductor layer 6 of the thin film transistor 10 and the drain electrode 9 is ensured. It becomes possible.

Since the plastic substrate greatly expands and contracts unlike the case of a glass substrate, when mask alignment is performed using a mark similar to a conventional alignment mark, alignment marks between different layers are superimposed on each other. Can not be done. Therefore, in the present embodiment, alignment markers 120a and 120b having a pattern as shown in FIG. 12 are employed. In the example shown in FIG. 12, the marker 120a formed by the first mask has a size of about twice (or more) the alignment margin Δy shown in Expression 6 (or more).
It consists of a dimensional scale pattern. And
The marker 120b formed by the second mask is composed of a pattern (for example, a cross-shaped pattern) in which the marker formed by the first mask is clearly located.

[0160] Such an alignment marker 120a
And 120b, the amount of positional deviation between the pattern formed by the second mask and the pattern formed by the first mask is read, and the position of the second mask is adjusted based on the amount of deviation. For example, the mask alignment may be performed so that the displacement amounts of the two alignment markers 120a and 120b shown in FIG.

(Example) An example of the active matrix substrate was prototyped using a 5-inch diagonal plastic substrate (thickness: about 0.2 mm) made of PES. In this embodiment, the size of one pixel region is set to 300 μm × 100 μm.
m, 10 [mu] m width G _width of the scanning lines, 5 [mu] m gap PP _gap between the pixel electrodes, 5 [mu] m width Y _con of the connecting portion, the drain electrode length L _d was 290 [mu] m. The alignment accuracy of the exposure apparatus used was ± 5 μm. From Expression 5, ΔY = 290-5-10 = 275 [μm] is obtained.

In this embodiment, the center of the drain electrode and the center of the scanning wiring are made to substantially coincide with each other at the center of the substrate so as to cope with both expansion and contraction of the plastic substrate. As a result, the alignment margin of this embodiment is ± 1.
32.5 μm (Δy = ΔY / 2−dY = 13
7.5-5 = 132.5 [μm]).

The pattern (marker) formed on the plastic substrate by the first mask was shifted by 42 μm on one side with respect to the marker by the second mask when performing the lithography process using the second mask. This pattern shift corresponds to a substrate contraction of 661 ppm. However, in this example, since there was an alignment margin of ± 132.5 μm, a normally operating thin film transistor was manufactured at any position on the substrate, and functioned as an active matrix substrate without any problem.

On the other hand, in the case of the conventional structure shown in FIG.
The allowable limit of substrate expansion / contraction is only ± 14 μm, and an active matrix substrate cannot be manufactured using a plastic substrate.

In the structure according to the present invention and the conventional structure, the alignment margin Δy with respect to each pixel pitch is described in Table 2 below, and a graph produced based on Table 2 is shown in FIG.

[0166]

[Table 2]

The graph of FIG. 13 shows the relationship between the alignment margin (substrate expansion / contraction margin) Δy and the pixel pitch. As can be seen from the graph, according to the present embodiment,
A large margin not obtained in the conventional example can be obtained, and the plastic substrate can be used even if the pixel pitch is considerably shortened.

As described above, according to the present embodiment, even if a substrate that can expand and contract to exceed 500 ppm during a photolithography process requiring alignment is used, the color filter layer is included. Since the elements of all layers can be formed in an appropriate arrangement relationship,
An active matrix liquid crystal display device using a plastic substrate can be realized.

In the case of manufacturing a liquid crystal display device using the active matrix substrate of the present embodiment, if a normally white type liquid crystal is used, the backlight light leaks out through the transparent signal wiring and its vicinity. More specifically, backlight light leaks from the region of the signal wiring 5, the region between the signal wiring 5 and the drain electrode 9, the region between the adjacent pixel electrodes 14, and the region between the adjacent drain electrodes 9, The contrast of the displayed image decreases. On the other hand, if the display operation is performed in the normally black mode,
The region between the pixel electrode 14 to which no voltage is applied, the adjacent drain electrode 9, and the region between the adjacent pixel electrodes 14 are displayed in black, and the signal wiring 5 to which an average voltage is applied. Becomes a halftone, so that a decrease in display contrast can be suppressed.

(Second Embodiment) In the first embodiment, I
By patterning a transparent conductive film such as TO,
Since the signal line 5, the drain electrode 9, and the pixel electrode 14 are formed, the signal line 5, which does not need to be transparent, is formed of a transparent conductive film similarly to the pixel electrode 14. Generally, the resistivity of the transparent conductive film is higher than the resistivity of the metal film, and the resistivity of ITO is 200 to 400 μΩcm.
For this reason, when the signal wiring is formed from ITO, if the signal wiring 5 is too long, the signal transmission is likely to be delayed. Therefore, it is considered that the size of the active matrix substrate 100 in the first embodiment is limited to about 5 inches diagonally.

Further, when a black matrix is provided on the opposite substrate of the active matrix substrate 100, a positional shift is likely to occur between the opening portion of the black matrix and the pixel electrode 14 due to expansion and contraction of the plastic substrate. For this reason, if no black matrix is provided,
External light may irradiate the thin film transistor 10 and increase off-leak current. When the off-leak current of the thin film transistor 10 increases, the holding voltage to be applied to the liquid crystal layer by the pixel electrode 14 and the counter electrode decreases, so that the contrast of the displayed image decreases. Further, when the black matrix is not provided, the backlight leaks out through the transparent signal wiring and its vicinity as described above, so that the display operation in the normally white mode cannot be performed. Even if the operation is performed in the normally black mode, the contrast slightly decreases on the signal wiring 5.

Therefore, in the present embodiment, in order to solve these problems, a black matrix is arranged on an active matrix substrate in a self-aligned manner.

Hereinafter, a second embodiment of the active matrix substrate according to the present invention will be described with reference to FIGS. FIG. 14 is a plan view showing a layout of the active matrix substrate 200 according to the present embodiment. FIG. 15A is a cross-sectional view taken along the line AA ′ of FIG. 14, and FIG. 14 is a sectional view taken along line BB ′ of FIG.

As is apparent from the figure, the basic configuration of the active matrix substrate 200 in the present embodiment is the same as the basic configuration of the active matrix substrate 100 in the first embodiment, except for the following points. That is, the features of the present embodiment are as follows.

(1) The black matrix 35 is arranged so as to cover the region where the pixel electrode 14 is not formed and the periphery of the pixel electrode 14 (FIG. 14). That is, the signal wiring 5, the scanning wiring 2, the thin film transistor 10,
A gap region between the signal wiring 5 and the drain electrode 9, a gap region between the drain electrode 9 and the pixel electrode 14, an adjacent pixel electrode 1
All of the gap region 4 and the gap region between the adjacent drain electrodes 9 are shielded from light by the black matrix 35.

(2) The black matrix 35 is formed of a negative photosensitive material, and is patterned by backside exposure.

(3) The color filter 33 has a region where the black matrix 35 is not formed.
(FIG. 15A and FIG. 15B).

(4) A metal film 93 made of Ta is formed on the signal line 5 made of ITO and the drain electrode 9 (FIG. 15A).

The resistivity of Ta is 2 compared to the resistivity of ITO.
Since it is as low as 5 to 40 μΩcm, the metal film 93 made of Ta
Are integrated with the signal wiring 5 to function as “low resistance wiring”. For this reason, the signal transmission speed can be improved as compared with the case where the wiring is formed only from a transparent conductive film such as ITO, and according to the present embodiment, the diagonal size of the active matrix substrate is increased to 10 inches or more. It becomes possible to do.

In the case where the main purpose is the light-shielding effect of the black matrix 35 and the purpose is not to reduce the resistance of the wiring, instead of providing a metal film such as Ta on the transparent conductive layer, a black resin material or the like is used. The light-shielding material layer may be arranged on the transparent conductive layer. Each of the metal film / insulating layer having a light shielding function functions as an optical mask necessary for patterning the black matrix 35 in the manufacturing method described below.

Hereinafter, a method for manufacturing the active matrix substrate 200 will be described in detail with reference to FIGS. FIG. 16 is a plan view showing two pixel regions in main process steps, and FIG.
FIG. 4 is a process cross-sectional view showing a cross section taken along line AA ′ and a cross section taken along line BB ′ of FIG.

First, as shown in FIGS. 16A and 17A, a plurality of scanning wirings 2 are formed on a plastic substrate 1.
To form The scanning wiring 2 is obtained by depositing a metal film such as aluminum (Al) or Ta on the plastic substrate 1 using a sputtering method or the like, and then patterning the metal film by a photolithography and etching process. The pattern of the scanning wiring 2 is defined by a mask (first mask) used in the photolithography.

Next, as shown in FIGS. 16 (b) and 17 (b), the intrinsic semiconductor layer 6 self-aligned with the scanning wiring 2 is formed.
Then, an impurity-added semiconductor layer 7 is formed on the scanning wiring 2 via the gate insulating film 4. At this time, a backside exposure method is used as in the first embodiment. Although only the impurity-added semiconductor layer 7 is shown in FIG. 16B, the intrinsic semiconductor layer 6 and the scanning wiring 2 are located immediately below the impurity-added semiconductor layer 7.

Next, the upper surface of the plastic substrate 1 is made of ITO.
After sequentially depositing a transparent conductive film 91 made of, for example, and a light-shielding metal film 93 made of Ta or the like, a resist mask 92 is formed as shown in FIG. Resist mask 9
Reference numeral 2 designates a relatively thick portion 92a defining the signal line 5, the drain electrode 9 and the pixel electrode 14, and a region between the signal line 5 and the drain electrode 9, as in the first embodiment. And a relatively thin portion 92b.

Next, using the resist mask 92, the light-shielding metal film 93, the transparent conductive film 91, the impurity-added semiconductor layer 7, and the intrinsic semiconductor layer 6 are sequentially etched. FIG.
(C) and FIG. 17 (c) show the configuration at the stage when this etching is completed. At this stage, the channel region 31 of the thin film transistor 10 is
2, the metal film 93, the transparent conductive film 91, and the impurity-added semiconductor layer 7 in the channel region are not etched at all. That is, in the transparent conductive film 91, the part to be the signal wiring 5 and the part to be the drain electrode 9 remain unseparated.

Next, after removing the resist portion 92b covering the channel region 31 of the thin film transistor 10 by, for example, oxygen plasma ashing, the metal film 93, the transparent conductive film 91 and the impurity-added semiconductor layer 7 are etched again. Do. Thus, the structure shown in FIGS. 16D and 17D can be manufactured. At this stage, the metal film 93 forms the signal wiring 5 and the drain electrode 9.
Not only on the pixel electrode 14 but also on the pixel electrode 14. To manufacture a transmissive display device, a light-shielding metal film 93 is required.
It is necessary to selectively remove a portion located on the pixel electrode 14 among them. The light-shielding metal film on the pixel electrode 14 is removed after forming a black matrix by the method described below.

As shown in FIG. 17E, after a transparent protective film 11 is deposited on the uppermost surface of the plastic substrate 1, a negative photosensitive black matrix film is applied on the protective film 11. The photosensitive black matrix film is irradiated with light from the back side of the substrate 1 (backside exposure). At this time, since the pattern of the light-shielding metal film 93 functions as one kind of optical mask, a relatively large portion of the photosensitive black matrix film located above the pixel electrode 14 is hardly exposed. On the other hand, since the light-shielding metal film 93 covering the signal wiring 5 and the drain electrode 9 has a small line width, the light-shielding metal film 93 is exposed by a diffraction phenomenon of light emitted from the back surface of the substrate.

After the above backside exposure, the unexposed portion of the photosensitive black matrix film is removed by performing development, as shown in FIGS. 16 (e) and 17 (e). A black matrix 35 having openings of substantially the same shape above the pixel electrode 14 is formed.

Thereafter, using the black matrix 35 as an etching mask, the protective film 11 and the light-shielding metal film 93 in a region exposed through the opening of the black matrix 35 are etched. By this etching, the light-shielding metal film 93 existing on the pixel electrode 14 is removed. Thereafter, the color filter 33 is formed by the electrodeposition method, and the configuration shown in FIG.

According to the present embodiment, since the upper surface of the signal wiring 5 made of a transparent conductive layer is backed with a metal film having a lower resistivity than the transparent conductive layer, the entire signal wiring including the metal film is included. Electrical resistance (wiring resistance) is reduced, and a large-sized liquid crystal display device having a diagonal size of 5 inches or more can be realized.

In this embodiment, the black matrix is provided on the active matrix substrate side,
The display characteristics can be greatly improved. Specifically, since the thin film transistor in the display region is covered with the black matrix, off-state current leakage of the transistor due to external light irradiation is suppressed, and a decrease in contrast due to such current leakage is prevented. Further, by providing the black matrix, unnecessary leakage of backlight light is suppressed, and a decrease in contrast due to light leakage is also prevented.

(Third Embodiment) Hereinafter, a third embodiment of the active matrix substrate according to the present invention will be described with reference to FIGS. FIG. 18 is a plan view schematically showing a layout of the active matrix substrate 300 according to the present embodiment, and FIGS.
(D) is a figure for demonstrating patterning of the black matrix by back surface exposure.

As can be seen from FIG. 18, the basic configuration of the active matrix substrate 300 according to the present embodiment is the same as the basic configuration of the active matrix substrate 200 according to the second embodiment except for the scanning lines 2.

The characteristic part of this embodiment is that the scanning wiring 2 is branched into a plurality of wiring parts 2a to 2c, and the width of each wiring part 2a to 2c is set to 6 to 7 μm. Since the semiconductor layer 6 of the thin film transistor 10 is self-aligned with the scanning wiring 2, the semiconductor layer 6 is also divided into three according to the wiring portions 2a to 2c. For this reason, in the present embodiment, three thin film transistors are arranged for each pixel, and they are connected in parallel between the signal wiring 5 and the drain electrode 9. The same scanning signal is input to the plurality of wiring portions 2a to 2c constituting the scanning wiring 2, and the three thin film transistors responsive thereto perform the same switching operation.

Hereinafter, the reason why each scanning wiring is branched into a plurality of parts will be described.

According to the backside exposure method employed in the first and second embodiments, the width of the scanning wiring 2 is reduced
Specifies a channel width of 0. Since the on-state current of the transistor is proportional to the channel width, the width of the scanning wiring 2 may need to be increased in order to obtain a necessary on-state current. The required ON current varies depending on the size and driving method of the pixel electrode 14, but the size of the pixel electrode 14 is 300 μm.
In the case of about × 100 μm, the channel width is 10 to 20 μm
Need to be designed.

However, if the width of the scanning wiring 2 exceeds 10 μm, when patterning the black matrix 35 by using the backside exposure method, diffracted light is generated by the scanning wiring 2.
Can't get around to the upper part of the center. FIG. 19 (a)
This point will be described with reference to FIGS. FIG.
FIGS. 9A and 9B are plan views showing the shape of the black matrix 35 in the thin film transistor formation region, and FIGS. 19C and 19D respectively show FIGS.
It is FF 'line sectional drawing of (a) and (b).

If the width of the scanning wiring 2 is too wide, the diffracted light emitted from the back side of the substrate does not reach the negative photosensitive black matrix film located at the center of the scanning wiring 2. Above, a non-photosensitive portion of the black matrix film occurs. As a result, after development, FIG.
As shown in (a) and (c), only the area within a few μm from the edge of the scanning wiring 2 is covered by the black matrix 35, and the central part of the scanning wiring 2 cannot be covered by the black matrix 35. In such a black matrix 35, irradiation of external light to the thin film transistor 10 cannot be prevented, and the off-state current of the thin film transistor 10 increases.

On the other hand, in the example of FIG. 19B, the scanning wiring 2 is divided into two wiring portions 2a to 2b, and a slit is formed between the wiring portion 2a and the wiring portion 2b during back surface exposure. It functions as an opening in the shape of a circle, and expands an exposure area by light passing through the opening and its diffracted light. Therefore, as shown in FIG. 19D, the upper part of the scanning wiring 2 is completely covered by the black matrix 35.

In the photosensitive resin film located on the light-shielding pattern, the portion located about 4 μm inside from the edge of the light-shielding pattern is also exposed to the diffracted light, so that the width of the scanning wiring 2 is about 8 μm or less. If so, it is not particularly necessary to divide the scanning wiring 2 into a plurality of parts. However, it is considered that it is preferable to set the wiring width to at most about 6 to 7 μm in consideration of a change in the wiring width due to a change in the manufacturing process parameter.

Referring back to FIG. In the configuration shown in FIG. 18, each scanning line 2 has three wiring portions 2a to 2c.
Is divided into The width of each wiring portion 2a-2c is 6-7
When set to μm, the effective width (= channel width) of the scanning wiring 2 becomes 18 to 21 μm.

Also in this embodiment, since the semiconductor layers 6 and 7 are self-aligned with the scanning wiring 2, the semiconductor layer 7 is also divided into three according to the wiring portions 2a to 2c. For this reason, three thin film transistors are arranged for each pixel,
They are in a state of being connected in parallel between the signal wiring 5 and the drain electrode 9. The same scanning signal is input to the plurality of wiring portions 2a to 2c constituting the scanning wiring 2, and the three thin film transistors responsive thereto perform the same switching operation, so that an increase in on-current can be achieved.

In the example shown in FIG. 18, the scanning wiring 2 is divided into three wiring portions, but the present invention is not limited to this. One scanning line to which the same signal is input may be divided into two or four or more lines. Note that the scanning wiring 2 may have a single wiring shape in an area other than the display area. For example, in a region where the scanning wiring is connected to the driver circuit, it is preferable that a plurality of wiring portions receiving the same signal be connected to one wiring.

The scanning wiring 2 may be separated into a plurality of wiring portions at least in a region where the semiconductor layer 6 of the thin film transistor 10 is formed. For example, the scanning wiring 2 is separated into a plurality of portions in a region where the pixel electrode 14 is arranged. It doesn't have to be. However, because the plastic substrate 1 expands and contracts, an array displacement occurs in the X-axis direction. Therefore, the planar shape of the scanning wiring is preferably uniform regardless of the position in the display area.

As described above, according to the present embodiment, even when the effective line width of the scanning wiring 2 is increased, the black matrix 35 that completely covers the thin film transistor 10 can be formed.

In this embodiment, the black matrix 35
Although a light amplification type photosensitive material is used as the material for the above, a chemically amplified type photosensitive material may be used instead.
In the case of a chemically amplified photosensitive material, there is an advantage that the amount of the black matrix 35 penetrating into the light-shielding pattern can be easily increased because the reaction proceeds from a portion irradiated with the light even if the light is not directly applied.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the active matrix substrate according to the present invention will be described with reference to FIGS. FIG. 20 is a plan view showing two pixel regions in main process steps for manufacturing the active matrix substrate 400 of the present embodiment. FIG. 21 is a cross-sectional view taken along line AA ′ of FIG. It is a process sectional view showing a 'line section.

In the first to third embodiments described above, the impurity-doped semiconductor layer 7 is directly deposited on the intrinsic semiconductor layer 6 to separate the signal wiring 5 functioning as a source electrode from the drain electrode 9. In addition, not only the surface of the intrinsic semiconductor layer 6 but also the surface of the intrinsic semiconductor layer 6 was etched. In the present embodiment, a channel protective layer is disposed between the intrinsic semiconductor layer 6 and the impurity-added semiconductor layer 7 so that the channel region of the intrinsic semiconductor layer 6 is not etched.

The basic structure of the active matrix substrate 400 in this embodiment is shown in FIGS.
As can be seen from (f), the basic configuration of the active matrix substrate 100 in the first embodiment is the same as that of the first embodiment except that a channel protective layer 95 is provided between the intrinsic semiconductor layer 6 and the doped semiconductor layer 7. . Since the function of the channel protective layer 95 is exhibited during the manufacturing process, a method for manufacturing the active matrix substrate 400 according to the present embodiment will be described in detail below.

First, as shown in FIGS. 20 (a) and 21 (a), a plurality of scanning lines 2 are formed on a plastic substrate 1.
To form The scanning wiring 2 is obtained by depositing a metal film such as AlNd or Ta on the plastic substrate 1 using a sputtering method or the like, and then patterning the metal film by a photolithography and etching process. The pattern of the scanning wiring 2 is defined by a mask (first mask) used in the photolithography.

Next, as shown in FIGS. 20 (b) and 21 (b), after depositing the intrinsic semiconductor layer 6 and the channel protective layer 95 on the substrate 1 via the gate insulating film 4, the back surface exposure method To form a channel protection layer 95 self-aligned with the scanning wiring 2 on the scanning wiring 2. At this time, patterning of the intrinsic semiconductor layer 6 is not performed, and only the channel protection layer 95 is patterned. Channel protection layer 95
Can be preferably formed from a SiN _x film having a thickness of about 200 nm. In the present embodiment, the exposure conditions and the etching conditions are adjusted so that the line width of the channel protection layer 95 is smaller than the line width of the scanning wiring 2 by about 1 to 4 μm. As a result, the position of each edge of the channel protection layer 95 is about 0.5 to 2 μm inside the corresponding edge of the scanning wiring 2. By increasing the side etching amount of the channel protection layer 92, the line width of the scanning wiring 2 and the channel protection layer 9 are increased.
In order to increase the difference from the line width of No. 5, it is preferable to use isotropic etching such as wet etching.

Next, the channel protective layer 9 is formed by the CVD method.
After depositing the impurity-added semiconductor layer 7 so as to cover the intrinsic semiconductor layer 6 and the intrinsic semiconductor layer 6, the intrinsic semiconductor layer 6 and the impurity-added semiconductor layer 7, which are self-aligned with the scanning wiring 2, are again deposited by the backside exposure method. Form on top. FIG. 20 (c)
1 shows only the impurity-added semiconductor layer 7, the channel protection layer 95, the intrinsic semiconductor layer 6, and the scanning wiring 2 are located directly below the impurity-added semiconductor layer 7. However, the width of the channel protection layer 95 is formed to be smaller than the line width of the intrinsic semiconductor layer 6 and the scanning wiring 2. Here, the “width” of the channel protection layer 95 refers to the width of the channel protection layer 95.
The distance between the two side surfaces parallel to the direction in which the scanning wiring 2 extends is shown.

Next, the upper surface of the plastic substrate 1 is made of ITO.
After depositing a transparent conductive film 91 made of
As shown in (c), a resist mask 92 is formed.
As in the case of the first embodiment, the resist mask 92 has a relatively thick portion 92 a defining the signal wiring 5, the drain electrode 9, and the pixel electrode 14, and a region between the signal wiring 5 and the drain electrode 9. Relatively thin portion 92b defining
And

Next, using the resist mask 92, the transparent conductive film 91, the impurity-added semiconductor layer 7, the channel protective layer 95, and the intrinsic semiconductor layer 6 are sequentially etched. FIG. 20D and FIG. 21D show the configuration at the stage when this etching is completed. At this stage, the channel region of the thin film transistor 10 is
2, the transparent conductive film 91 in the channel region is not etched at all.

Next, after removing the resist portion 92b covering the channel region of the thin film transistor 10 by, for example, oxygen plasma ashing, the transparent conductive film 91 and the impurity-added semiconductor layer 7 are etched again. During this etching, the channel protective layer 95 located at the lower level of the impurity-added semiconductor layer 7 functions as an etch stop layer, and protects the channel region of the intrinsic semiconductor layer 6 from etching. From this, FIG.
The structure shown in FIG. 21E can be manufactured. Next, a protective film 11 is formed on the uppermost surface of the plastic substrate 1.
Is deposited, and a color filter 33 is formed by an electrodeposition method to obtain a configuration shown in FIG.

According to the present embodiment, a mask for patterning the signal wiring 5 and the drain electrode 9 is used.
Wiring-shaped channel protection layer 95 located on scanning wiring 2
Are separated for each pixel. Therefore, the channel protection layer 9
5 is not only self-aligned with the scanning wiring 2 but also self-aligned with the signal wiring 5 and the drain electrode 9. More specifically, of the four side surfaces of the channel protection layer 95, two side surfaces parallel to the direction in which the signal wiring 5 and the drain electrode 9 extend are aligned with the outer side surfaces of the signal wiring 5 and the drain electrode 9. .

As a result, an alignment shift does not occur between the channel protection layer 95 and the signal wiring 5 or the drain electrode 9, and a channel protection type thin film transistor array can be manufactured on a substrate which is easily expanded and contracted.

As described above, in the present embodiment, it is not necessary to give a large alignment margin to the channel protective layer 95. Further, among the side surfaces of the channel protection layer 95, the distance between two side surfaces parallel to the direction in which the scanning wiring 5 extends is smaller than the line width of the scanning wiring 5. Can be formed without any contact area.

(Fifth Embodiment) A fifth embodiment of the active matrix substrate according to the present invention will be described with reference to FIGS. In the drawings, members corresponding to the above-described embodiment are denoted by the same reference numerals.

First, reference is made to FIG.

FIG. 22 is a plan view schematically showing a layout configuration of an active matrix substrate 500 according to the present embodiment. In the present embodiment, unlike the first to fourth embodiments, the space between the adjacent scanning lines 2 (for example, the line G
The storage capacitor line (Com) 20 is arranged between the scanning line 2 and the scanning line 2 (between 1 and the line G2). Auxiliary capacitance wiring 2
0 belongs to the same layer as the scanning wiring 2 and is formed of the same material as the material of the scanning wiring. Further, in the pixel region of the active matrix substrate 500, the auxiliary capacitance line 20 also has a straight wiring shape without a projection like the scanning line 2. FIG. 22 shows seven scanning wirings 2, seven auxiliary capacitance wirings 20, and eight signal wirings 5 for simplicity, but a large number of wirings are actually arranged.

Next, reference is made to FIG. FIG. 23 is a layout diagram in which a part of the display area of the active matrix substrate 500 is enlarged.

A conductive member 9 extends from the pixel electrode 14 arranged so as to pass over the scanning wiring 2 and the auxiliary capacitance wiring 20 in a direction parallel to the signal wiring 5 (Y-axis direction). The conductive member 9 functions as a drain electrode of the thin film transistor 10, and electrically connects the pixel electrode 14 and the thin film transistor 10.

In this embodiment, each thin film transistor 10
Is formed in a self-aligned manner with respect to the scanning wiring 2, and the signal wiring and the conductive member (drain electrode) 9 are arranged so as to extend over the semiconductor layer. The semiconductor layer is also formed on the auxiliary capacitance line 20 in a self-aligned manner, and physically forms a thin film transistor. However, a signal for turning off the parasitic thin film transistor is always input to the auxiliary capacitance line 20. As a result, the parasitic thin film transistor does not function as a switching element.

The drain electrode 9 connected to an arbitrary thin film transistor 10 and the pixel electrode 14 connected to the drain electrode 9 traverse adjacent separate scanning lines 2 and auxiliary capacitance lines 20.

When the active matrix substrate is applied to a liquid crystal display device or the like, it is desirable to suppress a change in pixel potential due to the gate-drain capacitance C _gd of the thin film transistor in order to improve display characteristics and reduce power consumption. . The change amount ΔV of the pixel potential due to C _gd is ΔV = C _gd /
(C _gd + C _cs + C _lc ) · V _gpp

Here, C _cs is the auxiliary electrode capacitance (scanning line 2
C _lc is a liquid crystal capacitance, and V _gpp is a potential difference when a signal on the scanning wiring 2 is turned on and off. Since V _gpp and C _lc are determined by the material used and the basic characteristics of the device, it is conceivable that ΔV is reduced by increasing the auxiliary capacitance C _cs . However,
When the alignment-free structure is adopted, increasing the auxiliary capacitance _Ccs by increasing the width of the scanning wiring 2 leads to increasing _Cgd at the same time.
For this reason, it is not preferable to control ΔV by adjusting the width of the scanning wiring 2. For example, it is assumed that the width G _{width of the} scanning wiring is increased by a factor of K in order to increase the auxiliary capacitance C _cs . Since the auxiliary capacitance C _cs is proportional to the width G _{width of the} scanning wiring,
_{cs ′} = K · C _cs On the other hand, since the gate-drain capacitance C _gd is also proportional to the width G _{width of the} scanning wiring, C _{gd ′} = K
_-It becomes _Cgd . Therefore, the pull-in voltage ΔV ′ is expressed by the following equation (7).

ΔV ′ = K · C _gd / (K · C _gd + K · C _cs + C _lc ) = C _gd / (C _gd + C _cs + C _lc / K) (Equation 7)

As is clear from the equation 7, the larger the K, the larger the pull-in voltage ΔV '.
In Equation 7, when K is reduced, the pull-in voltage ΔV ′
Is also smaller. However, the minimum line width of the scanning wiring 2 is determined due to restrictions in the manufacturing process and the like, and it is difficult to sufficiently reduce the pull-in voltage ΔV ′ by reducing K.

Therefore, in this embodiment, an auxiliary capacitance is formed between the auxiliary capacitance line 20 and the pixel electrode 14 in addition to the capacitance between the scanning line 2 and the pixel electrode 14. By adjusting the width of the auxiliary capacitance line 20, the pull-in voltage ΔV can be reduced.

In the present embodiment, in order to increase the margin for the expansion and contraction of the substrate, it is preferable to make the interval between the scanning wiring 2 and the auxiliary capacitance wiring 20 that cross the same pixel electrode 14 as small as possible.

Next, reference will be made to FIG. 24 and FIG. FIG. 24 is a sectional view taken along line AA ′ of FIG. 23, and FIG.
FIG. 24 is a sectional view taken along line BB ′ of FIG. 23.

As shown in FIG. 24, the thin film transistor 10 of this embodiment comprises, in order from the lower level, the scanning wiring 2, the gate insulating film 4, the intrinsic semiconductor 6, and the impurity-added semiconductor layer 7 functioning as a gate electrode. It has a laminated structure including: The intrinsic semiconductor 6 of this embodiment is formed of non-doped amorphous silicon, and the impurity-doped semiconductor layer 7 is formed of n ⁺ microcrystalline silicon doped with an n-type impurity such as phosphorus (P) at a high concentration. I have. The signal wiring 5 and the drain electrode 9 are electrically connected to the source region and the drain region of the semiconductor layer 6 via the impurity-added semiconductor layer 7 functioning as a contact layer, respectively. As is apparent from this, in the present embodiment, a part of the signal wiring 5 extending linearly (a part intersecting with the scanning wiring 2) functions as the source electrode S of the thin film transistor 10.

As shown in FIG. 24, of the semiconductor layer 6, a region 31 between the source region S and the drain region D functions as a channel region, and an impurity-doped semiconductor layer 7 is formed on the upper surface of the channel region 31. Does not exist. In the present embodiment, a channel-etch bottom gate thin film transistor is employed, and the upper surface of the channel portion of the semiconductor layer 6 is
The etching is thin when the impurity-added semiconductor layer 7 is removed.

It can be seen that the semiconductor layers 6 and 7 also exist on the scanning wiring 2 in the region where the pixel electrode 14 is formed. However, as is clear from FIG. 24, the semiconductor layers 6 and 7 in the region where the pixel electrode is formed
And 7 and do not perform transistor operation. Therefore, crosstalk does not occur between pixels belonging to the same row (scanning wiring).

The sectional structure on the auxiliary capacitance line 20 is the same as the sectional structure on the scanning line 20. Also here, since the semiconductor layer 6 exists between the signal wiring 5 and the drain electrode 9, a thin film transistor is parasitically formed. However, a voltage of about −8 to −15 V is always applied to the auxiliary capacitance wiring. Therefore, the parasitic transistor does not enter a conductive state (on state). Therefore, the signal wiring 5 and the drain electrode 9 are electrically separated.

In the present embodiment, all of the signal wiring 5, the drain electrode 9, and the pixel electrode 14 are formed of a conductive layer obtained by patterning one reflection electrode film.
All of the signal wiring 5, the drain electrode 9, and the pixel electrode 14 belong to the same layer. The signal wiring 5, the drain electrode 9, and the pixel electrode 14 are covered with the protective insulating film 11.

An alignment margin ΔY between the scanning line 2 and the auxiliary capacitance line 20 and the drain electrode 9 (pixel electrode 14) is expressed by the following equation (8).

ΔY = L _d −PP _gap −G _width −W _cs −CG _gap = P _pitch −G _width −PP _gap −W _cs −GC _gap −DD _gap −Y _con (Equation 8) where G _width is The width of the scanning line 2, _Wcs is the width of the auxiliary capacitance line 20, and the GC _gap is the interval between the scanning line and the auxiliary capacitance line 20.

As described above, according to the layout employed in this embodiment, even if the pitch of the scanning wirings increases or decreases due to expansion and contraction of the plastic substrate, there is a large alignment margin that can cope with the increase or decrease. A thin film transistor that operates normally at any position can be manufactured, and variations in transistor characteristics and parasitic capacitance in a substrate can be reduced. As described above, since the signal wiring 5, the drain electrode 9, and the pixel electrode 14 are all formed by patterning the same transparent conductive film or reflective electrode material film, the signal wiring 5, the drain electrode 9, and the drain electrode 9 are formed. 9 and the arrangement relationship of the pixel electrodes 14, there is no need to consider an alignment deviation.

Example An example of the active matrix substrate was prototyped using a 5-inch square plastic substrate (0.2 mm thick) made of PES. The panel size is 3.9 inches diagonally and the resolution is 1/4 VGA (320 ×
RGB × 240). The size of one pixel area is 82μ.
m × 246 μm, the width G _width of the scanning line 2 is 8 μm, the _gap between pixel electrodes PP _gap is 5 μm, the width Y _{con of the} connection portion is 5 μm, the width W _cs of the auxiliary capacitance line is 25 μm, and the auxiliary capacitance line 20 and the scanning line 2 The gap between the GC _gap is 10μ
m, and the gap DD _gap between the drain and 5μm,
ΔY = 246-8-5-25-10-5-5 = 188 μ
m.

In this embodiment, the plastic substrate is arranged so that ΔY1 = ΔY2 at the center of the substrate so as to cope with both expansion and contraction of the plastic substrate. As a result, the alignment margin ΔY between the scanning wiring layer and the source wiring / lower pixel electrode layer was ± 91 μm (ΔY = ΔY).
/ 2-dY, where dY is 3 which is the accuracy of the alignment device.
μm).

Since the length of the display area in the ΔY direction is 240 (lines) × 246 (μm) = 59040 (μm), the allowable substrate expansion / contraction margin between the two layers is 1
541 ppm. In this prototype, 500-700
Although the substrate expanded and contracted by about ppm, since there was a sufficient alignment margin, the thin film transistors operated normally in all the pixel regions and functioned as an active matrix substrate without any problem.

Table 2 below shows the substrate expansion / contraction margin for each pixel pitch in the structure according to the present invention and the conventional structure. The size of the display area is 4 inches diagonally (81.2
mm × 61 mm), and it is assumed that the scanning wiring terminals are arranged on the short sides.

[0245]

[Table 3]

The positioning accuracy of the exposure apparatus is ± 3 μm.
m.

(Sixth Embodiment) In the first to fifth embodiments, since the pixel electrode 14 and the signal wiring 5 are on the same layer, the alignment margin can be increased. However, the size of the pixel electrode 14 is limited due to the presence of the signal wiring, and the aperture ratio (the ratio of the pixel electrode to the pixel region in the reflective liquid crystal display device) cannot be increased.

A liquid crystal display device using a plastic substrate is expected to be applied to a reflection type liquid crystal in order to make use of the lightness and thinness of the substrate. In a reflective liquid crystal display device, 70
It is said that a sufficient visibility cannot be obtained unless the aperture ratio is not less than%. Therefore, in the conventional reflection type liquid crystal display device on a glass substrate, the pixel electrode 14 and the signal wiring 5 are arranged on a separate layer, and the gap between the pixel electrode 14 and the signal wiring 5 is eliminated, so that the opening of 80 to 90% is obtained. Rate is secured.

In the structures of the first to fifth embodiments, 30 to 5
Since only an aperture ratio of about 0% can be obtained, in the second embodiment shown in FIG. 26, the pixel electrode 14 has a two-layer structure. That is, the pixel electrode 14 is constituted by the upper pixel electrode 14A functioning as a reflective electrode and the lower pixel electrode 14B forming an auxiliary capacitance. The upper pixel electrode 14A is arranged on a different layer from the signal wiring 5 via an insulating film, and the lower pixel electrode 14B is arranged on the same layer as the signal wiring 5. By doing so, the alignment margin can be increased without lowering the aperture ratio.

The present embodiment will be described below with reference to FIGS. 26 is a plan view showing a layout of the active matrix substrate 600 in the present embodiment, FIG. 27 is a sectional view taken along line AA ′ of FIG. 26, and FIG. 28 is a sectional view taken along line BB ′ of FIG. FIG.

As is clear from the figure, the configuration of the active matrix substrate in this embodiment is the same as the configuration of the active matrix substrate in the fifth embodiment below the lower pixel electrode 14B.

An interlayer insulating film is arranged on the lower pixel electrode 14 B, drain electrode 9 and signal line 5.
14A is an upper layer pixel electrode made of a reflective electrode material such as AL. A contact hole is formed in a part of the lower pixel electrode 14B, and the upper pixel electrode 14B
A and the lower pixel electrode 14B are electrically connected.
Since the upper pixel electrode 14A has a larger area than the lower pixel electrode 14B, the aperture ratio can be increased. Further, since the auxiliary capacitance is formed between the lower pixel electrode 14B, the auxiliary capacitance wiring 20, and the scanning wiring 2, it is not necessary to control the alignment between the upper pixel electrode 14A and the scanning wiring layer.

Therefore, an alignment margin ΔY between the first mask for defining the scanning wiring and the second mask for defining the source wiring 5 and the pixel electrode 14B in the lower layer.
Is not different from the size of the alignment margin in the fifth embodiment. Therefore, ΔY is represented by the following equation.

ΔY = P _pitch −G _width −PP _gap −W _cs
-GC _gap -DD _gap -Y _con

Since the contact hole 21 and the upper pixel electrode 14B are formed in the upper layer of the lower pixel electrode 14B, it is necessary to consider an alignment margin also in these layers.

The contact hole 21 must always be arranged on the lower pixel electrode 14B. Assuming that the width of the contact hole is _Wch , a third mask defining the contact hole 21 layer and a second mask defining the lower pixel electrode 14B are provided.
The alignment margin between the mask and the other mask is represented by the following equation.

ΔC = P _ss −W _s −W _d −3 · SD _gap −W _ch where P _ss is the source wiring pitch, W _s is the width of the source wiring, W _d is the width of the drain electrode, and SD _gap is the width of the drain electrode. This is the gap between the source and drain.

Although there is a restriction on the expansion and contraction of the substrate also in the ΔY direction between the second mask and the third mask, it is ignored because it is sufficiently larger than ΔC. Since the expansion and contraction of the plastic substrate is substantially the same in the vertical and horizontal directions, if the margin of ΔC is satisfied, the margin in the ΔY direction should be satisfied.

Since the upper pixel electrode 14A needs to be formed on the contact hole 21, the upper pixel electrode 14A
The alignment margin between the fourth mask defining the layer and the third mask defining the contact hole 21 is ΔΔ
P = P _{ss -PP tgap} . Here, _PPtgap is a gap between the upper-layer pixel electrodes 14A.

Next, the manufacturing process of this embodiment will be described.

As can be seen from the drawing, the first to first lines up to the signal line 5, the drain electrode 9, and the pixel electrode 14B in the lower layer.
The same manufacturing process as the manufacturing process described in the fifth embodiment can be adopted. Thin film transistor 1
The structure of 0 may be either a channel protective film type or a channel etch type. In the present embodiment, a channel etch type is adopted.

After depositing an interlayer insulating film 21 made of an inorganic insulating film or an organic insulating film on the thin film transistor,
The contact hole 22 is formed by a photolithography process. The thickness of the interlayer insulating film 21 is, for example, 0.5 to 3 μm.

In the above-mentioned insulating film deposition step, it is necessary to select a material or a film forming method that causes less expansion and contraction of the substrate. In general, the organic insulating film has less expansion and contraction of the substrate than the inorganic insulating film. Therefore, the organic insulating material was selected here.

On the interlayer insulating film 21, Al, Al alloy,
A film of a reflective electrode material made of a silver alloy or the like is deposited. The thickness of the reflective electrode material film is, for example, about 50 to 100 nm. Through a photolithography process, an upper pixel electrode 14A (reflective electrode) is formed from the reflective electrode material film. In the present embodiment, the lower pixel electrode does not function strictly as a pixel electrode, but functions as a lower electrode for the upper pixel electrode, and is therefore referred to as a “lower image electrode”.

The material of the signal wiring layer must be a transparent conductive material in the case of manufacturing a transmission type active matrix substrate. However, in the case of a reflection type active matrix substrate, the conductive film may be a light shielding film. A transparent film may be used. However, it is necessary to select a material that can form a low-resistance contact with the upper pixel electrode 14A. Here, since Al is used as the material of the upper pixel electrode, Ti is selected as the material of the lower pixel electrode 14B, the signal wiring 5, and the drain electrode 9.

(Example) An example of the active matrix substrate was prototyped using a 5-inch square plastic substrate (0.2 mm thick) made of PES. The panel size is 3.9 "diagonal and the resolution is 1/4 VGA (320 x RG
B × 240) for reflection type. The size of one pixel area is 82 μm × 246 μm, and the width G _{width of the} scanning wiring is 8 μm.
m, the gap PP _gap between the pixel electrodes in the lower layer is 5 μm, the width Y _{con of the} connection portion is 5 μm, and the width W _cs of the auxiliary capacitance wiring is 25 μm.
m, the gap GC _gap between the auxiliary capacitance wiring and the scanning wiring is 1
0μm, and the gap DD _gap between the drain and 5μm, ΔY = 246-8-5-25-10-5-5 = 18
8 μm.

In this embodiment, the plastic substrate is arranged so that ΔY1 = ΔY2 at the center of the substrate so as to cope with both expansion and contraction of the plastic substrate. As a result, the alignment margin ΔY between the scanning wiring layer (first mask layer) and the source wiring / lower pixel electrode layer (second mask layer) was ± 91 μm (ΔY = ΔY / 2−2).
dY). Here, dY is the accuracy of the alignment apparatus, and dY = 3 μm.

Since the length of the display area in the ΔY direction is 240 (line) × 246 (μm) = 59040 (μm), the substrate expansion and contraction margin allowed between the first mask and the second mask is 1,541 ppm. is there. When the prototype was actually manufactured, the substrate expanded and contracted by about 500 to 700 ppm. However, due to the alignment margin, the shapes of the thin film transistor and the auxiliary capacitor were as designed in all the pixel regions.

On the other hand, the third mask defining the contact hole may be aligned only with the second mask. Source wiring width Ws is 8 μm, drain electrode width Wd is 8 μm, source-drain gap SD _gap
Is 5 μm and the width of the contact hole is 5 μm, Δ
C = 82-8-8-3 × 5-5 = 46 μm.

Also in this case, the arrangement was made such that Δc1 = Δc2 at the center of the substrate so as to be able to cope with both expansion and contraction of the substrate. As a result, the alignment margin Δc between the second mask and the third mask was ± 20 μm (Δc = ΔC / 2−dY).

In the Y-axis direction, mask alignment was performed such that the contact hole 21 was located substantially at the center of the lower pixel electrode 14B in the center of the substrate.

The length of the display area in the direction parallel to ΔC is 3
Since 20 × 82 × 3 = 78720 μm, the allowable substrate expansion / contraction margin is only 254 ppm. However, unlike the step between the first mask layer and the second mask layer, the CVD film formation causing a large expansion and contraction of the substrate during the photolithography step between the second mask layer and the third mask layer. There is no process. For this reason, when a prototype was actually produced, the expansion and contraction of the substrate was only about 1500 ppm at the maximum, and alignment was sufficiently performed by this structure.

The fourth pixel electrode 14A defining the upper pixel electrode 14A is provided.
In this mask, only the alignment with respect to the third mask needs to be performed. Gap PP _tgap between upper pixel electrodes is 5
If μm, ΔP = 82−5 = 77 μm.

Also in this case, the arrangement was made such that Δp1 = Δp2 at the center of the substrate so as to cope with both expansion and contraction of the substrate. As a result, the alignment margin Δp between the fourth mask and the third mask is ± 35.5 μm
(Δp = ΔP / 2−dY).

The length of the display area in the direction parallel to ΔP is 3
Since 20 × 82 × 3 = 78720 μm, the allowable substrate expansion / contraction margin is only 451 ppm. But,
Between the photolithography process for the third mask and the photolithography process for the fourth mask, there is no CVD film formation process that causes large expansion and contraction of the substrate. Therefore, the alignment between the third mask and the fourth mask is relatively easy.

In this embodiment, the aperture ratio (the ratio of the reflective electrode to the pixel area) is obtained by disposing the reflective electrode (upper pixel electrode) 14A in a layer different from the signal wiring 5.
Becomes 92%.

In the conventional structure, alignment accuracy of several μm or less is required between all layers. Therefore, when the alignment margin is 9 μm, the allowable substrate expansion and contraction is 150 ppm. Therefore, with the conventional structure, an active matrix substrate cannot be manufactured using a plastic substrate.

According to the current manufacturing technology, in order to obtain TFT characteristics required for an active matrix substrate, the gate insulating film and the semiconductor layer are formed at a substrate temperature of 100 to 200 ° C.
Need to be formed by the CVD method. Therefore,
In order to realize an active matrix substrate on a plastic substrate, a pixel structure having a large alignment margin between the first mask and the second mask as in this embodiment is desirable.

In the present embodiment, the C
Although the s on Common structure is shown, a similar effect can be obtained even when there is no auxiliary capacitance wiring. 29 to 31
Shows an active matrix substrate 700 according to an improved example having a structure (Cs on Gate structure) in which the auxiliary use wiring is removed from the configuration of the present embodiment. According to the active matrix substrate 700, ΔY can be further increased.

(Seventh Embodiment) By employing the structure of the sixth embodiment, a 3.9 inch １ ／ VGA reflective liquid crystal display device can be manufactured using a plastic substrate. However, when the pixel size is smaller or the panel size is larger, the alignment margin ΔC of the contact hole may be insufficient. Also, 3.9 inch 1 / 4V
Even in the case of a panel of about GA, it is preferable to further increase the alignment margin in consideration of mass production.
In the present embodiment, a configuration that can further increase the alignment margin ΔC of the contact hole is adopted.

The present embodiment will be described below with reference to FIGS. 32 is a plan view showing a layout of the active matrix substrate 800 in the present embodiment, FIG. 33 is a sectional view taken along line AA ′ of FIG. 32, and FIG. 34 is a sectional view taken along line BB ′ of FIG. FIG.

As can be seen from the figure, the lower pixel electrode 14B in this embodiment crosses the auxiliary capacitance line 20, and the corresponding scanning line crosses the drain electrode 9 extending from the lower pixel electrode 14B. As a result, the drain electrode 9 does not exist in the region apart from the lower pixel electrode 14B along the X-axis direction, and only the source line 5 is arranged.
For this reason, the width (the size in the X-axis direction) of the lower pixel electrode 14B can be relatively increased, and as a result,
The alignment margin ΔC of the contact hole can be increased. The alignment margin ΔC is represented by the following equation.

ΔC = P _ss −W _s −2 · SD _gap −W _ch where P _ss is the source pitch, W _s is the width of the source wiring,
SD _GAP gap between the pixel electrode and the source wiring, W _ch is the width of the X-axis direction of the contact hole.

On the other hand, the drain electrode 9 passes over only the scanning line 2 and does not overlap with the auxiliary capacitance line, and the pixel electrode 14B of the lower layer passes over only the auxiliary capacitance line 20 and does not overlap with the scanning line 2. Therefore, the substrate expansion / contraction margin ΔY between the first mask layer and the second mask layer is expressed by the following expression.

ΔY = (P _pitch −G _width −W _cs −DD
_gap -DG _gap ) / 2

In this embodiment, compared to the second embodiment,
This is about half, but is effective when it is necessary to increase the alignment margin between the second mask layer and the third mask layer.

The length of the drain electrode 9 in the Y-axis direction is
The active matrix substrate 800 according to this embodiment includes:
The active matrix substrate according to the sixth embodiment is manufactured by a method similar to that of the sixth embodiment.

(Example) An example of the active matrix substrate was prototyped using a 5-inch square plastic substrate (0.2 mm thick) made of PES. The panel size is 2.5 inches diagonal and the resolution is 1/4 VGA (32
0 × RGB × 240) for reflection type. The size of one pixel area is 53 × 159 μm, and the width Gwidt of the scanning wiring
h is 8 μm, the width W _cs of the auxiliary capacitance line is 10 μm, and the gap DDgap between the drain electrode and the lower pixel electrode is 5 μm.
m, and the minimum gap between the lower pixel electrode and the scanning wiring is 3 μm, ΔY = (159-8-10-5-3) / 2 = 1
33 μm.

In this embodiment, the plastic substrate is arranged so that ΔY1 = ΔY2 at the center of the substrate so as to cope with both expansion and contraction of the plastic substrate. As a result, the alignment margin ΔY between the scanning wiring layer (first mask layer) and the source wiring / lower pixel electrode layer (second mask layer) was ± 63.5 μm (ΔY = ΔY /
2-dY and dY were 3 μm in the accuracy of the alignment apparatus).

Since the length of the display area in the ΔY direction is 240 lines) × 159 (μm) = 38160 (μm), the substrate expansion and contraction allowed between the first mask layer and the second mask layer is possible. The margin amounts to 1664 ppm.

The alignment margin between the contact hole layer (third mask layer) and the lower pixel electrode layer (second mask layer) is ΔC = 53−8−2 × 5−5 = 3
0 μm. In order to cope with both expansion and contraction of the substrate, they were arranged so that Δc1 = Δc2 at the center of the substrate. As a result, the alignment margin Δc between the second mask layer and the third mask layer was ± 12 μm (Δc = ΔC / 2−dY). The length of the display area in the direction parallel to ΔC is 320 × 53 × 3 = 50880 μm
Therefore, the allowable substrate expansion / contraction margin is 590 pp.
m. This value is a sufficient alignment margin between the photolithography process of the second mask layer and the third mask layer without the CVD process.

On the other hand, when the structure of the second embodiment is adopted, the width Ws of the source wiring is 6 μm and the width W
When d is 6 μm, the source-drain gap SDgap is 5 μm, and the width of the contact hole is 5 μm, ΔC = 5
3-8-8-3 × 5-5 = 17 μm, Δc = ΔC
/ 2-dY is only ± 5.5 μm. The substrate expansion and contraction margin is only 108 ppm, and a sufficient manufacturing margin cannot be obtained.

Therefore, by employing this embodiment, it is possible to increase the photo alignment margin when forming the contact hole 22 connecting the upper pixel electrode 14A and the lower pixel electrode 14B. For this reason, for example, a 2.5 inch 1/4 VG as shown in this embodiment
A high-definition active matrix substrate exceeding 150 PPI corresponding to A can be realized on a plastic substrate.

The structure of the upper pixel electrode 14A is the second
Since the structure is the same as that of the embodiment, a high aperture ratio can be obtained. In this embodiment, the aperture ratio is 88%.

(Eighth Embodiment) The present embodiment will be described below with reference to FIGS. FIG.
Is the active matrix substrate 90 in the present embodiment.
FIG. 36 is a plan view showing a layout of FIG.
FIG. 37 is a sectional view taken along line AA ′ of FIG. 5, and FIG.
38 is a sectional view taken along the line B ′, and FIG. 38 is a sectional view taken along the line CC ′ in FIG.

The difference between the active matrix substrate 900 according to the present embodiment and the active matrix substrates according to the first to seventh embodiments lies in the shape of the thin film transistor.

In this embodiment, the source electrode 8B branched from the signal line 5 passes near the end of the drain electrode 9 and is bent in a direction parallel to the signal line 5. The source electrode 8B, together with the signal wiring 5, sandwiches the drain electrode 9. Then, the signal wiring 5 (the source electrode 8)
A), the source electrode 8B and the drain electrode 9 are all arranged so as to surmount the scanning wiring 2 and the semiconductor layer 6 on the scanning wiring.

As shown in FIG. 36, since the semiconductor layer 6 remains on the entire upper surface of the scanning wiring 2, the scanning wiring 2
Both the region between the signal wiring 5 (source electrode 8A) and the drain electrode 9 and the region between the source electrode 8B and the drain electrode 9 above function as a thin film transistor.

On the other hand, the source electrode 8B and the adjacent signal wiring 5
Since the semiconductor layer also exists between the region and the (source electrode 8A), this region can function as a parasitic thin film transistor. However, the signal on the adjacent signal line 5 is not
Since it is shielded by B, it does not affect the potential of the pixel electrode 14B via the drain electrode 9.

In the present embodiment, as is apparent from FIG. 38, the following equation is established. ΔY = (P _pitch −G _width −W _cs −Ws−3 · S
D _gap ) / 2

According to the present embodiment, the step of removing the semiconductor layer other than the channel portion of the thin film transistor by the half exposure technique is unnecessary. As a result, it is possible to shorten the manufacturing process time and improve the manufacturing yield of the active matrix substrate.

(Ninth Embodiment) Hereinafter, this embodiment will be described with reference to FIGS. FIG.
Is the active matrix substrate 10 in the present embodiment.
FIG. 40 is a plan view showing the layout of FIG. 00, and FIG. 40 is a sectional view taken along line AA ′ of FIG.

The active matrix substrate 1000 according to the present embodiment has a configuration similar to that of the active matrix substrate 900 according to the eighth embodiment. One of the features of the active matrix substrate 1000 is that the drain electrode 9 is arranged substantially at the center of two adjacent signal wires 5. The upper pixel electrode 14A completely covers the channel of the thin film transistor. In other words, the position of the drain electrode 9 is set so that the upper pixel electrode 14A completely covers the channel portion of the thin film transistor. In other respects, the configuration of the active matrix substrate 1000 is similar to the configuration of the active matrix substrate 900.

With such a structure, the light leakage current of the thin film transistor 10 is suppressed, so that the contrast when applied to a liquid crystal display device can be improved.

In the present embodiment, as is apparent from FIG. 40, the following equations hold.

ΔY = (P _pitch −G _width −W _cs −2 · W
s-3 · SD _gap ) / 2

In this embodiment, the signal wiring 5, the drain electrode 9 and the source electrode 8B have portions extending in parallel with each other, and these portions are orthogonal to the scanning wiring 2. In order to obtain the effect of the present invention, it is not necessary that the parallel portion and the scanning wiring 2 are orthogonal to each other, and may intersect at an angle other than 90 degrees.

The drain electrode 9 may be provided at a position slightly deviated from the center of the adjacent signal wiring 5 due to misalignment. However, the drain electrode 9 is within ± 25% of the pixel pitch (pixel pitch measured along the X-axis direction) from a straight line passing along the center of the corresponding lower pixel electrode 14B along the Y-axis. Is preferred.

According to this embodiment, as in the eighth embodiment, a step of removing the semiconductor layer other than the channel portion of the thin film transistor by the half exposure technique is unnecessary. As a result, it is possible to shorten the manufacturing process time and improve the manufacturing yield of the active matrix substrate.

(Embodiment 10) In each of the embodiments described above, the configuration in which the scanning wiring is formed at the lower level and the semiconductor layer of the thin film transistor is formed at the upper level is adopted. The transistor having this structure is called a “bottom-gate transistor (inverted staggered transistor)” because the scanning wiring functioning as a gate electrode is located at the lowest level of the transistor. In the present embodiment, an active matrix substrate is formed using a “top gate transistor (positive staggered transistor)” in which a scanning wiring functioning as a gate electrode is provided in the uppermost layer of the transistor.

The active matrix substrate 1 of the present embodiment
In 100, as shown in FIGS. 41 (c) and 42 (d), the scanning wiring 2 is formed at an upper layer level of the signal wiring 5, the drain electrode 9, and the pixel electrode 14, and the signal wiring 5, the drain It intersects the electrode 9 and the pixel electrode 14.

The semiconductor layer 6 is disposed at a lower level of the signal wiring 5, the drain electrode 9, and the pixel electrode 14, and is covered by the signal wiring 5, the drain electrode 9, and the pixel electrode 14. The gate insulating film 4 always exists immediately below the scanning line 2, and an auxiliary capacitance is formed between the scanning line 2 and the pixel electrode 14.

Hereinafter, the active matrix substrate 50 according to the present embodiment will be described with reference to FIGS. 41 and 42.
0 will be described.

First, as shown in FIG. 42A, an intrinsic semiconductor layer 6 made of non-doped amorphous silicon, an impurity-doped semiconductor layer 7 doped with P (phosphorus) and the like, and an APC ( Ag-Pd-C
After a reflective metal film 96 made of u (silver alloy) is laminated, a resist mask 92 is formed. The thicknesses of the intrinsic semiconductor layer 6, the impurity-added semiconductor layer 7, and the reflective metal film 96 are, for example, 150 nm, 50 nm, and 150 nm, respectively. As in the case of the first embodiment, the resist mask 92 has a relatively thick portion 92 a defining the signal wiring 5, the drain electrode 9, and the pixel electrode 14, and a region between the signal wiring 5 and the drain electrode 9. Relatively thin portion 92 defining
b.

Next, using the resist mask 92, the reflective metal film 96, the impurity-added semiconductor layer 7, and the intrinsic semiconductor layer 6 are sequentially etched. FIG. 41 (a) and FIG.
(B) shows the configuration at the stage when this etching is completed. At this stage, the channel region of the thin film transistor 10 is
Since it is covered with 2b, the metal film 96 in the channel region and the impurity-added semiconductor layer 7 are not etched at all. That is, in the reflective metal film 96, the part to be the signal wiring 5 and the part to be the drain electrode 9 remain unseparated.

Next, after removing the resist portion 92b covering the channel region of the thin film transistor by, for example, oxygen plasma ashing, the reflective metal film 9 is formed again.
6 and the impurity-added semiconductor layer 7 are etched. By removing the resist mask 92, FIG.
The structure shown in FIG. 42B and FIG. 42C can be manufactured. At this stage, as shown in FIG. 41B, in the gap region between the signal wiring 5 and the drain electrode 9, the intrinsic semiconductor layer 6 located at the lower level thereof is partially exposed.

Next, using a CVD method, a thickness of 400 nm
After laminating a gate insulating film 4 made of SiN _x and an AlNd film having a thickness of 200 nm,
FIG. 41 (b) and FIG. 42 (d)
The scanning wiring 2 is formed as shown in FIG.

Thereafter, an etching step using the scanning wiring 2 as a mask is performed to remove the gate insulating film 4 and the intrinsic semiconductor layer 6 located in a region not covered by the scanning wiring 2. As a result, FIG. 41 (c) and FIG. 42 (e)
Is obtained. By this etching, a portion of the intrinsic semiconductor layer 6 located in a region between the signal wiring 5 and the drain electrode 9 is removed except for a portion functioning as a thin film transistor. The pixel electrode 14
At the lower level of the drain electrode 9, there are finally semiconductor layers 6 and 7 having the same shape as the pixel electrode 14 and the drain electrode 9, and also at the lower level of the signal line 5. Conductor layer 6 having the same shape as
And 7 are present.

The active matrix substrate 5 of the present embodiment
Reference numeral 00 has a reflective pixel electrode 14 and is used to configure a reflective liquid crystal display device. According to the manufacturing method of the present embodiment, since the semiconductor layers 6 and 7 are left under the pixel electrode 14, even if the pixel electrode 14 is formed of a transparent conductive film, it cannot be applied to a transmissive display device. .

Note that the material of the scanning wiring 2 is not limited to AlNd, but may be any conductive material that can function as an etching mask when etching the gate insulating film 4 and the semiconductor layers 6 and 7. For example, Ta, Mo, W, Ti, A
or an alloy thereof, APC, or ITO. Alternatively, a film in which a plurality of layers made of these materials are stacked may be used.

The material of the reflective metal film is not limited to APC.
Ag, Al, Au, or alloy materials thereof may be used.

The material of the gate insulating film 4 is not limited to SiN _x , but may be an inorganic insulating material such as SiO ₂ , an organic insulating material such as BZT, or a film in which layers made of these materials are laminated. .

As described above, in the active matrix substrate of the present embodiment, the pixel electrodes 14 are formed from a reflective metal film, and the display device finally assembled is of a reflective type. On the other hand, the active matrix substrates according to the first to fourth embodiments are used for transmission type display devices. In order to convert the first to fourth embodiments to a reflective type, a reflective metal film is formed instead of the transparent conductive film, and the reflective metal film is patterned to form the signal wiring 5, the drain electrode 9, and the Pixel electrode 14
May be formed. In this case, there is no problem even if the semiconductor layers 6 and 7 remain at the lower level of the pixel electrode 14. Therefore, in the case of the reflection type, it is not necessary to pattern the semiconductor layers 6 and 7 into a shape matching the scanning wiring 2 before forming the pixel electrode 14. As in the case of the fourth embodiment, if a linear channel protective layer is formed on the scanning wiring, the contact layer and the reflective metal film deposited thereon are patterned to form the signal wiring 5 and the drain electrode 9. When forming the pixel electrode 14 and the relatively thin portion 92b of the resist mask 92 is removed, the channel protective layer can function as a part of the etching mask. Therefore, when an unnecessary semiconductor layer located in a region between the signal wiring 5 and the drain electrode 9 is removed by etching, the semiconductor layer is left directly below the channel protective layer, and a portion functioning as a semiconductor region of the thin film transistor Are appropriately arranged on the scanning wiring.

The configuration adopted in the sixth to ninth embodiments, that is, the configuration using the auxiliary capacitance wiring and the configuration in which the upper pixel electrode is arranged on the insulating film are combined with the top-gate transistor according to the present embodiment. Is also good.

(Eleventh Embodiment) Each of the scanning wiring 2 and the signal wiring 5 in the first to fourth embodiments is composed of a wiring extending linearly, and is parallel to the main surface of the substrate 1. It does not have any protruding or depressed parts. For this reason, even if an alignment shift occurs in the direction parallel to the scanning line 2, the layout in each pixel does not change. On the other hand, the alignment deviation in the direction perpendicular to the scanning wiring 2 is the alignment margin (Δ
Y) must be kept within a range that does not exceed Y), and the size of the alignment margin (ΔY) is smaller than the pixel pitch.

For this reason, when the substrate expansion / contraction ratio is not uniform depending on the azimuth, it is preferable to arrange the signal wiring 5 in parallel to the azimuth where the substrate expansion / contraction ratio is small. Therefore, in the present embodiment, the expansion and contraction ratio of the substrate 1 in the direction parallel to the signal wiring 5 is smaller than the expansion and contraction ratio of the substrate 1 in the direction perpendicular to the signal wiring 5. The direction is set. As a result, the alignment deviation in the direction parallel to the signal wiring 5 is reduced, so that the alignment deviation can be reliably kept within the alignment margin (ΔY).

On the other hand, in order to ensure a sufficient alignment margin in the direction parallel to the scanning wiring 2, the scanning wiring 2 is made sufficiently long as shown in FIG. 1 and is extended straight outside the display area (pixel area). Need to be kept. By providing such an extension in the scanning wiring 2, the signal wiring 5 and the pixel electrode 14 can be arranged in a direction parallel to the scanning wiring 2.
, The signal lines 5 and the pixel electrodes 14 can cross the scanning lines 2 without fail. The alignment margin (Δ in the direction parallel to the scanning wiring 2)
X) is defined by the length of the extension of the scanning wiring 2.

In this embodiment, as described above, the scanning wiring 2
The alignment margin (ΔX) in the direction parallel to the scanning line 2 is selected as the alignment margin (ΔX) in the direction parallel to the scanning line 2 because the arrangement is selected such that the substrate expansion ratio in the direction parallel to the scanning line 2 is relatively large. Δ
It is preferable to set larger than Y). For this reason,
In the present embodiment, the length of the extension of the scanning wiring 2 is longer than the scanning wiring pitch.

The example of realizing the active matrix substrate using the plastic substrate has been described above, but the scope of the present invention is not limited to this. The present invention exerts a remarkable effect when a substrate that expands and contracts during the manufacturing process such as a plastic substrate is used. Among various effects obtained by the present invention, an effect that is hardly affected by misalignment is caused by plastic. Even if a substrate other than the substrate (for example, a glass substrate) is used, it can be sufficiently enjoyed. In particular,
A favorable effect can be obtained when a large-sized display panel is manufactured using an exposure apparatus with low alignment accuracy.

The active matrix substrate according to the present invention can be used for a display device other than a liquid crystal display device (for example, an organic EL device).
The present invention can also provide excellent effects when applied to a (display device using).

[0331] The "crossing" in the present specification is defined as
For example, as shown in FIG. 4A, this does not mean only the state in which the drain electrode 9 completely crosses the scanning wiring 2 located in the lower layer, but the position of the tip (edge 9E) of the drain electrode 9 This includes the case where the position coincides with the position of the edge (side surface) of the scanning wiring 2.

[0332]

According to the active matrix substrate of the present invention, the conductive member for connecting the pixel electrode to the thin film transistor extends to the position of the scanning wiring located at a position distant from the pixel electrode, and intersects with the scanning wiring. ing. For this reason, the alignment margin between the scanning wiring and the conductive member is sufficiently large, and it is possible to use a substrate having a large expansion and contraction rate such as a plastic substrate.

In the case where the semiconductor layer of the thin film transistor is formed on the scanning wiring (gate electrode) in a self-aligned manner, the semiconductor layer and the scanning wiring (gate electrode) are manufactured during the manufacturing.
This eliminates the need for mask alignment between the thin film transistor and the semiconductor layer of the thin film transistor and the scanning wiring (gate electrode) even if the substrate expands and contracts significantly.

[0334] In the case where a channel protective layer is provided over the semiconductor layer of the thin film transistor, the channel region of the semiconductor layer is not etched during the manufacturing process, and variation in transistor characteristics is prevented. Further, when the channel protective layer is formed in a self-aligned manner with respect to the scanning wiring (gate electrode), the mask alignment between the channel protective layer and the scanning wiring (gate electrode) becomes unnecessary, so that the substrate expands and contracts greatly. Even if the channel protection layer and scanning wiring (gate electrode)
There is an advantage that no positional deviation occurs between them.

When the scanning wiring (gate electrode) is formed of a light-shielding metal, the above-described semiconductor layer and channel protection layer can be formed by using a backside exposure method.

When the thin film transistor is covered with the black matrix, an increase in off current leakage of the thin film transistor due to external light is suppressed.

According to the method of manufacturing an active matrix substrate of the present invention, a thin film transistor can be formed on a scanning wiring in a self-aligned manner by a backside exposure method.
Even if the substrate expands and contracts, there is no need to consider the alignment deviation between the thin film transistor and the scanning wiring.
In addition, since a layout in which a signal wiring functioning as a source electrode and a conductive member functioning as a drain electrode can easily intersect with a scanning wiring is employed, a thin film transistor which functions normally even when the substrate expands and contracts greatly is used. Can be formed. For this reason, it becomes possible to manufacture an active matrix substrate using a plastic substrate which has conventionally been considered difficult to realize.

According to the display device of the present invention, since the above-described active matrix substrate is provided, display can be performed using a lightweight and high-impact-resistance plastic substrate.

[Brief description of the drawings]

FIG. 1 is a top view schematically showing a layout of an active matrix substrate 100 according to a first embodiment of the present invention.

FIG. 2 is a top view in which a part of a display area of an active matrix substrate 100 is enlarged.

FIG. 3A is a sectional view taken along line AA ′ of FIG. 2;
FIG. 3B is a sectional view taken along line BB ′ of FIG. 2.

FIG. 4A shows an example of an arrangement suitable for a case in which a plastic substrate extends after a scan wiring is formed and before a drain electrode and a pixel electrode are patterned;
(B) shows an arrangement example suitable for a case where the plastic substrate shrinks in the same period.

FIG. 5 shows an arrangement example in a case where it is unspecified whether a plastic substrate extends or shrinks after patterning of a drain electrode or a pixel electrode after forming a scanning wiring.

FIGS. 6A to 6D are top views showing two pixel regions in main process steps.

FIGS. 7A to 7E are process cross-sectional views showing a cross section taken along line AA ′ and a cross section taken along line BB ′ of FIG. 6 in main process steps.

FIGS. 7A to 7E are process cross-sectional views showing a cross section taken along line AA ′ and a cross section taken along line BB ′ of FIG. 6 in main process steps.

FIGS. 7A and 7B are process cross-sectional views showing a cross section taken along line AA ′ and a cross section taken along line BB ′ of FIG. 6 in main process steps.

8A is a partially enlarged view showing a part of a resist mask for defining a pixel electrode and the like, and FIGS. 8B, 8C, and 8D are respectively CCs of FIG. 'Line cross section,
It is DD 'line sectional drawing, and EE' line sectional drawing.

FIG. 9 is a schematic perspective view of the resist mask shown in FIG.

FIG. 10 is a schematic perspective view after ashing of the resist mask of FIG. 8;

FIG. 11 is a diagram for explaining an electrodeposition method of a color filter employed in an embodiment of the present invention.

FIG. 12 is a plan view illustrating an example of an alignment marker employed in an embodiment of the present invention.

FIG. 13: Alignment margin (substrate expansion / contraction margin)
6 is a graph illustrating a relationship between Δy and a pixel pitch.

FIG. 14 is a plan view schematically showing a layout of an active matrix substrate 200 according to a second embodiment of the present invention.

15A is a cross-sectional view taken along the line AA ′ of FIG. 14, and FIG. 15B is a cross-sectional view taken along the line BB ′ of FIG.

FIG. 16 is a view illustrating a method for manufacturing the active matrix substrate 200 according to the second embodiment of the present invention, and is a plan view illustrating two pixel regions in main process steps.

17 is a process sectional view showing a section taken along line AA ′ and a section taken along line BB ′ of FIG. 16;

FIG. 18 is a plan view schematically showing a layout of an active matrix substrate 300 according to a third embodiment of the present invention.

FIGS. 19 (a) and (b) are plan views showing the shape of a black matrix 35 in a thin film transistor formation region, and FIGS. 19 (c) and 19 (d) are (a), respectively.
It is a FF 'line sectional view of (b).

FIG. 20 is a view showing a method for manufacturing the active matrix substrate 400 according to the fourth embodiment of the present invention, and is a plan view showing two pixel regions in main process steps.

21 is a process sectional view showing a section taken along line AA ′ and a section taken along line BB ′ of FIG. 20;

FIG. 22 is a top view schematically showing a layout of an active matrix substrate 500 according to a fifth embodiment of the present invention.

FIG. 23 is a top view in which a part of a display area of the active matrix substrate 500 is enlarged.

24 is a sectional view taken along line A-A 'of FIG.

FIG. 25 is a sectional view taken along line B-B ′ of FIG. 23;

FIG. 26 is an enlarged top view of a part of a display area of an active matrix substrate 600 according to a sixth embodiment of the present invention.

FIG. 27 is a sectional view taken along line A-A ′ of FIG. 26;

FIG. 28 is a sectional view taken along line B-B ′ of FIG. 26;

FIG. 29 is an enlarged top view of a part of a display region of an active matrix substrate 700 according to a modification of the sixth embodiment of the present invention.

30 is a sectional view taken along line A-A 'of FIG.

FIG. 31 is a sectional view taken along line B-B ′ of FIG. 29;

FIG. 32 is an enlarged top view of a part of a display area of an active matrix substrate 800 according to a seventh embodiment of the present invention.

FIG. 33 is a sectional view taken along line A-A ′ of FIG. 32;

34 is a sectional view taken along line B-B 'of FIG.

FIG. 35 is an enlarged top view of a part of a display region of an active matrix substrate 900 according to an eighth embodiment of the present invention.

FIG. 36 is a sectional view taken along line A-A ′ of FIG. 35;

FIG. 37 is a sectional view taken along line B-B ′ of FIG. 35;

FIG. 38 is a sectional view taken along line C-C ′ of FIG. 35;

FIG. 39 is an enlarged top view of a part of a display area of an active matrix substrate 1000 according to a ninth embodiment of the present invention.

40 is a sectional view taken along line A-A 'of FIG.

FIG. 41 is a view illustrating the method for manufacturing the active matrix substrate 1100 according to the tenth embodiment of the present invention, and is a plan view illustrating two pixel regions in main process steps.

42 is a process cross-sectional view showing a cross section taken along line AA ′ and a cross section taken along line BB ′ of FIG. 41.

FIG. 43 is a plan view of a conventional active matrix display device.

FIG. 44 is a sectional view of a conventional liquid crystal display panel.

FIG. 45A is a plan layout view of one pixel region formed on a conventional active matrix substrate, and FIG. 45B is a cross-sectional view taken along the line AA ′.

FIG. 46A is a plan layout view of one pixel region formed on a conventional active matrix substrate, and FIG. 46B is a cross-sectional view taken along the line AA ′.

FIG. 47 is a layout diagram of one pixel region formed on a conventional active matrix substrate.

FIG. 48 shows a conventional active matrix substrate.
FIG. 4 is a layout diagram used for obtaining a relationship between a pixel pitch and an alignment margin.

FIG. 49 is a plan view showing an intersection 80 between a scanning wiring 102 and a signal wiring 105 in a conventional active matrix substrate.

[Explanation of symbols]

Reference Signs List 1 plastic substrate 2 scanning wiring 3 gate electrode 4 gate insulating film 5 signal wiring 6 intrinsic semiconductor layer 7 impurity doped semiconductor layer 8 source electrode 9 drain electrode 10 thin film transistor (TFT) 11 protective insulating film 14 pixel electrode 15 connection part of drain electrode ( 20 Auxiliary capacitance line 21 Interlayer insulating film 22 Contact hole 23 Channel protective film 31 Thin film transistor channel region 33 Color filter 35 Black matrix 36 Counter electrode 37 Alignment film 38 Liquid crystal layer 39 Seal 40 Spacer 50 Liquid crystal panel 51 Gate drive circuit 51 52 Source drive circuit 52 53 Gate driver / source driver 54 Transparent insulating substrate 55 Opposite substrate 56 Polarizer 91 Transparent conductive film 92 Resist mask 93 Light-shielding metal film 95 Channel protective layer 96 reflective metal film 101 plastic substrate 102 scan wiring 103 gate electrode 104 gate insulating film 105 signal wiring 106 intrinsic semiconductor layer 107 impurity-doped semiconductor layer (contact layer) 108 source electrode 109 drain electrode 110 thin film transistor (TFT) 113 auxiliary capacitance Line 114 pixel electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09F 9/00 338 G09F 9/00 342Z 342 9/30 330Z 9/30 330 338 338 349C 349 9/35 9 / 35 H01L 29/78 612D H01L 29/786 616T 627C 626C 616N (72) Inventor Shinya Yamakawa 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Within Sharp Corporation (72) Inventor Atsushi Ban Atsushi, Osaka-shi, Osaka 22-22, Nagaike-cho, Ward Sharp Co., Ltd. (72) Inventor Masaya Okamoto 22-22, Nagaike-cho, Abeno-ku, Osaka, Osaka Prefecture Within Sharp Co., Ltd. No.22 F-term in Sharp Corporation (reference) 2H090 JB02 JB03 2H092 JA24 JA32 JA34 JA37 JA41 JA46 JB01 JB24 JB26 JB33 JB35 JB52 JB69 KA05 KA10 MA13 MA18 NA27 NA29 PA01 PA02 PA03 PA08 PA11 PA12 5C094 AA14 AA43 AA03 BA03 BA43 CA19 DA14 EA04 EA07 ED15 5F110 AA04 AA07 EA01 A01 EE03 A01 EA01 A01 EE01 EE15 EE24 EE25 EE37 EE44 FF01 FF03 FF29 GG02 GG13 GG14 GG15 GG24 GG29 GG35 GG44 HK04 HK06 HK07 HK09 HK15 HK21 HK25 HK34 HL03 HL06 HM04 HM05 HM18 HM19 NN04 NN14 NN16 NN24 NN27 NN43 NN44 NN45 NN47 NN49 NN52 NN63 NN72 NN73 NN77 NN80 QQ01 QQ02 QQ05 QQ11 QQ12 5G435 BB12 CC09 FF13 KK05 KK09 KK10

Claims (62)

[Claims] A substrate, a plurality of scanning lines formed on the substrate, a plurality of signal lines intersecting the scanning lines via an insulating film, and a plurality of signal lines formed on the substrate and corresponding to the scanning lines. An active matrix substrate, comprising: a plurality of thin film transistors that operate in response to an applied signal; and a plurality of pixel electrodes that can be electrically connected to corresponding signal lines via the thin film transistors. And the corresponding thin film transistors are connected to each other by a conductive member, and the pixel electrode and the conductive member each cross an adjacent different scanning line. 2. A substrate; a plurality of scanning lines formed on the substrate; a plurality of auxiliary capacitance lines; a plurality of signal lines intersecting the scanning lines and the auxiliary capacitance lines via an insulating film; A plurality of thin film transistors formed on a substrate and operating in response to a signal applied to a corresponding scan wiring; and a plurality of pixel electrodes capable of being electrically connected to the corresponding signal wiring via the thin film transistor. An active matrix substrate, wherein each pixel electrode and a corresponding thin film transistor are connected to each other by a conductive member, and each of the pixel electrode and the conductive member intersects a different adjacent scanning line. In addition, an active matrix substrate that also crosses adjacent different auxiliary capacitance wirings. 3. A substrate; a plurality of scanning lines formed on the substrate; a plurality of auxiliary capacitance lines; and a plurality of signal lines intersecting with the scanning lines and the auxiliary capacitance lines via a first insulating film. A plurality of thin film transistors formed on the substrate and operating in response to a signal applied to a corresponding scan line; and a plurality of lower pixel electrodes that can be electrically connected to the corresponding signal line via the thin film transistor An active matrix, comprising: a plurality of upper pixel electrodes disposed on the lower pixel electrode via a second insulating film and electrically connected to the lower pixel electrode via a contact hole; A substrate, wherein the signal wiring, the conductive member, and a lower pixel electrode are:
Both are formed by patterning the same conductive film, each pixel electrode and the corresponding thin film transistor are connected to each other by a conductive member, and the lower pixel electrode and the conductive member are Active matrix substrates each intersecting adjacent different scanning wirings and intersecting different adjacent storage capacitance wirings. 4. A substrate, a plurality of scanning lines formed on the substrate, a plurality of signal lines intersecting with the scanning lines via a first insulating film, and formed on the substrate to correspond to the plurality of signal lines. A plurality of thin film transistors that operate in response to a signal applied to the scanning wiring; a plurality of lower pixel electrodes that can be electrically connected to the corresponding signal wiring via the thin film transistor; An active matrix substrate, comprising: a plurality of upper pixel electrodes disposed in an upper layer of the lower pixel electrode and electrically connected to the lower pixel electrode via a contact hole; The conductive member, and the lower pixel electrode,
Both are formed by patterning the same conductive film, and the pixel electrode composed of the lower pixel electrode and the upper pixel electrode, and the corresponding thin film transistor are connected to each other by the conductive member. An active matrix substrate, wherein the lower pixel electrode and the conductive member each intersect with different adjacent scanning wirings; 5. A substrate; a plurality of scanning lines formed on the substrate; a plurality of auxiliary capacitance lines; a plurality of signal lines intersecting the scanning lines and the auxiliary capacitance lines via an insulating film; A plurality of thin film transistors formed on a substrate and operating in response to a signal applied to a corresponding scanning line; a plurality of lower pixel electrodes that can be electrically connected to the corresponding signal line via the thin film transistor; Disposed above the lower pixel electrode via a film,
An active matrix substrate comprising: a plurality of upper pixel electrodes electrically connected to the lower pixel electrode via a contact hole; wherein the signal wiring, the conductive member, and the lower pixel electrode are:
Both are formed by patterning the same conductive film, and the pixel electrode constituted by the lower pixel electrode and the upper pixel electrode, and the thin film transistor corresponding thereto are mutually connected by a conductive member. A scanning line and an auxiliary capacitance line adjacent to each other
An active matrix substrate in which one intersects the lower pixel electrode and the other intersects the conductive member. 6. A source electrode branched from the signal wiring and intersecting the scanning wiring, wherein an intersection between the conductive member and the scanning wiring is an intersection between the signal wiring and the scanning wiring and the source. The active matrix substrate according to claim 5, wherein the active matrix substrate is interposed between intersections of electrodes and the scanning lines. 7. The active matrix substrate according to claim 6, wherein a distance between the signal wiring and the conductive member is substantially equal to a distance between the conductive member and the source electrode. 8. The active matrix substrate according to claim 7, wherein a channel portion of said thin film transistor is located substantially at a center of an adjacent signal wiring. 9. The active matrix substrate according to claim 8, wherein a channel portion of the thin film transistor is covered by the upper pixel electrode. 10. The semiconductor layer of each thin film transistor is formed in a self-aligned manner with respect to the scanning wiring, and the signal wiring and the conductive member are arranged so as to intersect the semiconductor layer. 10. The active matrix substrate according to any one of items 1 to 9. 11. The signal line and the conductive member are arranged so as to extend over the semiconductor layer, and the channel region of the semiconductor layer is formed in a self-aligned manner with respect to the scan line. The active matrix substrate according to claim 1, wherein the active matrix substrate is covered with the active matrix substrate. 12. The side surface of the channel protection layer, the side surface of the side surface parallel to the direction in which the signal wiring and the conductive member extend is aligned with the outer side surface of the signal wiring and the conductive member. Active matrix substrate. 13. The active matrix according to claim 12, wherein, of the side surfaces of the channel protection layer, a distance between two side surfaces parallel to a direction in which the scanning line extends is smaller than a line width of the scanning line. substrate. 14. The conductive member extends from a pixel electrode connected to the conductive member in a direction parallel to the signal wiring, and is connected to the conductive member from a tip of the conductive member. The distance to the opposite end of the pixel electrode is longer than one time the scanning line interval and less than twice the scanning line interval.
4. The active matrix substrate according to any one of 3. 15. The device according to claim 1, wherein each of the signal wiring, the conductive member, and the pixel electrode includes a conductive layer formed by patterning the same conductive film. Active matrix substrate. 16. The signal line, the conductive member, and the pixel electrode each include a transparent conductive layer formed by patterning the same transparent conductive film, and the signal line includes the transparent conductive layer. 3. The active matrix substrate according to claim 1, wherein a light-shielding film is disposed on the transparent conductive layer. 17. The active matrix substrate according to claim 16, wherein the light-shielding film is formed of a metal whose electric resistivity is lower than that of the transparent conductive layer. 18. The scanning line and the signal line,
18. The active matrix substrate according to claim 1, wherein the active matrix substrate does not have a portion projecting in an orientation parallel to a surface of the substrate in the display area. 19. The active matrix substrate according to claim 1, wherein the scanning wiring is formed of a light-shielding metal. 20. Each of the plurality of scanning lines has at least a region where the thin film transistor is formed.
The active matrix substrate according to claim 1, further comprising a slit-shaped opening through which light can pass. 21. Each of the plurality of scanning wirings has at least a region where the thin film transistor is formed.
20. The active matrix substrate according to claim 1, wherein the active matrix substrate is separated into a plurality of wiring portions. 22. A line width of each of the plurality of wiring portions, after forming a negative photosensitive resin layer covering the scanning wiring,
When irradiating the substrate with light from the back side of the substrate, thereby exposing a part of the negative photosensitive resin layer, the light is diffracted, whereby the negative photosensitive resin positioned on the plurality of wiring portions is exposed. 22. The active matrix substrate according to claim 21, having a size capable of exposing substantially all of the resin layer to light. 23. A method according to claim 1, wherein the expansion and contraction of the substrate in a direction parallel to the signal wiring is smaller than the expansion and contraction of the substrate in a direction perpendicular to the signal wiring. 23. The active matrix substrate according to claim 1, wherein an arrangement relationship is defined. 24. The scanning line according to claim 1, wherein the plurality of scanning lines extend outside a display area, and a length of an extension of each scanning line is larger than a scanning line pitch. Active matrix substrate. 25. The active matrix substrate according to claim 1, wherein a color filter is formed on the pixel electrode. 26. The active matrix substrate according to claim 1, wherein said substrate is formed of plastic. 27. The substrate according to claim 26, wherein the substrate integrally includes an optical member for changing an optical path or polarization of incident light.
An active matrix substrate according to item 1. 28. A plastic substrate, a first scan line formed on the plastic substrate, and a second scan formed on the plastic substrate and arranged in parallel with the first scan line. A wiring, a third scanning wiring formed on the plastic substrate and arranged in parallel with the second scanning wiring, and a signal intersecting the first to third scanning wirings via an insulating film. Wiring, a first pixel electrode crossing the first scanning wiring, a second pixel electrode crossing the second scanning wiring, and a first pixel electrode formed in a self-aligned manner with respect to the second scanning wiring. A first thin film transistor; and a second thin film transistor formed in a self-aligned manner with respect to the third scanning line, wherein the first pixel electrode is provided with a first conductive layer that crosses the second scanning line. Said first member An active matrix substrate connected to a thin film transistor, wherein the second pixel electrode is connected to the second thin film transistor by a second conductive member crossing the third scan line. 29. The active matrix substrate according to claim 1, a substrate facing the active matrix substrate, a light modulation layer located between the active matrix substrate and the counter substrate, Display device provided with. 30. A portable electronic device comprising the display device according to claim 29. 31. A step of forming a plurality of scanning wirings on a substrate, a step of forming an insulating film covering the scanning wirings, a step of forming a semiconductor layer on the insulating film, and a step of forming a positive electrode on the semiconductor layer. Forming a mold resist layer, irradiating the substrate with light from the back side of the substrate, thereby exposing the positive resist layer, and then developing,
Forming a first resist mask aligned with the scanning wiring above the scanning wiring; removing a portion of the semiconductor layer that is not covered by the first resist mask to function as a semiconductor region of the thin film transistor Forming a linear semiconductor layer including a portion to be formed in a self-aligned manner with respect to the scanning wiring; removing the first resist mask; and depositing a conductive film so as to cover the linear semiconductor layer. Patterning the conductive film using a second resist mask to form a signal wiring and a pixel electrode that intersect with the scanning wiring, and extend from the pixel electrode in parallel with the signal wiring, Forming a conductive member that intersects with the scanning line adjacent to the scanning line with which the pixel electrode intersects, and further patterning the linear semiconductor layer; Forming a semiconductor region of the thin film transistor below the signal wiring and the conductive member, thereby forming an active matrix substrate. 32. The step of forming a semiconductor region of the thin film transistor, comprising: forming, as the second resist mask, a relatively thick portion defining the signal wiring and the conductive member; and a gap between the signal wiring and the conductive member. Forming a resist pattern having a relatively thin portion that defines a region of; a step of etching a portion of the conductive film and the linear semiconductor layer that is not covered with the resist pattern; Removing the relatively thin portion of, and etching the portion of the conductive film that was covered by the relatively thin portion of the resist pattern to form the signal wiring and the conductive member, 32. The method for manufacturing an active matrix substrate according to claim 31, further comprising: 33. A step of forming a plurality of scanning wirings on a substrate; a step of forming an insulating film covering the scanning wirings; a step of forming a semiconductor layer on the insulating film; Forming a mold resist layer, irradiating the substrate with light from the back side of the substrate, thereby exposing the positive resist layer, and then developing,
Forming a first resist mask aligned with the scanning wiring above the scanning wiring; removing a portion of the semiconductor layer that is not covered by the first resist mask to function as a semiconductor region of the thin film transistor Forming a linear semiconductor layer including a portion to be formed in a self-aligned manner with respect to the scanning wiring; removing the first resist mask; depositing a transparent conductive film so as to cover the linear semiconductor layer Performing a step of: depositing a light-shielding film on the transparent conductive film; and patterning the light-shielding film and the transparent conductive film using a second resist mask, so that the signal wiring and the pixel electrode intersecting with the scanning wiring And extending from the pixel electrode in parallel with the signal wiring and intersecting with the scanning wiring adjacent to the scanning wiring at which the pixel electrode intersects. Forming a semiconductor region of the thin film transistor below the signal wiring and the conductive member by patterning the linear semiconductor layer, and forming a negative photosensitive resin material on the substrate And applying the light to the substrate from the back side of the substrate, thereby exposing the negative photosensitive resin material, and then developing, removing the non-photosensitive portion to form a black matrix And manufacturing the active matrix substrate. 34. When exposing the negative photosensitive resin material, light transmitted through the region where the scanning wiring and the light-shielding film are not formed is used to form the signal wiring, the conductive member, and the semiconductor region of the thin film transistor. The method for manufacturing an active matrix substrate according to claim 33, wherein the negative-type photosensitive resin material located thereon is exposed to light, and thus, the region where the pixel electrode is not formed is covered with the black matrix. 35. A light-transmitting region is formed on the pixel electrode by etching a portion of the light-shielding film that is not covered by the black matrix.
3. The method for manufacturing an active matrix substrate according to 1. 36. A step of forming a semiconductor region of the thin film transistor, comprising: forming, as the second resist mask, a relatively thick portion defining the signal wiring and the conductive member; and a gap between the signal wiring and the conductive member. Forming a resist pattern having a relatively thin portion that defines a region of; a step of etching a portion of the conductive film and the linear semiconductor layer that is not covered with the resist pattern; Removing the relatively thin portion of, and etching the portion of the conductive film that was covered by the relatively thin portion of the resist pattern to form the signal wiring and the conductive member, The method for manufacturing an active matrix substrate according to any one of claims 33 to 35, comprising: 37. A step of forming a plurality of scanning lines on a substrate, a step of forming an insulating film covering the scanning lines, a step of forming a semiconductor layer on the insulating film, and a channel on the semiconductor layer. Forming a protective layer; forming a first positive resist layer on the channel protective layer; irradiating the substrate with light from the back side of the substrate, thereby forming the first positive resist. Forming a first resist mask aligned with the scanning wiring by exposure after the layer is exposed, and forming a portion of the channel protection layer that is not covered by the first resist mask; Forming a channel protection layer having a line width smaller than the line width of the scanning line in a self-aligned manner with respect to the scanning line; and covering the channel protection layer and the semiconductor layer. Depositing a contact layer on the contact layer; forming a second positive resist layer on the contact layer; irradiating the substrate with light from the back side of the substrate, whereby the second positive resist Forming a second resist mask aligned with the scan wiring above the scan wiring by developing after exposing the layer; and covering the contact layer and the semiconductor layer with the second resist mask. Forming a linear contact layer and a linear semiconductor layer including a portion functioning as a semiconductor region of a thin film transistor in a self-aligned manner with respect to the scanning wiring; and removing the second resist mask. Forming a conductive film so as to cover the linear contact layer; and patterning the conductive film using a third resist mask. This forms a signal line and a pixel electrode that intersect with the scanning line, and extends from the pixel electrode in parallel with the signal line, and intersects with a scanning line adjacent to the scanning line where the pixel electrode intersects Forming a conductive member, further, the linear contact layer, a channel protective layer,
Forming a semiconductor region of the thin film transistor having an upper surface partially covered with the channel protective film below the signal wiring and the conductive member by patterning the semiconductor layer. Method. 38. A step of forming a semiconductor region of the thin film transistor, comprising: forming a relatively thick portion defining the signal wiring and the conductive member as the third resist mask; and a gap between the signal wiring and the conductive member. Forming a resist pattern having a relatively thin portion that defines a region of the conductive film, a linear contact layer, a linear channel protective layer,
Etching a portion of the linear semiconductor layer that is not covered with the resist pattern; removing a relatively thin portion of the resist pattern; and forming the resist pattern of the conductive film and the contact layer. 38. The method of manufacturing an active matrix substrate according to claim 37, further comprising: etching a portion covered by the relatively thin portion to separate and form the signal wiring and the conductive member. 39. A step of forming a plurality of scanning lines on a substrate, a step of forming an insulating film covering the scanning lines, a step of forming a semiconductor layer on the insulating film, and a channel on the semiconductor layer. Forming a protective layer, and forming a positive resist layer on the channel protective layer, irradiating the substrate with light from the back side of the substrate, thereby exposing the positive resist layer, By development
Forming a first resist mask aligned with the scanning wiring above the scanning wiring; removing a portion of the channel protection layer that is not covered by the first resist mask; Forming a self-aligned pattern with respect to the scanning wiring, depositing a contact layer so as to cover the channel protective layer and the semiconductor layer, depositing a conductive film so as to cover the contact layer; By patterning the conductive film using the resist mask, a signal wiring and a pixel electrode that intersect with the scanning wiring are formed, and the pixel wiring extends from the pixel electrode along the signal wiring, and the pixel electrode intersects Forming a conductive member that intersects with a scanning line adjacent to the scanning line, and further includes a contact layer, a channel protection layer, and a semiconductor. Forming a semiconductor region of the thin film transistor whose upper surface is covered with the channel protective film below the signal wiring and the conductive member by patterning a layer. 40. The step of forming a semiconductor region of the thin film transistor, comprising: forming, as the second resist mask, a relatively thick portion defining the signal wiring and the conductive member; and a gap between the signal wiring and the conductive member. Forming a resist pattern having a relatively thin portion that defines a region, and etching a portion of the conductive film, the contact layer, the channel protective layer, and the semiconductor layer that is not covered with the resist pattern. Removing a relatively thin portion of the resist pattern; etching a portion of the conductive film and the contact layer that was covered by the relatively thin portion of the resist pattern; 40. The active matrix according to claim 39, further comprising: forming the conductive member separately. Method of manufacturing a substrate. 41. The method of manufacturing an active matrix substrate according to claim 39, wherein the semiconductor layer is formed in a self-aligned manner with respect to the scanning wiring by a backside exposure method before the formation of the contact layer. 42. After removing a relatively thin portion of the resist pattern, etching the portion of the conductive film and the contact layer which is covered by the relatively thin portion of the resist pattern. The method of manufacturing an active matrix substrate according to claim 40, wherein an exposed portion of the layer is etched to leave a semiconductor region of the thin film transistor below the channel protective layer. 43. forming a semiconductor film on a substrate; forming a first conductive film on the semiconductor film; and patterning the first conductive film and the semiconductor film to form a plurality of signal wirings. Forming a plurality of pixel electrodes, and a conductive member extending from each pixel electrode along the signal wiring, and leaving the semiconductor film located in a region between the signal wiring and the conductive member without removing it; Forming an insulating film on the substrate; forming a second conductive film on the insulating film; and patterning the second conductive film to intersect the signal wiring, the pixel electrode, and the conductive member. Forming a plurality of scanning lines, and exposing a portion of the semiconductor film located in a region between the signal lines and the conductive member other than a portion located below the scanning lines. The method for manufacturing an active matrix substrate comprising a step of quenching, the. 44. A step of patterning the first conductive film and the semiconductor film, comprising: forming a relatively thick portion defining the signal wiring, the pixel electrode, and the conductive member; Forming a resist mask having a relatively thin portion that defines a region between; and etching a portion of the first conductive film and the semiconductor film that is not covered by the resist mask; Removing the relatively thin portion from the resist mask; and etching a portion of the first conductive film that is covered by the relatively thin portion of the resist mask. Item 43. The method for manufacturing an active matrix substrate according to item 43. 45. A step of forming a gate electrode on a substrate, a step of forming a gate insulating film covering the gate electrode, a step of forming a semiconductor layer on the gate insulating film, and a step of forming a positive electrode on the semiconductor layer. Forming a mold resist layer, irradiating the substrate with light from the back side of the substrate, thereby exposing the positive resist layer, and then developing,
Forming a first resist mask aligned with the gate electrode above the gate electrode; removing a portion of the semiconductor layer not covered by the first resist mask to function as a semiconductor region of the thin film transistor Forming a semiconductor layer including a portion to be self-aligned with the gate electrode; removing the first resist mask; depositing a conductive film so as to cover the semiconductor layer; Patterning the conductive film using the second resist mask to form a source electrode and a drain electrode intersecting with the gate electrode, and further patterning the semiconductor layer to form a lower portion of the source electrode and the lower electrode. Forming a semiconductor region of the thin film transistor at the same time. Plate manufacturing method. 46. A step of forming a semiconductor region of the thin film transistor, comprising: forming a second resist mask as a second resist mask; a relatively thick portion defining the source electrode and the drain electrode; and a gap between the source electrode and the drain electrode. Forming a resist pattern having a relatively thin portion that defines a region of the resist pattern; etching a portion of the conductive film and the semiconductor layer that is not covered with the resist pattern; Forming a source electrode and a drain electrode by etching a portion of the conductive film that is covered by a relatively thin portion of the resist pattern. A method for manufacturing the active matrix substrate according to claim 36. 47. The signal line according to claim 47, wherein the source electrode is a part of a signal line extending linearly so as to intersect the scanning line, and the drain electrode extends in parallel from the pixel electrode along the signal line. Item 47. The method for manufacturing an active matrix substrate according to Item 45 or 46. 48. A step of forming a gate electrode on a substrate; a step of forming a gate insulating film covering the gate electrode; a step of forming a semiconductor layer on the gate insulating film; and a channel on the semiconductor layer. Forming a protective layer; forming a first positive resist layer on the channel protective layer; irradiating the substrate with light from the back side of the substrate, thereby forming the first positive resist. Forming a first resist mask aligned with the gate electrode above the gate electrode by developing after exposing the layer; and a portion of the channel protection layer that is not covered by the first resist mask. Removing the channel protection layer and the gate electrode in a self-aligned manner; and depositing a contact layer so as to cover the channel protection layer and the semiconductor layer. Forming a second resist mask above the gate electrode; removing a portion of the contact layer and the semiconductor layer that is not covered by the second resist mask; Forming a layer and a semiconductor layer including a portion functioning as a semiconductor region of the thin film transistor in a self-aligned manner with respect to the gate electrode; removing the second resist mask; and covering the contact layer. Depositing a conductive film, patterning the conductive film using a third resist mask to form a source electrode and a drain electrode that intersect with the gate electrode, and further form the contact layer, the channel protection layer, And by patterning the semiconductor layer, the source electrode and the drain electrode The method for manufacturing an active matrix substrate including the steps of forming a semiconductor region of the thin film transistor upper surface in said channel protection film is covered partially. 49. A step of forming a semiconductor layer of the thin film transistor, comprising: forming, as the third resist mask, a relatively thick portion defining the source electrode and the drain electrode; and a gap between the source electrode and the drain electrode. Forming a resist pattern having a relatively thin portion defining a region of the conductive film, a contact layer, and a semiconductor layer, a step of etching a portion not covered by the resist pattern, Removing a relatively thin portion of the resist pattern; and etching a portion of the conductive film and the contact layer that is covered by the relatively thin portion of the resist pattern to separate the source electrode and the drain electrode. 49. The method of manufacturing an active matrix substrate according to claim 48, comprising the steps of: Method. 50. The method for manufacturing an active matrix substrate according to 48 or 49, wherein the width of the channel protective layer is smaller than the width of the semiconductor region. 51. A step of forming a gate electrode on a substrate; a step of forming a gate insulating film covering the gate electrode; a step of forming a semiconductor layer on the gate insulating film; and a channel on the semiconductor layer. Forming a protective layer, and forming a positive resist layer on the channel protective layer, irradiating the substrate with light from the back side of the substrate, thereby exposing the positive resist layer, By development
Forming a first resist mask aligned with the gate electrode above the gate electrode; removing a portion of the channel protection layer that is not covered by the first resist mask; A step of arranging the contact layer in a self-aligned manner with respect to the gate electrode, a step of depositing a contact layer so as to cover the channel protective layer and the semiconductor layer, and a step of depositing a conductive film so as to cover the contact layer. Forming a source electrode and a drain electrode that intersect with the gate electrode by patterning the conductive film using the resist mask of No. 2, and further patterning the contact layer, the channel protective layer, and the semiconductor layer, The upper surface is partially covered with the channel protective film below the source electrode and the drain electrode. Forming a semiconductor region of a thin film transistor. 52. A step of forming a semiconductor region of the thin film transistor, comprising: forming a second resist mask as a second resist mask; a relatively thick portion defining the source electrode and the drain electrode; and a gap between the source electrode and the drain electrode Forming a resist pattern having a relatively thin portion defining a region of the conductive film, a contact layer, and a semiconductor layer, a step of etching a portion not covered by the resist pattern, Removing a relatively thin portion of the resist pattern; and etching a portion of the conductive film and the contact layer that is covered by the relatively thin portion of the resist pattern, thereby removing the signal wiring and the conductive member. 52. The active matrix group of claim 51, comprising the step of forming separately. The method of production. 53. The method of manufacturing an active matrix substrate according to claim 51, wherein the semiconductor layer is formed in a self-aligned manner with respect to the gate electrode by a backside exposure method before forming the contact layer. 54. After removing a relatively thin portion of the resist pattern, etching the portion of the conductive film and the contact layer which is covered by the relatively thin portion of the resist pattern. 53. The method of manufacturing an active matrix substrate according to claim 52, wherein an exposed portion of the layer is etched to leave a semiconductor region of the thin film transistor below the channel protective layer. 55. A substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and a semiconductor layer formed above the gate electrode via the gate insulating film A source electrode formed so as to intersect with the semiconductor layer, and a drain electrode formed so as to intersect with the semiconductor layer. Of the side surfaces of the semiconductor layer, the source electrode and the drain electrode extend. The thin film transistor, wherein a side surface parallel to the direction is aligned with a side surface outside the source electrode and the drain electrode. 56. The thin film transistor according to claim 55, wherein a side surface of the side surface of the semiconductor layer parallel to a direction in which the gate electrode extends is aligned with a side surface of the gate electrode. 57. between the source electrode and the semiconductor layer;
57. The thin film transistor according to claim 55, wherein a contact layer is provided between the drain electrode and the semiconductor layer. 58. A substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and a semiconductor layer formed above the gate electrode via the gate insulating film A channel protection layer formed on the semiconductor layer; a source electrode formed to cross the channel protection layer; and a drain electrode formed to cross the channel protection layer. A side surface of the channel protective layer, which is parallel to a direction in which the source electrode and the drain electrode extend, is aligned with a side surface outside the source electrode and the drain electrode. 59. The thin film transistor according to claim 58, wherein a distance between two side surfaces of the side surface of the channel protection layer parallel to a direction in which the gate electrode extends is smaller than a line width of the gate electrode. 60. The thin film transistor according to claim 58, wherein a side surface of the side surface of the semiconductor layer parallel to a direction in which the gate electrode extends is aligned with the side surface of the gate electrode. 61. A side surface of the semiconductor layer, wherein a side surface parallel to a direction in which the source electrode and the drain electrode extend is aligned with a side surface outside the source electrode and the drain electrode. A thin film transistor according to any one of the above. 62. A semiconductor device comprising: a space between the source electrode and the semiconductor layer;
62. The thin film transistor according to claim 58, wherein a contact layer is provided between the drain electrode and the semiconductor layer.