JP2002033417A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2002033417A JP2002033417A JP2000215485A JP2000215485A JP2002033417A JP 2002033417 A JP2002033417 A JP 2002033417A JP 2000215485 A JP2000215485 A JP 2000215485A JP 2000215485 A JP2000215485 A JP 2000215485A JP 2002033417 A JP2002033417 A JP 2002033417A
- Authority
- JP
- Japan
- Prior art keywords
- diameter
- solder ball
- ball
- wiring pattern
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、特にたとえばＢＧＡ
（Ball Grid Array ）型樹脂モールドパッケージを採用
した、半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor device employing a (Ball Grid Array) type resin mold package.
【０００２】[0002]
【従来の技術】この種の従来の半導体装置１では、図５
（Ａ）に示すように、基板２の表面に形成された配線パ
ターン３と、基板２の貫通孔４内に配置された半田ボー
ル５とが直接接続されていた。そして、半田ボール５の
直径と貫通孔４の直径との関係については特に考慮され
ていなかった。2. Description of the Related Art In a conventional semiconductor device 1 of this type, FIG.
As shown in (A), the wiring pattern 3 formed on the surface of the substrate 2 and the solder balls 5 arranged in the through holes 4 of the substrate 2 were directly connected. The relationship between the diameter of the solder ball 5 and the diameter of the through hole 4 has not been particularly considered.
【０００３】[0003]
【発明が解決しようとする課題】従来技術では、貫通孔
４の直径に対して半田ボール５の直径が大き過ぎたり小
さ過ぎたりする場合が生じ、前者の場合（大き過ぎる場
合）には、図５（Ｂ）に示すように、半導体装置１の実
装時に半田ボール５と配線パターン３との電気的な接続
が断たれるおそれがあった。In the prior art, the diameter of the solder ball 5 may be too large or too small with respect to the diameter of the through hole 4, and in the former case (when the diameter is too large), the diameter of the solder ball 5 becomes too small. As shown in FIG. 5B, when the semiconductor device 1 is mounted, the electrical connection between the solder ball 5 and the wiring pattern 3 may be disconnected.
【０００４】つまり、実装時に半田ボール５をリフロー
すると、半田ボール５には球形になろうとする力が作用
し、この力は、半田ボール５の直径が大きくなるほど大
きくなる。一方、半田ボール５と配線パターン３との接
合力の大きさは、接合面積が小さくなれば小さくなり、
その接合面積は、貫通孔４の直径により定まる。したが
って、貫通孔４の直径に対して半田ボール５の直径が大
き過ぎる場合には、半田ボール５が球形になろうとする
力が、半田ボール５と配線パターン３との接合力よりも
大きくなり、ボール落ち（半田ボール５が配線パターン
３から引き離される現象）を生じるおそれがあった。[0004] That is, when the solder ball 5 is reflowed during mounting, a force for making the solder ball 5 spherical is applied, and this force increases as the diameter of the solder ball 5 increases. On the other hand, the magnitude of the joining force between the solder ball 5 and the wiring pattern 3 decreases as the joining area decreases,
The joint area is determined by the diameter of the through hole 4. Therefore, when the diameter of the solder ball 5 is too large with respect to the diameter of the through hole 4, the force of the solder ball 5 to be spherical becomes larger than the bonding force between the solder ball 5 and the wiring pattern 3, and There is a possibility that a ball drop (a phenomenon in which the solder ball 5 is separated from the wiring pattern 3) may occur.
【０００５】それゆえに、この発明の主たる目的は、ボ
ール落ちを防止することにより実装不良の発生を防止で
きる、半導体装置を提供することである。[0005] Therefore, a main object of the present invention is to provide a semiconductor device capable of preventing occurrence of defective mounting by preventing ball drop.
【０００６】[0006]
【課題を解決するための手段】この発明は、貫通孔が形
成された基板と、基板の表面に形成された配線パターン
と、基板の裏面側から貫通孔を通して配線パターンに接
続された半田ボールとを備える、半導体装置において、
半田ボールの直径をＡとし、貫通孔の直径をＢとしたと
き、Ａ／Ｂ＜１．２５の関係を満たすことを特徴とす
る、半導体装置である。SUMMARY OF THE INVENTION The present invention relates to a substrate having a through hole, a wiring pattern formed on the surface of the substrate, and a solder ball connected to the wiring pattern through the through hole from the back surface of the substrate. In a semiconductor device comprising:
A semiconductor device characterized by satisfying a relationship of A / B <1.25, where A is a diameter of a solder ball and B is a diameter of a through hole.
【０００７】[0007]
【作用】半田ボールの直径をＡとし、貫通孔の直径をＢ
としたとき、Ａ／Ｂ＜１．２５の関係を満たすようにし
ているので、半田ボールが球形になろうとする力が、半
田ボールと配線パターンとの接合力よりも大きくなるこ
とはない。Ａ／Ｂ＜１．２５の関係は、ボール落ちを生
じないための条件として、発明者が実験により求めたも
のである。[Action] Let A be the diameter of the solder ball and B be the diameter of the through hole.
In this case, since the relationship of A / B <1.25 is satisfied, the force of the solder ball to be spherical does not become larger than the bonding force between the solder ball and the wiring pattern. The relationship of A / B <1.25 is obtained by experiments by the inventor as conditions for preventing ball drop.
【０００８】[0008]
【発明の効果】この発明によれば、ボール落ちを防止で
き、実装不良の発生率を大幅に低減できる。According to the present invention, falling of a ball can be prevented, and the incidence of defective mounting can be greatly reduced.
【０００９】この発明の上述の目的，その他の目的，特
徴および利点は、図面を参照して行う以下の実施例の詳
細な説明から一層明らかとなろう。The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.
【００１０】[0010]
【実施例】図１および図２に示すこの実施例の半導体装
置１０は、半導体チップ１２にＢＧＡ（Ball Grid Arra
y ）型樹脂モールドパッケージを施したものであり、簡
単に言えば、基板１４の表面に形成された配線パターン
１６と基板１４の貫通孔１８内に配置された半田ボール
２０とをフラックスのみで直接接続したものである。1 and 2 show a semiconductor device 10 of this embodiment, in which a semiconductor chip 12 has a ball grid array (BGA).
y) A mold resin package is applied. In short, the wiring pattern 16 formed on the surface of the substrate 14 and the solder balls 20 arranged in the through holes 18 of the substrate 14 are directly formed by flux only. Connected.
【００１１】基板１４は、ポリイミド，ガラスエポキシ
またはセラミック等のような絶縁材料からなり、基板１
４のダイボンディング領域には、複数（この実施例では
３６個）の貫通孔１８が行列状に形成される。The substrate 14 is made of an insulating material such as polyimide, glass epoxy or ceramic.
In the die bonding region of No. 4, a plurality (36 in this embodiment) of through holes 18 are formed in a matrix.
【００１２】配線パターン１６は、Ｃｕ等のような導電
性金属からなり、配線パターン１６の一端は貫通孔１８
の上端を閉塞するように配置され、他端は基板１４の周
縁部に配置され、この他端がボンディングパッド１６ａ
とされる。The wiring pattern 16 is made of a conductive metal such as Cu or the like.
Is disposed so as to close the upper end of the substrate 14, the other end is disposed on the periphery of the substrate 14, and the other end is
It is said.
【００１３】そして、基板１４の表面（ダイボンディン
グ領域）には、レジスト２２が形成され、レジスト２２
上には、ダイボンディングシート２４を介して半導体チ
ップ１２がダイボンディングされる。A resist 22 is formed on the surface of the substrate 14 (die bonding region).
The semiconductor chip 12 is die-bonded thereon via a die bonding sheet 24.
【００１４】ダイボンディングシート２４は、たとえば
ポリイミド樹脂やエポキシ樹脂等からなる周知のシート
状接着剤であり、このダイボンディングシート２４によ
り、レジスト２２の上面に均一な厚さで接着剤層が形成
される。ダイボンディングシート２４が熱硬化性樹脂か
らなる場合には、半導体チップ１２がダイボンディング
シート２４上に載置された後、ダイボンディングシート
２４がヒータ等により加熱され、それにより半導体チッ
プ１２がレジスト２２上に接着される。The die bonding sheet 24 is a known sheet adhesive made of, for example, a polyimide resin or an epoxy resin. The die bonding sheet 24 forms an adhesive layer on the upper surface of the resist 22 with a uniform thickness. You. When the die bonding sheet 24 is made of a thermosetting resin, after the semiconductor chip 12 is placed on the die bonding sheet 24, the die bonding sheet 24 is heated by a heater or the like, whereby the semiconductor chip 12 is Glued on top.
【００１５】そして、半導体チップ１２の上面電極１２
ａと配線パターン１６のボンディングパッド１６ａとが
金ワイヤ２６を介してワイヤボンディングされ、半導体
チップ１２および金ワイヤ２６がモールド樹脂２８によ
り封止される。The upper electrode 12 of the semiconductor chip 12
a and the bonding pad 16a of the wiring pattern 16 are wire-bonded via the gold wire 26, and the semiconductor chip 12 and the gold wire 26 are sealed with the mold resin 28.
【００１６】さらに、基板１４の下面に開口された各貫
通孔１８内には、半田ボール２０が配置され、各半田ボ
ール２０がフラックスを用いて配線パターン１６に直接
接続される。Further, solder balls 20 are arranged in the respective through holes 18 opened on the lower surface of the substrate 14, and each solder ball 20 is directly connected to the wiring pattern 16 using a flux.
【００１７】ここで、図３に示すように、半田ボール２
０の直径をＡとし、貫通孔１８の直径をＢとしたとき、
Ｂに対してＡが大き過ぎるとボール落ち（図５（Ｂ））
を生じてしまう。そこで、この発明では、Ｂに対してＡ
が大きくなり過ぎないようにこれらの関係が設定され
る。Here, as shown in FIG.
When the diameter of 0 is A and the diameter of the through hole 18 is B,
If A is too large compared to B, the ball falls (Fig. 5 (B))
Will occur. Therefore, in the present invention, A
These relations are set so that is not too large.
【００１８】つまり、Ａ／Ｂと実装不良（ボール落ち
等）の発生率との関係を発明者等が実験により調べたと
ころ、図４のグラフに示すように、Ａ／Ｂが１．２５よ
り小さい（Ａ／Ｂ＜１．２５）ときに、実装不良が生じ
ないことが分かった。したがって、この発明では、Ａお
よびＢが、Ａ／Ｂ＜１．２５の関係を満たすように設定
される。That is, when the inventors examined the relationship between A / B and the occurrence rate of mounting failures (ball drop, etc.) by experiments, as shown in the graph of FIG. When it was small (A / B <1.25), it was found that mounting failure did not occur. Therefore, in the present invention, A and B are set so as to satisfy the relationship of A / B <1.25.
【００１９】なお、半田ボール２０の直径Ａは、配線パ
ターン１６に接続する前後で変化するものではないが、
この実施例では接続前の直径Ａ（図３）を基準として、
この直径Ａが、Ａ／Ｂ＜１．２５の関係を満たすように
設定される。Although the diameter A of the solder ball 20 does not change before and after connection to the wiring pattern 16,
In this embodiment, based on the diameter A (FIG. 3) before connection,
The diameter A is set so as to satisfy the relationship of A / B <1.25.
【００２０】この実施例によれば、半田ボール２０の直
径Ａと貫通孔１８の直径Ｂとを適切に設定することによ
りボール落ちを防止でき、実装不良の発生率を大幅に低
減できる。According to this embodiment, by appropriately setting the diameter A of the solder ball 20 and the diameter B of the through hole 18, it is possible to prevent the ball from dropping, and it is possible to greatly reduce the incidence of defective mounting.
【図１】この発明の一実施例を示す図解図である。FIG. 1 is an illustrative view showing one embodiment of the present invention;
【図２】図１実施例（モールド前）の平面図である。FIG. 2 is a plan view of the embodiment of FIG. 1 (before molding).
【図３】半田ボールの直径Ａと貫通孔の直径Ｂとの関係
を示す図解図である。FIG. 3 is an illustrative view showing a relationship between a diameter A of a solder ball and a diameter B of a through hole;
【図４】Ａ／Ｂと実装不良の発生率との関係を示すグラ
フである。FIG. 4 is a graph showing the relationship between A / B and the incidence of mounting defects.
【図５】従来技術を示す図解図である。FIG. 5 is an illustrative view showing a conventional technique;
１０ …半導体装置 １２ …半導体チップ １４ …基板 １６ …配線パターン １８ …貫通孔 ２０ …半田ボール ２４ …ダイボンディングシート ２６ …金ワイヤ DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 12 ... Semiconductor chip 14 ... Substrate 16 ... Wiring pattern 18 ... Through hole 20 ... Solder ball 24 ... Die bonding sheet 26 ... Gold wire
Claims (1)
面に形成された配線パターンと、前記基板の裏面側から
前記貫通孔を通して前記配線パターンに接続された半田
ボールとを備える、半導体装置において、 前記半田ボールの直径をＡとし、前記貫通孔の直径をＢ
としたとき、Ａ／Ｂ＜１．２５の関係を満たすことを特
徴とする、半導体装置。1. A semiconductor comprising: a substrate having a through hole formed therein; a wiring pattern formed on a front surface of the substrate; and a solder ball connected to the wiring pattern through the through hole from the back side of the substrate. In the apparatus, the diameter of the solder ball is A, and the diameter of the through hole is B.
Where A / B <1.25 is satisfied.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000215485A JP2002033417A (en) | 2000-07-17 | 2000-07-17 | Semiconductor device |
| US09/906,436 US6541844B2 (en) | 2000-07-17 | 2001-07-16 | Semiconductor device having substrate with die-bonding area and wire-bonding areas |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000215485A JP2002033417A (en) | 2000-07-17 | 2000-07-17 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010021098A Division JP2010135825A (en) | 2010-02-02 | 2010-02-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002033417A true JP2002033417A (en) | 2002-01-31 |
Family
ID=18710898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000215485A Pending JP2002033417A (en) | 2000-07-17 | 2000-07-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002033417A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100703022B1 (en) * | 2004-11-29 | 2007-04-06 | 세이코 엡슨 가부시키가이샤 | Method of manufacturing electrooptical device and image forming device |
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| JPH11126852A (en) * | 1997-10-23 | 1999-05-11 | Texas Instr Japan Ltd | Semiconductor device, manufacture thereof and conductive ball mounting method |
| JPH11145192A (en) * | 1997-11-07 | 1999-05-28 | Matsushita Electric Ind Co Ltd | Method for forming solder bump |
| JPH11251353A (en) * | 1998-03-03 | 1999-09-17 | Canon Inc | Semiconductor device and its manufacture |
| JP2000252324A (en) * | 1999-03-02 | 2000-09-14 | Canon Inc | Semiconductor package and manufacture thereof |
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| JPH10256418A (en) * | 1997-03-06 | 1998-09-25 | Fujitsu Ltd | Semiconductor device and manufacture of semiconductor device |
| JPH11126852A (en) * | 1997-10-23 | 1999-05-11 | Texas Instr Japan Ltd | Semiconductor device, manufacture thereof and conductive ball mounting method |
| JPH11145192A (en) * | 1997-11-07 | 1999-05-28 | Matsushita Electric Ind Co Ltd | Method for forming solder bump |
| JPH11251353A (en) * | 1998-03-03 | 1999-09-17 | Canon Inc | Semiconductor device and its manufacture |
| JP2000252324A (en) * | 1999-03-02 | 2000-09-14 | Canon Inc | Semiconductor package and manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100703022B1 (en) * | 2004-11-29 | 2007-04-06 | 세이코 엡슨 가부시키가이샤 | Method of manufacturing electrooptical device and image forming device |
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