JP2002033406A - Method for manufacturing flash memory - Google Patents
Method for manufacturing flash memoryInfo
- Publication number
- JP2002033406A JP2002033406A JP2001092659A JP2001092659A JP2002033406A JP 2002033406 A JP2002033406 A JP 2002033406A JP 2001092659 A JP2001092659 A JP 2001092659A JP 2001092659 A JP2001092659 A JP 2001092659A JP 2002033406 A JP2002033406 A JP 2002033406A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- floating gate
- semiconductor substrate
- film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 title claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000005498 polishing Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はフラッシュメモリセ
ルの製造方法に係り、特にフローティングゲートの段差
によるステップカバレージ不良を防止したフラッシュメ
モリセルの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory cell, and more particularly to a method of manufacturing a flash memory cell in which a step coverage failure due to a step of a floating gate is prevented.
【０００２】[0002]
【従来の技術】一般に、フラッシュメモリセルは、チャ
ネル領域の半導体基板上に積層されたフローティングゲ
ート及びコントロールゲートと、フローティングゲート
の両側部の半導体基板に形成された接合領域とからな
り、コントロールゲート及び接合領域に印加されるバイ
アス電圧条件に応じてフローティングゲートに熱電子が
注入されるか、注入された電子が放電されることによ
り、プログラム或いは消去されるように構成される。2. Description of the Related Art Generally, a flash memory cell comprises a floating gate and a control gate laminated on a semiconductor substrate in a channel region, and junction regions formed on the semiconductor substrate on both sides of the floating gate. According to a bias voltage condition applied to the junction region, thermal electrons are injected into the floating gate, or the injected electrons are discharged to be programmed or erased.
【０００３】以下、前記のように構成されたフラッシュ
メモリセルの製造方法を図１に基づいて説明する。Hereinafter, a method of manufacturing the flash memory cell having the above structure will be described with reference to FIG.
【０００４】素子分離膜２が形成された半導体基板１上
にトンネル酸化膜３及びポリシリコン層４を順次形成し
た後、パターニングしてフローティングゲート４を形成
する。全体上部面に酸化膜、窒化膜及び酸化膜からなる
誘電体膜５を形成した後、前記誘電体膜５上にポリシリ
コン層６を形成し、前記ポリシリコン層６上にタングス
テンシリサイド層（ＷＳｉｘ）７を形成する。その後、
前記タングステンシリサイド層７、ポリシリコン層６及
び誘電体膜５を順次パターニングしてポリシリコン層６
とタングステンシリサイド層７とからなるコントロール
ゲートを形成し、露出された前記フローティングゲート
４の両側部の半導体基板１に不純物イオンを注入して接
合領域（図示せず）を形成する。After a tunnel oxide film 3 and a polysilicon layer 4 are sequentially formed on a semiconductor substrate 1 on which an element isolation film 2 is formed, a floating gate 4 is formed by patterning. After forming a dielectric film 5 composed of an oxide film, a nitride film and an oxide film on the entire upper surface, a polysilicon layer 6 is formed on the dielectric film 5, and a tungsten silicide layer (WSix) is formed on the polysilicon layer 6. ) 7 is formed. afterwards,
The tungsten silicide layer 7, the polysilicon layer 6, and the dielectric film 5 are sequentially patterned to form a polysilicon layer 6.
And a tungsten silicide layer 7 are formed, and impurity ions are implanted into the semiconductor substrate 1 on both sides of the exposed floating gate 4 to form a junction region (not shown).
【０００５】ところで、前述した従来の方法を用いる
と、前記フローティングゲート４の段差によって前記誘
電体膜５、ポリシリコン層６及びタングステンシリサイ
ド層７のステップカバレージが不良になる。When the above-mentioned conventional method is used, the step coverage of the dielectric film 5, the polysilicon layer 6, and the tungsten silicide layer 7 becomes poor due to the step of the floating gate 4.
【０００６】このようなステップカバレージ不良は半導
体素子の高集積化に伴うメモリセルのサイズ減少によっ
て隣接するフローティングゲート４間の距離が微細化さ
れるために一層酷くなり、酷い場合はポリシリコン層６
及びタングステンシリサイド層７を蒸着する過程でボイ
ド８が発生してコントロールゲートの自体抵抗（Ｒｓ）
が増加する。[0006] Such a step coverage defect becomes more severe because the distance between adjacent floating gates 4 becomes smaller due to the decrease in the size of the memory cell accompanying the higher integration of the semiconductor element.
In the process of depositing the tungsten silicide layer 7, voids 8 are generated and the resistance (Rs) of the control gate itself is increased.
Increase.
【０００７】ボイド８の生成を回避するためには、フロ
ーティングゲート４を成すポリシリコン層の厚さを薄く
するか、フローティングゲート４間の距離を増加させな
ければならない。しかし、フローティングゲート４の厚
さ減少はメモリセルのキャパシタンスの変化を招き、フ
ローティングゲート４間の距離減少はデザインルールと
写真工程のしきい値に影響を受けるため、難しい実状が
ある。よって、新しい工程技術の開発が望まれる。In order to avoid the formation of the voids 8, the thickness of the polysilicon layer forming the floating gate 4 must be reduced or the distance between the floating gates 4 must be increased. However, a decrease in the thickness of the floating gate 4 causes a change in the capacitance of the memory cell, and a decrease in the distance between the floating gates 4 is affected by the design rules and the threshold of the photographic process. Therefore, development of a new process technology is desired.
【０００８】[0008]
【発明が解決しようとする課題】従って、本発明の目的
は、ダマシン(damascene)工程を用いて酸化膜パターン
の間にフローティングゲートを形成した後、酸化膜パタ
ーンの厚さを減少させてフローティングゲートの段差を
減少させることにより、前記短所を解消することができ
るフラッシュメモリセルの製造方法を提供することにあ
る。Accordingly, an object of the present invention is to form a floating gate between oxide film patterns using a damascene process and then reduce the thickness of the oxide film pattern to form a floating gate. It is an object of the present invention to provide a method of manufacturing a flash memory cell which can solve the above-mentioned disadvantage by reducing the step.
【０００９】[0009]
【課題を解決するための手段】本発明に係るフラッシュ
メモリセルの製造方法は、素子分離膜が形成された半導
体基板上に酸化膜を形成した後、フローティングゲート
が形成されるべき部分の半導体基板が露出されるように
酸化膜をパターニングする段階と、全体上部面にトンネ
ル酸化膜及び第１ポリシリコン層を順次形成した後、ト
ンネル酸化膜が露出するまで第１ポリシリコン層を平坦
化してフローティングゲートを形成する段階と、露出し
た部分のトンネル酸化膜及び酸化膜を所定の厚さエッチ
ングした後、全体上部面に誘電体膜を形成する段階と、
誘電体膜上に第２ポリシリコン層、タングステンシリサ
イド層及びハードマスクを順次形成した後、パターニン
グしてコントロールゲートを形成する段階と、フローテ
ィングゲートの両側部の露出した半導体基板に不純物イ
オンを注入して接合領域を形成する段階とを含んでな
る。According to a method of manufacturing a flash memory cell according to the present invention, an oxide film is formed on a semiconductor substrate on which an element isolation film is formed, and then a portion of the semiconductor substrate where a floating gate is to be formed is formed. Patterning an oxide film so that the oxide film is exposed, forming a tunnel oxide film and a first polysilicon layer sequentially on the entire upper surface, flattening the first polysilicon layer until the tunnel oxide film is exposed, and floating the first polysilicon layer. Forming a gate, etching the exposed portion of the tunnel oxide film and the oxide film to a predetermined thickness, and then forming a dielectric film on the entire upper surface;
Forming a second polysilicon layer, a tungsten silicide layer, and a hard mask on the dielectric film in that order and then patterning to form a control gate; and implanting impurity ions into the exposed semiconductor substrate on both sides of the floating gate. Forming a bonding region by performing the above steps.
【００１０】前記酸化膜は熱酸化膜（ＨＴＯ）または高
密度プラズマ酸化膜であり、前記平坦化は化学的機械的
研磨法或いは回転を用いたウェットエッチング法で行
う。また、前記露出された部分のトンネル酸化膜及び酸
化膜を、前記フローティングゲートの厚さの２０％以上
エッチングする。The oxide film is a thermal oxide film (HTO) or a high-density plasma oxide film, and the planarization is performed by a chemical mechanical polishing method or a wet etching method using rotation. Further, the exposed portion of the tunnel oxide film and the oxide film is etched by 20% or more of the thickness of the floating gate.
【００１１】[0011]
【発明の実施の形態】以下、添付図に基づいて本発明を
詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
【００１２】図２ａ〜図２ｇは本発明に係るフラッシュ
メモリセルの製造方法を説明するための素子の断面図で
ある。FIGS. 2A to 2G are cross-sectional views of a device for explaining a method of manufacturing a flash memory cell according to the present invention.
【００１３】図２ａは素子分離膜１２が形成された半導
体基板１１上に酸化膜１３を形成した後、フローティン
グゲートが形成されるべき部分の前記酸化膜が露出され
るように感光膜パターン１４を形成した状態の断面図で
ある。前記酸化膜１３は熱酸化膜（ＨＴＯ）または高密
度プラズマ酸化膜（ＨＤＰ Ｏｘｉｄｅ）で形成し、前
記酸化膜１３の代わりに窒化膜またはシリコン窒化膜
（ＳｉＯＮ）を使用することができる。前記酸化膜１３
は５００〜２０００Åの厚さに形成する。FIG. 2A shows that after forming an oxide film 13 on a semiconductor substrate 11 on which an element isolation film 12 is formed, a photosensitive film pattern 14 is formed so that a portion of the oxide film where a floating gate is to be formed is exposed. It is sectional drawing of the state which formed. The oxide film 13 is formed of a thermal oxide film (HTO) or a high-density plasma oxide film (HDP oxide), and a nitride film or a silicon nitride film (SiON) can be used instead of the oxide film 13. The oxide film 13
Is formed to a thickness of 500 to 2000 mm.
【００１４】図２ｂは前記感光膜パターン１４をマスク
として前記酸化膜１３の露出部分をエッチングした状態
の断面図である。前記エッチング工程は−３０〜０℃の
温度で前記半導体基板１１と２：１以上のエッチング選
択比を有するエッチングガス、例えば、フッ素に酸素
（Ｏ2）が混合されたガスを用いたドライエッチング方
法で行うが、５０％以上のオーバーエッチングが行われ
るようにガスの混合比を調節する。FIG. 2B is a cross-sectional view showing a state where the exposed portion of the oxide film 13 is etched using the photosensitive film pattern 14 as a mask. The etching process is a dry etching method using an etching gas having an etching selectivity of 2: 1 or more with the semiconductor substrate 11 at a temperature of -30 to 0 ° C., for example, a gas in which oxygen (O 2 ) is mixed with fluorine. The mixing ratio of the gas is adjusted so that over-etching of 50% or more is performed.
【００１５】図２ｃは全体上部面にトンネル酸化膜１５
を形成した状態の断面図であり、図２ｄは前記トンネル
酸化膜１５上に第１ポリシリコン層１６を形成した状態
の断面図である。FIG. 2C shows a tunnel oxide film 15 on the entire upper surface.
FIG. 2D is a sectional view showing a state in which a first polysilicon layer 16 is formed on the tunnel oxide film 15.
【００１６】図２ｅは前記トンネル酸化膜１５が露出す
るまで前記第１ポリシリコン層１６を平坦化することに
より、フローティングゲート１６ａを形成した状態の断
面図である。前記平坦化は化学的機械的研磨(Chemical
Mechanical Polishing)工程或いは回転を用いたウエッ
トエッチング(Spin Wet Etch)工程により行い、平坦化
後には低エッチング率を有するエッチバックを追加的に
行う。FIG. 2E is a sectional view showing a state where the floating gate 16a is formed by flattening the first polysilicon layer 16 until the tunnel oxide film 15 is exposed. The planarization is performed by chemical mechanical polishing (Chemical mechanical polishing).
This step is performed by a mechanical polishing (Surface Polishing) process or a wet etching (Spin Wet Etch) process using rotation. After planarization, an etch-back having a low etching rate is additionally performed.
【００１７】図２ｆは露出した部分の前記トンネル酸化
膜１５及び酸化膜１３をさらに所定の厚さエッチングし
た後、全体上部面に誘電体膜１７を形成した状態の断面
図である。この際、前記フローティングゲート１６ａの
厚さの２０％以上の前記トンネル酸化膜１５及び酸化膜
１３を除去し、前記誘電体膜１７を酸化膜、窒化膜及び
酸化膜が積層されたＯＮＯ構造で形成する。FIG. 2F is a cross-sectional view showing a state where the exposed portions of the tunnel oxide film 15 and the oxide film 13 are further etched by a predetermined thickness, and a dielectric film 17 is formed on the entire upper surface. At this time, the tunnel oxide film 15 and the oxide film 13 that are 20% or more of the thickness of the floating gate 16a are removed, and the dielectric film 17 is formed with an ONO structure in which an oxide film, a nitride film, and an oxide film are stacked. I do.
【００１８】図２ｇは前記誘電体膜１７上に第２ポリシ
リコン層１８、タングステンシリサイド層１９及びハー
ドマスク２０を順次形成した状態の断面図である。FIG. 2G is a sectional view showing a state in which a second polysilicon layer 18, a tungsten silicide layer 19 and a hard mask 20 are sequentially formed on the dielectric film 17.
【００１９】次に、前記ハードマスク２０、タングステ
ンシリサイド層１９及び第２ポリシリコン層１８を順次
パターニングして、第２ポリシリコン層１８とタングス
テンシリサイド層１９とからなるコントロールゲートを
形成した後、前記フローティングゲート１６ａの両側部
の露出された半導体基板１１に不純物イオンを注入して
接合領域（図示せず）を形成する。Next, the hard mask 20, the tungsten silicide layer 19 and the second polysilicon layer 18 are sequentially patterned to form a control gate composed of the second polysilicon layer 18 and the tungsten silicide layer 19, Impurity ions are implanted into the exposed semiconductor substrate 11 on both sides of the floating gate 16a to form a junction region (not shown).
【００２０】[0020]
【発明の効果】上述したように、本発明はダマシン工程
を用いて酸化膜パターンの間にフローティングゲートが
形成されるようにした後、酸化膜パターンの厚さを減少
させてフローティングゲートの段差を減少させた後、誘
電体膜、ポリシリコン層及びタングステンシリサイド層
を順次形成する。従って、フローティングゲートの段差
減少によって誘電体膜、ポリシリコン層及びタングステ
ンシリサイド層のステップカバレージが良好になる。As described above, according to the present invention, after the floating gate is formed between the oxide film patterns using the damascene process, the thickness of the oxide film pattern is reduced to reduce the step of the floating gate. After the reduction, a dielectric film, a polysilicon layer, and a tungsten silicide layer are sequentially formed. Therefore, the step coverage of the dielectric film, the polysilicon layer, and the tungsten silicide layer is improved due to the reduction in the step of the floating gate.
【００２１】従って、本発明を用いると、ボイドの生成
が防止されてコントロールゲートの自体抵抗増加が防止
され、これにより素子の電気的特性が向上する。また、
本発明によれば、全体的な表面の段差が減少するので、
後続工程の遂行が容易になり、工程の安定化を図ること
ができて素子の歩留りが増大する。Therefore, when the present invention is used, the generation of voids is prevented and the resistance of the control gate itself is prevented from increasing, thereby improving the electrical characteristics of the device. Also,
According to the invention, the overall surface step is reduced,
The subsequent steps can be easily performed, and the steps can be stabilized, thereby increasing the yield of devices.
【図１】従来のフラッシュメモリセルの製造方法を説明
するための素子の断面図である。FIG. 1 is a cross-sectional view of an element for explaining a conventional method of manufacturing a flash memory cell.
【図２】図２ａ乃至図２ｇは、本発明に係るフラッシュ
メモリセルの製造方法を説明するための素子の断面図で
ある。FIGS. 2A to 2G are cross-sectional views of an element for explaining a method of manufacturing a flash memory cell according to the present invention.
１，１１ 半導体基板 ２，１２ 素子分離膜 ３，１５ トンネル酸化膜 ４，１６ａ フローティングゲート ５，１７ 誘電体膜 ６ ポリシリコン層 ７，１９ タングステンシリサイド層 ８ ボイド １３ 酸化膜 １４ 感光膜パターン １６ 第１ポリシリコン層 １８ 第２ポリシリコン層 ２０ ハードマスク DESCRIPTION OF SYMBOLS 1,11 Semiconductor substrate 2,12 Element isolation film 3,15 Tunnel oxide film 4,16a Floating gate 5,17 Dielectric film 6 Polysilicon layer 7,19 Tungsten silicide layer 8 Void 13 Oxide film 14 Photosensitive film pattern 16 First Polysilicon layer 18 second polysilicon layer 20 hard mask
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 27/115 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 27/115
Claims (7)
酸化膜を形成した後、フローティングゲートが形成され
るべき部分の前記半導体基板が露出されるように前記酸
化膜をパターニングする段階と、 全体上部面にトンネル酸化膜及び第１ポリシリコン層を
順次形成した後、前記トンネル酸化膜が露出するまで前
記第１ポリシリコン層を平坦化してフローティングゲー
トを形成する段階と、 露出した部分の前記トンネル酸化膜及び酸化膜を所定の
厚さエッチングした後、全体上部面に誘電体膜を形成す
る段階と、 前記誘電体膜上に第２ポリシリコン層、タングステンシ
リサイド層及びハードマスクを順次形成した後、パター
ニングしてコントロールゲートを形成する段階と、 前記フローティングゲートの両側部の露出した半導体基
板に不純物イオンを注入して接合領域を形成する段階と
を含んでなることを特徴とするフラッシュメモリセルの
製造方法。Forming an oxide film on a semiconductor substrate on which an element isolation film is formed, and then patterning the oxide film so that a portion of the semiconductor substrate where a floating gate is to be formed is exposed; Forming a floating gate by sequentially forming a tunnel oxide film and a first polysilicon layer on the entire upper surface, and planarizing the first polysilicon layer until the tunnel oxide film is exposed; Forming a dielectric film on the entire upper surface after etching the tunnel oxide film and the oxide film to a predetermined thickness, and sequentially forming a second polysilicon layer, a tungsten silicide layer, and a hard mask on the dielectric film. Forming a control gate by patterning the semiconductor substrate, and exposing the exposed semiconductor substrate on both sides of the floating gate to impurities. Method of manufacturing a flash memory cell, characterized by comprising the steps of forming a junction region by implanting ions.
密度プラズマ酸化膜のいずれか一つであることを特徴と
する請求項１記載のフラッシュメモリセルの製造方法。2. The method according to claim 1, wherein the oxide film is one of a thermal oxide film (HTO) and a high density plasma oxide film.
に形成することを特徴とする請求項１記載のフラッシュ
メモリセルの製造方法。3. The method as claimed in claim 1, wherein the oxide film is formed to a thickness of 500 to 2000 Å.
素に酸素が混合されたガスを用いたドライエッチング法
によりエッチングすることを特徴とする請求項１記載の
フラッシュメモリセルの製造方法。4. The method according to claim 1, wherein the oxide film is etched by a dry etching method using a gas in which oxygen is mixed with fluorine at a temperature of -30 to 0 ° C. .
び回転を用いたウェットエッチング工程のいずれかで行
うことを特徴とする請求項１記載のフラッシュメモリセ
ルの製造方法。5. The method according to claim 1, wherein the planarization is performed by one of a chemical mechanical polishing process and a wet etching process using rotation.
階をさらに含んでなることを特徴とする請求項１記載の
フラッシュメモリセルの製造方法。6. The method of claim 1, further comprising performing an etch back after the flattening process.
膜及び酸化膜を前記フローティングゲートの厚さの２０
％以上エッチングすることを特徴とする請求項１記載の
フラッシュメモリセルの製造方法。7. The method according to claim 7, wherein the exposed portion of the tunnel oxide film and the oxide film have a thickness of 20% of the floating gate.
2. The method according to claim 1, wherein the etching is performed by at least%.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2000-37004 | 2000-06-30 | ||
| KR10-2000-0037004A KR100415518B1 (en) | 2000-06-30 | 2000-06-30 | Method for manufacturing a flash memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002033406A true JP2002033406A (en) | 2002-01-31 |
| JP5093945B2 JP5093945B2 (en) | 2012-12-12 |
Family
ID=19675267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001092659A Expired - Fee Related JP5093945B2 (en) | 2000-06-30 | 2001-03-28 | Manufacturing method of flash memory cell |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6465293B2 (en) |
| JP (1) | JP5093945B2 (en) |
| KR (1) | KR100415518B1 (en) |
| TW (1) | TW488040B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100436290B1 (en) * | 2002-07-18 | 2004-06-16 | 주식회사 하이닉스반도체 | Method for manufacturing a flash memory device |
| JP2006128673A (en) * | 2004-10-26 | 2006-05-18 | Samsung Electronics Co Ltd | Manufacturing method of semiconductor device |
| KR100672722B1 (en) | 2005-12-29 | 2007-01-22 | 동부일렉트로닉스 주식회사 | Floating gate forming method of semiconductor memory device |
| JP2012162450A (en) * | 2012-03-23 | 2012-08-30 | National Institute Of Advanced Industrial Science & Technology | Silicon carbide mold having fine periodic structure and method for manufacturing the same |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413840B1 (en) * | 2001-03-28 | 2002-07-02 | Macronix International Co., Ltd. | Method of gettering layer for improving chemical-mechanical polishing process in flash memory production and semiconductor structure thereof |
| KR100471575B1 (en) * | 2002-12-26 | 2005-03-10 | 주식회사 하이닉스반도체 | Method of manufacturing flash memory device |
| KR100567624B1 (en) * | 2004-06-15 | 2006-04-04 | 삼성전자주식회사 | Manufacturing Method of Semiconductor Device |
| KR100539275B1 (en) * | 2004-07-12 | 2005-12-27 | 삼성전자주식회사 | Method of manufacturing a semiconductor device |
| KR100655283B1 (en) | 2004-10-13 | 2006-12-11 | 삼성전자주식회사 | Ipyrom device and its manufacturing method |
| KR100603930B1 (en) * | 2004-11-16 | 2006-07-24 | 삼성전자주식회사 | Method of forming nonvolatile memory device |
| KR100661186B1 (en) * | 2005-03-23 | 2006-12-22 | 주식회사 하이닉스반도체 | Manufacturing Method of Flash Memory Device |
| KR100685730B1 (en) * | 2005-05-02 | 2007-02-26 | 삼성전자주식회사 | Method of forming insulating film structure and method of manufacturing semiconductor device using same |
| KR100636031B1 (en) * | 2005-06-30 | 2006-10-18 | 삼성전자주식회사 | Method of manufacturing a nonvolatile memory device. |
| KR100625142B1 (en) * | 2005-07-05 | 2006-09-15 | 삼성전자주식회사 | Manufacturing Method of Semiconductor Device |
| US7790560B2 (en) * | 2007-03-12 | 2010-09-07 | Board Of Regents Of The Nevada System Of Higher Education | Construction of flash memory chips and circuits from ordered nanoparticles |
| CN106601593A (en) * | 2016-12-28 | 2017-04-26 | 武汉华星光电技术有限公司 | Method for reducing the polysilicon surface roughness |
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| JP2000077631A (en) * | 1998-08-27 | 2000-03-14 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
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| US5541130A (en) * | 1995-06-07 | 1996-07-30 | International Business Machines Corporation | Process for making and programming a flash memory array |
| KR970004034A (en) * | 1995-06-20 | 1997-01-29 | Nonvolatile Memory Cells and Manufacturing Method Thereof | |
| US5753525A (en) * | 1995-12-19 | 1998-05-19 | International Business Machines Corporation | Method of making EEPROM cell with improved coupling ratio |
| US6057193A (en) * | 1998-04-16 | 2000-05-02 | Advanced Micro Devices, Inc. | Elimination of poly cap for easy poly1 contact for NAND product |
| KR20000004244A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Method for forming a floating gate of flash memory devices |
| JP3425887B2 (en) * | 1999-03-23 | 2003-07-14 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor memory device and method of manufacturing the same |
-
2000
- 2000-06-30 KR KR10-2000-0037004A patent/KR100415518B1/en not_active IP Right Cessation
-
2001
- 2001-03-28 JP JP2001092659A patent/JP5093945B2/en not_active Expired - Fee Related
- 2001-06-15 TW TW090114501A patent/TW488040B/en active
- 2001-06-15 US US09/882,189 patent/US6465293B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000077631A (en) * | 1998-08-27 | 2000-03-14 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100436290B1 (en) * | 2002-07-18 | 2004-06-16 | 주식회사 하이닉스반도체 | Method for manufacturing a flash memory device |
| JP2006128673A (en) * | 2004-10-26 | 2006-05-18 | Samsung Electronics Co Ltd | Manufacturing method of semiconductor device |
| KR100672722B1 (en) | 2005-12-29 | 2007-01-22 | 동부일렉트로닉스 주식회사 | Floating gate forming method of semiconductor memory device |
| JP2012162450A (en) * | 2012-03-23 | 2012-08-30 | National Institute Of Advanced Industrial Science & Technology | Silicon carbide mold having fine periodic structure and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100415518B1 (en) | 2004-01-31 |
| US6465293B2 (en) | 2002-10-15 |
| US20020001898A1 (en) | 2002-01-03 |
| KR20020002718A (en) | 2002-01-10 |
| JP5093945B2 (en) | 2012-12-12 |
| TW488040B (en) | 2002-05-21 |
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