JP2002026283A - Multilayered memory device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To significantly reduce the manufacturing cost of the peripheral circuit of a multilayered memory device at the time of increasing the capacity of the memory layer by making memory multilayred. SOLUTION: The memory section 12 of a multilayered memory device is formed by laminating upon another a plurality of memory layers 12A-12B each of which is composed of a plurality of two-dimensionally arranged memory cells. The memory device is provided with one series of peripheral circuits 13 and 15 which function to find three-dimensional addresses by encoding address signals and switch sections 13 and 15 which select the memory cells corresponding to the three-dimensional addresses from the memory layers 12A-12C. Each of the memory layers 12A-12C is a simple matrix type memory layer. The peripheral circuits are a pair of peripheral circuits provided correspondingly to the rows and columns of the memory layers 12A-12C. The switch sections 13 and 15 are provided with electronic switches which are connected to the row- or column-direction electrodes of all memory cells forming each memory layer and are turned on/off in accordance with control signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device having a multilayer structure and a method of manufacturing the same, and more particularly, to a memory device having a structure in which memory layers forming a data memory section are multilayered and a method of manufacturing the same.

[0002]

2. Description of the Related Art In general, a memory device includes a memory unit for storing data, and various peripheral circuits for writing data to the memory unit and reading data from the memory unit. The memory unit is formed on a substrate as a memory layer forming a layered matrix, and peripheral circuits are arranged around the memory layer on the substrate. Since the memory layers correspond to the peripheral circuits on a one-to-one basis, when the memory layers are multilayered, the peripheral circuits are required accordingly.

FIG. 7 schematically shows an example of this multi-layer structure.
For example, when three memory layers are stacked, a first memory layer M1 is formed on the substrate BP, and data is written to and read from the memory layer near the periphery thereof. X to form a peripheral circuit
Peripheral circuits (drivers, decoders, sense amplifiers, etc.) PS1 and PS1 in the direction and the Y direction are formed. On the first memory layer M1 and the peripheral circuits PS1, PS1,
A second memory layer M2 via an interlayer insulating film (not shown)
And its peripheral circuits PS2 and PS2 are similarly formed.
Subsequently, the second memory layer M1 and the peripheral circuits PS2, P
A third memory layer M3 and its peripheral circuits PS3 and PS3 are similarly formed on S2 via an interlayer insulating film (not shown).

[0004] A similar example of multilayering is disclosed in International Publication No. WO99 /
No. 12170 in FIG. In the case of this publication, stripe-shaped electrodes are arranged on the front and back sides of the ferroelectric in the thickness direction along the X direction and the Y direction, respectively, to form a memory layer of a simple matrix type memory element. Are stacked directly above in the Z direction. At this time, the peripheral circuits of each memory layer are also stacked directly above in the Z direction.

FIG. 8 of WO 99/14762 and WO 99/14762 show still another example of multilayering.
FIG. 10 of / 14763 proposes a structure in which a ROM memory layer and an insulating layer are alternately stacked on a substrate on which peripheral circuits such as a driver and a control circuit are formed. In the case of this structure, the respective ROM memory layers are connected to each other via a driver bus formed on one side surface of the stacked body along the stacking direction.

[0006]

However, in the case of the multi-layered structure of the memory layers described above, in any case, the peripheral circuits must be prepared by the number of memory layers to be overlapped. The manufacturing cost of the process of creating the corresponding peripheral circuit is simply multiplied. In other words, the manufacturing cost is still high, and there is a problem that it is difficult to reduce the manufacturing cost in spite of increasing the memory layer and increasing the capacity.

SUMMARY OF THE INVENTION It is an object of the present invention to greatly reduce the manufacturing cost of peripheral circuits of a multilayer memory layer when increasing the capacity by increasing the number of memory layers.

[0008]

In order to achieve the above object, according to the memory device of the present invention, a memory section is formed by laminating a plurality of memory layers composed of a plurality of memory cells arranged two-dimensionally. In the memory device having the multilayer structure described above, a series of peripheral circuits having a function of obtaining a three-dimensional address by encoding a given address signal and a memory cell corresponding to the three-dimensional address are selected from the plurality of memory layers. And switching means.

[0009] This makes it possible to increase the capacity by increasing the number of memory layers, while providing switching means, as in the prior art, corresponding to the number of multilayer memory layers. As compared with a memory device provided with peripheral circuits, the cost involved in manufacturing the peripheral circuits can be significantly reduced.

[0010] The configuration of the memory device can be further developed in various ways. For example, each of the plurality of memory layers is a simple matrix type memory layer, and the one series of peripheral circuits is a pair of peripheral circuits provided corresponding to rows and columns forming a matrix of the memory layer. . At this time, the simple matrix type memory layer may be an organic thin film layer in which memory cells are selected by passive addressing drive. This organic thin film layer may be a thin film layer made of an organic material having ferroelectricity.

Further, for example, the switching means includes a memory layer selection switch section in a row direction provided in correspondence with the plurality of memory layers and a memory layer selection switch section in a column direction thereof, and a control signal is supplied to both of the switch sections. An electronic switch connected to the row-direction electrodes of all the memory cells forming each of the plurality of memory layers and turned on / off according to the control signal. And the column-directional memory layer selection switch unit includes an electronic switch that is connected to column-directional electrodes of all memory cells forming each of the plurality of memory layers and that is turned on / off in response to the control signal. Is also good. In this case, as an example, at least the peripheral circuit and the memory layer selection switch units in both the row direction and the column direction may be formed on the same substrate. As another example, at least the peripheral circuit and the memory layer selection switch sections in both the row direction and the column direction may be transfer-molded on the same substrate.

On the other hand, in the method of manufacturing a memory device having a multilayer structure according to the present invention, a step of transferring and forming at least a peripheral circuit and a memory layer selection switch portion for selecting a memory cell of each of a plurality of memory layers on a substrate. Forming a flattening film on the substrate on the side where the peripheral circuit and the memory layer selection switch portion are transferred and formed; and forming a contact hole in the flattening film at a switch output terminal of the memory layer selection switch portion. Forming a connection portion electrically connected to the semiconductor device through a memory, forming a memory layer including a memory cell having a simple matrix structure on the flattening film, forming the flattening film, and forming the connection portion And repeating the memory layer forming step in this order by the number of the plurality of memory layers. According to this method, the same operation and effect as those of the above-described basic configuration of the memory device can be obtained.

[0013] For example, in the transfer forming step, at least the peripheral circuit and the memory layer selection switch section are formed on a base via a release layer, and the release layer is irradiated with irradiation light to prevent the release layer from inter-layer or interface release. And causing at least the peripheral circuit and the memory layer selection switch section to be separated from the base and transferred and formed on the substrate.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. The memory device according to the present embodiment has a multilayer structure as shown in FIGS. 1 and 2 as a whole. 1 is a schematic plan view taken along the line II of FIG. 2, and FIG. 2 is a schematic cross-sectional view taken along the line IIA-II of FIG. As described later, the memory cell portion, the memory layer selection switch portion, and the peripheral circuits of the memory device are formed in a matrix in the X direction and the Y direction and have symmetry. The cross-sectional structure along the line IIB-IIB in FIG. 2 also appears equivalent to the cross-sectional structure along the line IIA-IIA in FIG.

As shown in FIG. 1, the memory device includes a single rectangular substrate 11, on which various memory components are integrally formed. More specifically, a memory cell portion 12 having a multilayer structure formed on the surface of the substrate 11 so as to be close to one corner thereof, and an X memory layer selection of the memory cell portion 12 which is juxtaposed in the horizontal direction in FIG. The switch unit 13 and the X peripheral circuit 14, and the Y memory layer selection switch unit 1 which is juxtaposed to the memory cell unit 12 in the upward direction in FIG.
5 and a Y peripheral circuit 16 and a control circuit 17.

A planarizing film 18 is formed on the upper surfaces of the X memory layer selection switch section 13 and the X peripheral circuit 14 and the Y memory layer selection switch section 15 and the Y peripheral circuit 16 as shown in FIG. You. X peripheral circuit 14 is responsible for selecting a word line, while Y peripheral circuit 16 is responsible for selecting a bit line.

Here, the memory cell section 12 is composed of three memory layers 12A to 12C as a multilayer structure, but the number of stacked memory layers may be plural, for example, two layers. There may be eight layers.

Each of the memory layers 12A to 12C is provided on a thin film 21 (for example, an organic thin film) formed so as to form a rectangular memory cell region, and on the front and back surfaces of the thin film 21 with the organic thin film 21 interposed therebetween. striped X stripe electrodes ₂₂ 1 through 22 _n and the Y stripe electrodes ₂₃ 1 ~ 23 _n
And X stripe electrodes ₂₂ 1 through 22 _n are plural along the X direction, is extended, the first layer selects the output end of the X memory layer selection switch section 13 one end thereof via the contact hole ₂₄ 1 to 24 _n Each is electrically connected. On the other hand, Y stripe electrodes ₂₃ 1 ~ 23 _n are plural along the Y direction, is extended, the first layer selects the output of the Y memory layer selection switch section 15 one end thereof via the contact hole ₂₅ 1 to 25 _n Each end is electrically connected.

The organic thin film 21 is composed of an X stripe electrode and a Y stripe electrode.
When the intensity of the electric field applied between the stripe electrodes exceeds a certain threshold value, the impedance (voltage-current characteristic) changes, and the impedance is not changed even when the applied electric field is set to zero. Therefore, by assigning “0” or “1” to the high impedance state and the low impedance state of the organic thin film 21, respectively, a nonvolatile memory can be realized. When such an organic thin film 21 is used, one memory cell (unit memory cell) is formed at each intersection of the X stripe electrode and the Y stripe electrode which are orthogonal to each other.

As another example of the organic thin film 21, an organic material having ferroelectricity can be used. This organic material has spontaneous polarization, and the polarization axis is inverted according to the electric field applied between the X stripe electrode and the Y stripe electrode,
Further, even when the applied electric field is set to 0, the polarization state does not change. Therefore, a nonvolatile memory can be realized by assigning "0" or "1" to the polarization state of the organic thin film 21, respectively. Such an organic thin film 21
Is used, one memory cell (unit memory cell) is formed at each intersection of the X stripe electrode and the Y stripe electrode that are orthogonal to each other.

[0021] Thus the organic thin film 21 and formed on its front and back surfaces X stripe electrodes ₂₂ 1 _{through 22} n, Y stripe electrodes ₂₃ 1 ~ 23 _n are integrally formed as one set.
A flattening film 26A is formed on the upper surface of the first memory layer 12A.
Are stacked, and a second-layer memory layer 12B having the same configuration as the above-described set is integrally formed on the upper surface of the flattening film 26A. A flattening film 26B is laminated on the upper surface of the second memory layer 12B, and a third memory layer 12C having the same configuration as the above-described set is integrally formed on the upper surface of the flattening film 26B. You. A flattening film 26C is stacked on the upper surface of the memory layer 12C to form a memory multilayer structure.

The second and third memory layers 12B and 12B
As shown in FIG. 2, each of the plurality of X stripe electrodes C also has contact holes 27 _{1 to} 27 _n and 28 _{1 to} 28 _n.
n , the second layer of the X memory layer selection switch unit 13,
Each layer is electrically connected to a switch output terminal.
This contact structure is the same for the Y memory layer selection switch section 15.

The X memory layer selection switch section 13 and the Y memory layer selection switch section 15 respond to the memory layer selection signals S1 to S3 from the control circuit 17 to store the memory layers 12A to 12A.
An electronic switch such as a TFT (thin film transistor) for selectively selecting C is provided according to the number of layers and the number of electrodes in each direction.

FIG. 3 partially shows an electric circuit system of these switch units 13 and 15. As shown in the figure, the first word line from the X peripheral circuit 14 branches into three lines, and electronic switches 131A to 131C such as TFTs are provided in the middle of each line.
Is inserted. The electronic switches 131A to 131A
The output terminal of C is connected to the contact holes 241 and 27 described above.
1, and 281 are electrically connected to the first X stripe electrodes 221 of the first to third memory layers 12A to 12C, respectively. The second and subsequent word lines of the X peripheral circuit 14 are configured in the same manner as described above, and the second and subsequent stripe electrodes 222 (... 22n) via the electronic switches 132A (... 13nA) to 132C (.
Is electrically connected to the Therefore, the electronic switch 1
31A to 13nC are three memory layer selection signals S1 to S
Three switch groups S that can be switched in response to any of
X1 to SX3.

On the other hand, the first bit line from the Y peripheral circuit 16 is branched into three, and electronic switches 151A to 151C such as TFTs are inserted in the middle of each line. The output terminals of the electronic switches 151A to 151C are electrically connected to the first Y stripe electrodes 231 of the first to third memory layers 12A to 12C via the above-described contact holes (such as 251). It is connected. The second and subsequent bit lines of the Y peripheral circuit 16 are configured in the same manner as described above, and the electronic switches 152A (...
It is electrically connected to the second and subsequent stripe electrodes 232 (... 23n) through 2C (... 15nC). Therefore, the electronic switches 151A to 15nC are classified into three switch groups SY1 to SY3 that can be switched by receiving any one of the three memory layer selection signals S1 to S3.

Each of the X peripheral circuit 14 and the Y peripheral circuit 16 includes data and a driver for performing addressing to each of the memory layers 12A to 12C to perform reading / writing of a decoder. Each word line of the X peripheral circuit 14 branches into three as shown in FIG. 3, and each branch path passes through the electronic switch 131A (.about.13nC) of each switch group SX1 (.about.SX3) of the X memory layer selection switch unit 13. Each of the X stripe electrodes 221 (２２22n) is electrically connected.
On the other hand, as shown in FIG.
The electronic switch 151 of each switch group SY1 (１SY3) of the Y memory layer selection switch unit 15 is branched.
A (〜15 nC) through each Y stripe electrode 231
(.About.23n).

The X peripheral circuit 14 and the Y peripheral circuit 16 send the decoding information to the control circuit 17 when decoding the given address signal for memory cell selection.

The control circuit 17 includes a CPU, a logic circuit, and the like that generate memory layer selection signals S1 to S3 based on decoding information from the X peripheral circuit 14 and the Y peripheral circuit 16.

Subsequently, a method of manufacturing the memory device according to the present embodiment will be described. In this manufacturing method, the peripheral circuits 14 and 16, the memory layer selection switch sections 13 and 15, and the control circuit 17, which have been formed in a desired semiconductor process in advance, are transferred to a substrate by a so-called transfer method, and the transfer is performed. It is characterized in that the flattening, the formation of the contact holes, and the formation of the memory layer are repeated on the finished substrate to realize a multilayer structure. Note that the peripheral circuits 14 and 16, the memory layer selection switch sections 13 and 15, and the control circuit may be formed on a silicon substrate by using a normal semiconductor process.

According to this manufacturing method, the memory device has a multi-layered memory layer, and the peripheral circuits 14 and 16, the memory layer selection switch sections 13 and 15, and the control circuit 17 are formed in the same layer. Even when the memory layers are multi-layered, the provision of the memory layer selection switch sections 13 and 15 has an effect that the peripheral circuits 14 and 16 can be provided in one system in each of the X direction and the Y direction.

Hereinafter, this manufacturing method will be described in detail. First, referring to FIG. 4, the peripheral circuits 14 and 16, the memory layer selection switch sections 13 and 15, and the control circuit 17 (in FIG.
The manufacturing process denoted by reference numerals “14 to 17” will be described.

First, as shown in FIG.
Peripheral circuits and the like 14 to 17 are manufactured on the base 39 via the “0”.

The base 39 has a light-transmitting property through which irradiation light can pass, and is made of a material having heat resistance and corrosion resistance to a semiconductor process for manufacturing the peripheral circuits 14 to 17. The transmittance of the irradiation light is preferably at least 10%, more preferably at least 50%. If the transmittance is too low, the attenuation of the irradiation light will increase,
This is because a larger energy is required to peel off the peeling layer 40.

The heat resistance of the base 39 may be, for example, 400 ° C. to 900 ° C. or more depending on the semiconductor process. Therefore, it is preferable that the base 39 has a property that can withstand these temperatures. If the base 39 is excellent in heat resistance, the temperature can be freely set under the manufacturing conditions of the peripheral circuits 14 to 17. The base 39 is preferably made of a material whose strain point is equal to or higher than the maximum temperature of the manufacturing process of the peripheral circuits 14 to 17. Specifically, the strain point is preferably 350 ° C. or higher, more preferably 500 ° C. or higher. Such materials include:
For example, quartz glass, soda glass, Corning 705
9. There is a heat-resistant glass such as NEC Glass OA-2.
In particular, quartz glass is excellent in heat resistance.

The strain point is such that ordinary glass is 400 ° C. to 6 ° C.
It is 1000 ° C, while it is 00 ° C. The thickness of the base 39 is not particularly limited, but is preferably about 0.1 mm to 5 mm, and more preferably 0.5 mm to 1.5 mm.
Is more preferable. If the thickness of the base 39 is too small, the strength is reduced. On the other hand, if the thickness of the base 39 is too small, the irradiation light is attenuated when the transmittance of the base 39 is low. However, when the transmittance of the irradiation light of the base 39 is high, the thickness can be increased beyond the upper limit. Also,
It is preferable that the thickness of the base 39 is uniform so that the irradiation light can reach the release layer evenly.

On the other hand, the peeling layer 40 is a thin film in which peeling (also referred to as "intralayer peeling" or "interfacial peeling") occurs in a layer or at an interface by irradiation light such as laser light. By irradiating the release layer 40 with light of a constant intensity, the release layer 4
The interatomic or intermolecular bonding force in the atoms or molecules constituting 0 disappears or decreases, and ablation (abl
ation) and the like, causing peeling. Further, the irradiation with the irradiation light may release a gas from the peeling layer 40 to cause separation. There are a case where the component contained in the release layer 40 is released as a gas to be separated and a case where the release layer 40 absorbs light to become a gas and the vapor is released to be separated.

The composition of the release layer 40 is as follows:
Various oxide ceramics such as (1) amorphous silicon, (2) silicon oxide or silicate compound, titanium oxide or titanate compound, zirconium oxide or zirconate compound, lanthanum oxide or lanthanum compound,
Alternatively, dielectrics or semiconductors, (3) nitride ceramics such as silicon nitride, aluminum nitride, and titanium nitride, (4) organic polymer materials, and (5) metals can be considered.

In this case, the amorphous silicon may contain hydrogen. The content of hydrogen is preferably about 2 at% or more, more preferably 2 at% to 20 at%. This is because, when hydrogen is contained, hydrogen is released by light irradiation to generate an internal pressure in the peeling layer 40, which promotes peeling. The hydrogen content is determined according to film formation conditions, for example, when using a CVD method, its gas composition, gas pressure, gas atmosphere, gas flow rate,
The adjustment is performed by appropriately setting conditions such as a gas temperature, a substrate temperature, and a power of light to be input.

As the silicon oxide, SiO, SiO
₂, Si₃O₂Is mentioned. Examples of silicate compounds include
For example, K₂Si₃, Li₂SiO₃, CaSiO₃, Zr
SiO₄, Na2SO3. As titanium oxide
TiO, Ti₂O₃, TiO₂Is mentioned. H
As the tanoic acid compound, for example, BaTiO₄, BaT
iO₃, CaTiO₃, SrTiO₃, PbTi₃, M
gTiO₃, ZrTi ₂, SnTiO₄, Al₂T
i₅, FeTiO₃, BaTi₅O₁₁,
You. Examples of zirconium oxide include ZrO2.
You. As the zirconate compound, for example, BaZr
O₃, ZrSiO₄, PbZrO₃, MgZrO₃, K
₂ZrO₃Is mentioned.

As the organic polymer material, -CH ₂ -,-
CO- (ketone), -CONH- (amide), -NH-
(Imido), -COO- (ester), -N = N- (azo), -CH = N- (shif) or the like (these interatomic bonds are broken by light irradiation); In particular, other compositions may be used as long as they have many of these bonds.

The organic polymer material may have an aromatic hydrocarbon (one or more benzene rings or a condensed ring thereof) in the structural formula. Specific examples of such organic polymer materials include polyolefins such as polyethylene and polypropylene, polyimides, polyamides, polyesters, polymethyl methacrylates (PMM
A), polyphenylene sulfide (PPS), polyether sulfone (PES), epoxy resin and the like.

As the metal, for example, Al, Li, T
i, Mn, In, Sn, Y, La, Ce, Nd, Pr,
Gd or Sm, or an alloy containing at least one of them is given.

The thickness of the release layer 40 is 1 nm to 20 nm.
It is preferably about μm, more preferably about 10 nm to 2 μm, and still more preferably about 40 nm to 1 μm. If the thickness of the peeling layer 40 is too thin, the uniformity of the formed film thickness is lost and the peeling becomes uneven. Conversely, if the thickness is too thick, the power (light amount) of the irradiation light required for the peeling is ) Needs to be increased, and it takes time to remove the residue of the peeling layer left after the peeling.

The method of forming the release layer 40 may be any method that can form the release layer with a uniform thickness, and can be appropriately selected according to various conditions such as the composition and thickness of the release layer 40. For example, CVD (MOCVD, low pressure CVD, ECR
-Including CVD), vapor deposition, molecular beam deposition (MB), sputtering, ion plating, PVD, etc., various vapor deposition methods, electroplating, immersion plating (dipping), electroless plating, etc. The present invention can be applied to a coating method such as a plating method, a Langmuir-Blodgett (LB) method, a spin coating method, a spray coating method, a roll coating method, various printing methods, a transfer method, an ink jet method, a powder jet method and the like. Two or more of these methods may be combined.

In particular, when the composition of the release layer 40 is amorphous silicon, it is preferable to form the film by CVD, especially low pressure CVD or plasma CVD. In the case where the release layer 10 is formed using a ceramic by a sol-gel method or when the release layer 10 is formed of an organic polymer material, it is preferable to form the film by a coating method, particularly, spin coating.

The peripheral circuits 14 to 17 are formed by a known semiconductor process, for example, formation of a silicon oxide film by a plasma CVD method using organic silane (TEOS) and oxygen as a reaction gas, and SiH _{4 by} a low pressure CVD method. It is manufactured by a process including formation of a silicon layer (device formation layer) by thermal decomposition, formation of a gate insulating film, implantation of impurity ions, a desired wiring step, and the like. As a result, peripheral circuits 14 to 17 composed of various semiconductor elements such as TFTs are manufactured.

Next, as shown in FIG.
Light is irradiated from the back surface of the substrate 9 to peel off the peripheral circuits 14 to 17 from the base 39. Irradiation light may be any as long as it causes in-layer peeling and / or interfacial peeling of the peeling layer 40, such as X-ray, ultraviolet light, visible light, infrared light (heat ray), laser light, millimeter wave, Light of each wavelength such as a microwave can be applied. Further, it may be an electron beam or a radiation (α ray, β ray, γ ray) or the like. Among them, a laser beam is preferable in that ablation easily occurs in the peeling layer.

As a laser device for generating this laser beam, various gas lasers, solid lasers (semiconductor lasers) and the like can be mentioned. In particular, excimer laser, Nd-YAG laser, argon laser, CO ₂ laser, CO laser, H
An e-Ne laser or the like is preferable, and among them, an escimer laser is particularly preferable. Since the excimer laser outputs high energy in a short wavelength range, the exfoliation layer 40 can ablate in a very short time. Therefore, there is almost no rise in the temperature of the adjacent layer or the adjacent layer, and the delamination can be achieved while minimizing the deterioration and damage of the layer.

When the peeling layer 40 has a wavelength dependency that causes ablation, the wavelength of the laser light to be irradiated is 1
It is preferably about 00 nm to 350 nm. In order to cause the release layer 40 to undergo a layer change such as gas release, vaporization, or sublimation, the wavelength of the laser light to be applied is 350
It is preferably about nm to 1200 nm.

In the case of an excimer laser, the energy density of the laser beam to be irradiated is 10 mJ / cm ² to 50 mJ / cm ^2.
It is preferably about 100 mJ / cm ² , especially 100 mJ / c.
It is more preferably about m ^{2 to} 5299 mJ / cm ² . The irradiation time is preferably about 1 nsec to 1000 nsec, and more preferably about 10 nsec to 100 nsec. If the energy density is low or the irradiation time is short, sufficient ablation does not occur, and if the energy density is high or the irradiation time is long, the irradiation light transmitted through the release layer 40 adversely affects peripheral circuits 14 to 17. There is.

The light irradiation is preferably performed so that the intensity becomes uniform. The light irradiation direction is not limited to the direction perpendicular to the release layer 40, and may be a direction inclined at a predetermined angle with respect to the release layer 40. When the area of the peeling layer 40 is larger than the irradiation area of one irradiation light, the entire area of the peeling layer 40 may be irradiated with the light in a plurality of times. Also,
The same location may be irradiated several times. Also different types,
The same region or different regions may be irradiated with light of different wavelengths (wavelength regions) a plurality of times.

Next, with reference to FIGS. 5 and 6, a description will be given of a manufacturing process of a memory device having a multilayer structure (the memory cell portion forms a simple matrix type memory element). (A) of FIG.
6E correspond to the process diagrams of FIGS. 6A to 6E, respectively, and FIG. 6 is a cross-sectional view of the manufacturing process of the memory cell portion.

First, as shown in FIGS. 5A and 6A, the peripheral circuits 14 to 17 peeled off from the base 39 are transferred and formed on the substrate 11 as shown in FIG. 4B. . The substrate 11 is not particularly limited as long as it has heat resistance, erosion resistance, and the like and has a desired mechanical strength in a later-described step of forming a flattening film, an organic thin film, an X stripe electrode, and a Y stripe electrode. Instead, a plastic substrate, a quartz substrate, or the like can be used.

Subsequently, as shown in FIGS. 5B and 6B, the memory cell region and the peripheral circuit
A flattening film 18 is formed in a region including 4 to 17, and further,
N contact holes 24 are formed for each memory layer in accordance with the connection terminal positions between the X memory layer selection switch section 13 and the n X stripe electrodes formed later. At the same time, n contact holes are formed for each memory layer in accordance with the connection terminal positions of the Y memory layer selection switch section 15 and the n Y stripe electrodes formed later.

The flattening film 18 absorbs a step between the substrate 11 and the peripheral circuits 14 to 17 transcribed and formed on the substrate 11 and enables connection between the peripheral circuits 14 to 17 and the X stripe electrode and the Y stripe electrode. The thickness is not particularly limited as long as it is a thin film having an insulating property. To form a polyimide film, for example, as the flattening film 18, an arbitrary method such as a lithography method or a printing method can be selected. When using the lithography method, spin coating, spray coating, roll coating, die coating,
The organic material may be applied by a predetermined method such as dip coating. When a silicon oxide film is formed as the flattening film 18, for example, a silicon nitride film can be formed by a plasma CVD method using organic silane (TEOS) and oxygen as a reaction gas. In this case, a plasma C using a silane-based gas and nitrogen as a reaction gas is used.
The film can be formed by a VD method or the like.

[0056] Then, as shown in FIG. 5 (C) and FIG. 6 (C), 1 layer of the contact hole ₂₄ 1-24 of n lines to be connected to the _n X stripe electrodes ₂₂ 1 through 22 _n memory cell area Formed over. To form this X stripe electrode, for example, Al, RuO ₂ , Pt, IrO
₂ , YBa ₂ Cu ₃ O ₇ , OsO ₂ , MoO ₂ , ReO
_{2, WO 2, Au, Ag} , In, In-Ga alloy, Ga
A conductive material liquid (electrode material liquid) may be prepared by dissolving fine particles of a conductive material such as a material in an appropriate solvent, and may be patterned and coated in a stripe shape using an ink jet recording head (fluid ejection head). As the solvent, butyl carbitol acetate, 3-dimethyl-2-imitazolidine, BMA, or the like can be used. As an ink jet recording head, even if it is a piezo jet type that discharges a desired fluid by a volume change of a piezoelectric element,
A bubble jet (registered trademark) system in which a fluid is discharged by sudden generation of steam by application of heat may be used. Subsequently, the applied electrode material liquid is subjected to a heat treatment to evaporate the solvent component, thereby forming n X stripe electrodes.

Next, as shown in FIGS. 5D and 6D, an organic thin film 21 is formed in the memory cell region. This organic thin film 21 has a characteristic that when the electric field intensity applied between the X stripe electrode and the Y stripe electrode exceeds a certain threshold value, the impedance (voltage-current characteristic) changes, and the impedance does not change even when the applied electric field is zero. And a material having As such an organic thin film 21, for example, Cu-TCNQ disclosed in International Publication WO 98/58383 can be used.

Note that an organic material having ferroelectricity can be used as the organic thin film 21. This organic material has spontaneous polarization, the polarization axis is inverted according to the electric field applied between the X stripe electrode and the Y stripe electrode, and the polarization state does not change even when the applied electric field is zero. ing. As such an organic thin film 21, for example, International Publication WO
A copolymer of vinylidene fluoride (vinylidenefluoride) and trifluoroethylene (trifluoroethylene) disclosed in JP-A-99 / 12170 can be used. In order to form the organic thin film 21, the above-mentioned organic material may be dissolved in a solvent such as PGMEA, cyclohexane, carbitol acetate and the like, and this may be spin-coated on the memory cell region and heat-treated. This heat treatment evaporates the solvent component in the film, and solidifies the film. Further, glycerin, diethylene glycol, ethylene glycol, or the like may be added to the solvent as a wetting agent or a binder as needed.

[0059] Then, as shown in FIG. 5 (E) and FIG. 6 (E), the an n Y stripe electrodes ₂₃ 1 ~ 23 _n to be connected to the first layer of the n contact holes 25 over the memory cell region Form. The Y stripe electrode may be formed by patterning using an ink jet recording head in the same manner as the X stripe electrode. Thus, the first memory layer 12A is completed. As shown in FIG. 2, a flattening film 26A is further formed on the upper surface of the first memory layer 12A, and the X memory layer selection switch section 13 and the Y
For each second layer of the memory layer selection switch section 15, n contact holes 27 are formed in the flattening film 26A.

Thereafter, the memory layer forming process shown in FIGS. 5C to 5E (and FIGS. 6C to 6E) is repeated to form the second memory layer 12B. In the second memory layer 12B, the region of the organic thin film and the stripe electrode slightly extends to the peripheral circuit side by the distance of the contact hole as compared with that of the first layer, but the substantial memory cell region is It is formed just above the first layer.

Next, as shown in FIG. 2, a flattening film 26B is further formed on the upper surface of the second memory layer 12B, and the X memory layer selection switch section 13 and the Y memory layer selection switch section 15 are formed. For each third layer, n contact holes 28 are formed in the flattening film 26B.

Thereafter, the above-mentioned FIGS.
(And the memory layer forming process of FIGS. 6C to 6E) is repeated to form the third memory layer 12C. In the third memory layer 12C, the area of the organic thin film and the stripe electrode slightly extends to the peripheral circuit side as much as the position of the contact hole is further distant from that of the second memory layer. Is formed immediately above the first and second layers. The flattening film 26C is formed on the third memory layer 13B.
Is formed.

When the surface of the laminated body laminated on the substrate 11 is sealed with a resin or the like, a memory device using a simple matrix type memory element is completed.

Next, the operation of the memory device will be described.
When an address signal is sent to the X peripheral circuit 14 and the Y peripheral circuit 16, the address is three-dimensionally decoded corresponding to the memory layer having a multilayer structure, and the three-dimensional address (x, y, z) is obtained. Desired. Out of the three-dimensional addresses (x, y, z), the two-dimensional address (x, y) signal is transmitted from the X peripheral circuit 14 and the Y peripheral circuit 16 to the X memory layer selection switch unit 13 and the Y memory layer selection switch unit. 15 That is, X through the word line of the X peripheral circuit 14
The x address signal is sent to the memory layer selection switch unit 13, while the y address signal is sent to the Y memory layer selection switch unit 15 via the bit line of the Y peripheral circuit 16.

The X peripheral circuit 14 and the Y peripheral circuit 16
Therefore, the z address is passed to the control circuit 17 as encoding information. Therefore, the control circuit 17 determines which of the first to third memory layers 12A to 12C the z address corresponds to, and selects a corresponding memory layer by using a memory layer selection signal. On / off control of S1 to S3.

For example, if the z address is the first memory layer 12
If there is a memory cell in A, the selection signal S1 is turned on and the selection signals S2 and S3 are turned off. As a result, in each of the X memory layer selection switch section 13 and the Y memory layer selection switch section 15, the first switch groups SX1 and SY
Electronic switches 131A to 13nA such as TFTs belonging to
And 151A to 15nA are turned on, and the other electronic switches belonging to the switch groups SX2 and SX3 and SY2 and SY3 are turned off. A two-dimensional address (x, y) signal flows to desired X-stripe electrodes 22 and Y-stripe electrodes in the first memory layer 12A via the on-state electronic switches. As a result, the first-layer memory cell 12A corresponding to the desired three-dimensional address (x, y, z)
Are selected, and data read and data write are performed.

When the z address is the second memory layer 12B or 3
The same applies to the case where it is in the second memory layer 12C.

As described above, the X memory layer selection switch unit 1
By selecting a switch group of the 3 and Y memory layer selection switch section 15, the memory layer of the z address is preferentially selected, and the memory cell of the two-dimensional address (x, y) is selected according to this selection. . As a result, a desired memory cell corresponding to the three-dimensional address (x, y, z) is finally selected, and data reading and writing are performed.

Therefore, according to the memory device of the present embodiment, the memory capacity can be increased by increasing the number of memory layers. For example, if the number of layers is eight, a memory capacity as large as eight times that of a single layer can be obtained. Moreover, while a large capacity is realized by such multi-layering, a relatively simple configuration in which a memory layer selection switch section is inserted in each of rows and columns of a memory layer in a matrix form and a control circuit is provided for the same. On the other hand, peripheral circuits for encoding, driving, etc., can be arranged in one series (only one pair of circuits corresponding to rows and columns). That is, as in the past, 8
In the case of a multi-layered memory structure with layers, there is no need for eight series of peripheral circuits, and even in that case, only one series of peripheral circuits is required. This makes it possible to significantly reduce the circuit scale of the peripheral circuit accompanying the increase in the number of memory layers. In the case of eight layers, only one-eighth is required. In addition, the required circuit area is reduced,
In addition, manufacturing costs can be reduced.

In the memory device of this embodiment, since the peripheral circuit, the memory layer selection switch section, and the control circuit are formed on the same substrate by the transfer forming method, the arrangement and positioning on the substrate are easy. Some useful effects are obtained, such as being able to produce only necessary parts, and being able to significantly reduce the manufacturing cost of memory elements due to the use of inexpensive materials such as plastic substrates as substrates. Can be

Further, since a flattening film is formed on a substrate on which a peripheral circuit, a memory layer selection switch section, and a control circuit are mounted by transfer molding, a step between the substrate and the peripheral circuit caused by the transfer formation is absorbed. As a result, a stable physical connection between the memory layer selection switch section and each stripe electrode can be ensured.

Further, since the resolution of the ink jet recording head is as fine as 400 bpi, for example, any patterning coating can be performed with an accuracy of the order of μm. Therefore, fine patterning of each stripe electrode can be performed in accordance with high integration of the memory element.

If a Y-stripe electrode is formed on an organic thin film by a conventional lithography process, the organic thin film may be damaged in processes such as resist coating, exposure, and development. Such a problem can be solved by patterning coating using a recording head. Further, in the conventional lithography process, steps such as resist coating, exposure, development and the like were required, so that capital investment was large and maintenance was troublesome. Further, since the material once applied in the etching process was removed, material wasted. However, according to the present embodiment, since the film formation and patterning of each stripe electrode can be performed at a time by the ink jet recording head, a large facility such as a factory is not required, and furthermore, the waste of material is reduced. Since it can be omitted, the manufacturing cost can be reduced.

The present invention is not limited to the embodiments described above, but can be modified in various forms.

For example, without using the control circuit in the present embodiment, the X peripheral circuit 14 and the Y peripheral circuit 16 for encoding the address signal can directly directly switch their own X memory layer selection switch section 13 and Y memory layer selection switch section. 1
The switch units may be configured to select five switch groups.

[0076]

As described above, according to the present invention, there is provided a function having a function of obtaining a three-dimensional address by encoding an address signal applied to a memory device having a multilayer structure.
Since a series peripheral circuit and switching means for selecting a memory cell corresponding to the three-dimensional address from a plurality of memory layers are provided, the memory layers can be multilayered to achieve a large capacity, and at the same time, Since only one peripheral circuit is required, the manufacturing cost of the peripheral circuit of the multi-layered memory layer can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a memory device according to an embodiment of the present invention, viewed along a line II in FIG. 2;

FIG. 2 is a schematic cross-sectional view illustrating a memory device according to an embodiment of the present invention, and is taken along lines IIA-IIA and IIB-I in FIG.
It is the figure seen along the IB line.

FIG. 3 is a partial view of an electric circuit mainly showing a memory layer selection switch unit of the memory device according to the embodiment;

FIGS. 4A and 4B are diagrams for explaining an outline of a process of forming a transfer of a peripheral circuit and the like;

FIGS. 5A to 5E are schematic perspective views illustrating manufacturing steps of a memory device.

FIGS. 6A to 6E are schematic cross-sectional views illustrating manufacturing steps of a memory device.

FIG. 7 is a diagram showing a state of forming a peripheral circuit in a conventional memory device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Substrate 12 Memory part 12A-12C memory layer 13 X memory layer selection switch part (row direction memory layer selection switch part) 131A-13nC Electronic switch 14 X peripheral circuit 15 Y memory layer selection switch part (column direction memory layer selection switch part) ) 151A～15nC electronic switch 16 Y peripheral circuit 17 control circuit 18 planarizing film 21 organic thin film 22 ₁ through 22 _n X stripe electrodes 23 ₁ ~ 23 _n Y stripe electrodes _{24 1 ~24 n, 25 1 ~25} n, 27 1 ~ 27 _n , 2
8 _{1 to} 28 _n contact holes 26A to 26C Flattening film 39 Base 40 Release layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/268 H01L 27/10 444C 27/00 301 21/26 E 51/00 27/10 444Z 29/786 29/28 21/336 29/78 613B 627D

Claims (9)

[Claims] In a memory device having a multi-layer structure in which a memory section is formed by laminating a plurality of memory layers composed of a plurality of memory cells arranged two-dimensionally, a given address signal is encoded to encode a three-dimensional address. A memory device having a multi-layer structure, comprising: a series of peripheral circuits having a desired function; and switching means for selecting a memory cell corresponding to the three-dimensional address from the plurality of memory layers. 2. The memory layer according to claim 1, wherein each of the plurality of memory layers is a simple matrix type memory layer, and the one series of peripheral circuits includes a pair of peripheral circuits provided corresponding to rows and columns forming a matrix of the memory layer. The memory device according to claim 1, which is a circuit. 3. The memory device according to claim 2, wherein said simple matrix type memory layer is an organic ferroelectric thin film layer whose memory cells are selected by a passive addressing method. 4. The memory device according to claim 3, wherein said organic thin film layer is a thin film layer made of an organic material having ferroelectricity. 5. The memory device according to claim 1, wherein said switching means comprises a memory layer selection switch section in a row direction and a memory layer selection switch section in a column direction provided corresponding to said plurality of memory layers. Control means for sending a control signal to both of the switch units, wherein the memory layer selection switch unit in the row direction is connected to a row electrode of all memory cells forming each of the plurality of memory layers, and An electronic switch that is turned on / off in response to a signal; and the column-directional memory layer selection switch unit is connected to column-directional electrodes of all memory cells forming each of the plurality of memory layers, and responds to the control signal. A memory device including an electronic switch that is turned on and off. 6. The memory device according to claim 5, wherein at least the peripheral circuit and the memory layer selection switch sections in both the row direction and the column direction are formed on the same substrate. 7. The memory device according to claim 6, wherein at least the peripheral circuit and the memory layer selection switch sections in both the row direction and the column direction are transfer-molded on the same substrate. 8. A step of transferring and forming at least a peripheral circuit and a memory layer selection switch for selecting a memory cell of each of a plurality of memory layers on a substrate, and the peripheral circuit and the memory layer selection switch are formed by transfer molding. Forming a flattening film on the substrate on the side of the memory, and forming a connection portion electrically connected to a switch output terminal of the memory layer selection switch portion via a contact hole on the flattening film. Forming a memory layer composed of memory cells having a simple matrix structure on the flattening film; and forming the flattening film forming step, the connecting portion forming step, and the memory layer forming step in this order by the plurality of memories. Repeating the process for the number of layers. 9. The manufacturing method according to claim 8, wherein in the transfer forming step, at least the peripheral circuit and the memory layer selection switch section are formed on a base via a peeling layer.
A memory layer in which the peeling layer is caused to undergo in-layer or interfacial peeling by irradiation with irradiation light, and at least the peripheral circuit and the memory layer selection switch portion are peeled off from the base and transferred onto the substrate. Manufacturing method.