JP2002016179A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for enabling flip chip connection without the need of an underfill. SOLUTION: This semiconductor device is provided with a semiconductor element, an insulation layer formed on the semiconductor element and an external connection terminal formed on the insulation layer and electrically connected to an electrode provided on the semiconductor element. In an area from the edge of the insulation layer to a flat part where the thickness of the insulation layer is almost the same, the kind of the wiring pattern of wiring for a power source or the wiring for grounding and the kind of the wiring pattern for the wiring for signals are different.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a manufacturing method of a semiconductor device for flip-chip connection.

[0002]

2. Description of the Related Art Many semiconductor devices have a laminated structure, and an insulating layer is often arranged between layers.
An opening is provided in the insulating layer, and a wiring for connecting the terminal in the lower layer and the terminal in the upper layer is formed through the opening.

The following method has been adopted as a method for forming an insulating layer. That is, a photosensitive insulating material is applied to a semiconductor device by a spin coating method, and exposure and development are performed to form openings in the insulating layer. The metal wiring connecting the lower layer terminal and the upper layer terminal is formed by applying a second photosensitive material to the upper layer of the insulating layer, exposing and developing the same, forming a mask, By using processes such as sputtering, CVD, and vapor deposition together, a metal wiring connecting the lower terminal of the insulating layer and the upper layer is formed. After the photosensitive insulating material used as the mask becomes unnecessary, it is removed.

[0004] Through the above steps, it is possible to form a wiring for connecting a terminal below the insulating layer to an upper layer. FIG. 3 is a partial cross-sectional view of the semiconductor device formed by such a process.
1 is shown. In the figure, the aluminum pad 7 is the insulating layer 1
2 are the terminals in the lower layer, and the bump pads 3 are the terminals in the upper layer of the insulating layer. Then, an insulating layer 12 having an opening is formed on the aluminum pad 7 formed on the wafer on which the semiconductor is formed. Further, a metal wiring 11 is formed from the aluminum pad 7 in the opening to the bump pad 3 in the upper layer of the insulating layer 12. A bump 10 is formed on the bump pad 3. Forming the wiring from the aluminum pad 7 to the bump pad 3 in this manner is called rewiring. In this case, the insulating layer 13
Is substantially equal to the thickness of the metal wiring 11.

[0005] One type of mounting and connecting a semiconductor device manufactured through such a process on a substrate such as a printed wiring board is flip-chip connection. FIG. 32 is a cross-sectional view of a flip-chip connected semiconductor device. The connection between the semiconductor device 13 and the substrate 14 is realized by the fact that the bumps 10 provided on the terminals of the semiconductor device 13 are solidified again after melting on the substrate. The gap between the semiconductor device 13 and the substrate 14 is filled with a highly rigid resin. In addition,
This resin is called an underfill 15 and has an effect of reinforcing the connection portion. Japanese Patent Application Laid-Open No. 11-111768 discloses an example of flip-chip connection in which underfill is performed.

[0006]

However, the above prior art has the following problems.

First, there is a difficulty in a method of supplying a resin to a gap between a semiconductor device and a substrate. That is, the gap is generally 0.3
As a method of supplying the resin to the gap of not more than mm, a method utilizing a capillary phenomenon has been adopted. However, since the resin material for the underfill is a high-viscosity liquid resin, it takes a long time to bury the resin in the gaps, resulting in poor productivity, and also has a problem that air bubbles which adversely affect connection reliability tend to remain. .

Second, it is difficult to remove the semiconductor device.
In other words, if the semiconductor device connected to the substrate is defective, even if the semiconductor device is removed from the substrate, the cured underfill material remains on the substrate even after the removal, so that the substrate can be recycled. There is a problem that is difficult.

In order to solve the first and second problems, it is desirable to connect a semiconductor device to a substrate without performing underfill. However, the underfill is performed for the purpose of preventing the destruction of the connection part due to the distortion generated in the connection part due to heat generation or the like when using the completed electric product. There is a problem that the life is extremely shortened.

By the way, in order to realize a semiconductor device which enables flip-chip connection without underfill, when a thick insulating film is formed by printing, external connection terminals and bump pads formed on the thick insulating layer are formed. Has a gap of only the thick-film insulating layer.

Therefore, when exposure is carried out by a usual method,
Exposure is not focused, resulting in insufficient resolution.

An object of the present invention is to realize a semiconductor device which enables flip-chip connection without underfill.
It is to form wiring with high accuracy.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention is structured as claimed. Thus, on a desired insulating layer (thick film insulating layer),
The above object is achieved by forming the wiring. For example, the width of the wiring is changed between the flat part and the inclined part of the thick film insulating layer, that is, the wiring is formed with high accuracy by increasing the wiring width of the inclined part. In addition, when a liquid resist is used, the thickness of the resist is increased at the boundary surface between the thick film insulating layer edge layer and the insulating layer formed below the thick film insulating layer, and the resolution is reduced. The wiring is formed with high precision by using a film resist. In this specification, this thick film insulating layer is described as a stress relaxation layer.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. Note that, in all the drawings, the same reference numerals indicate the same parts, and thus duplicate description may be omitted, and the dimensional ratio of each part is changed from the actual one in order to facilitate the description.

First, the structure of the semiconductor device according to the present embodiment will be described. A large number of semiconductor devices are manufactured collectively for each wafer, but a part of them will be described below for ease of explanation. FIG. 1 shows a partial cross-sectional view of the semiconductor device 13 of the present embodiment.

The wafer 9 on which the semiconductor circuit is formed is:
This is a wafer that has been subjected to the pre-process in the semiconductor manufacturing process and has not been divided into a large number of semiconductor devices 13 before being cut. External connection terminals, for example, aluminum pads 7 are formed on each semiconductor device 13. This aluminum pad 7
In the conventional semiconductor device 13, QFP (Quad
It is used for connecting a gold wire or the like and realizing conduction with an external terminal of the semiconductor package when the semiconductor package is placed in a semiconductor package such as a flat package. The surface of the semiconductor device 13 on which the semiconductor circuit is formed,
Except for the cut portion 24 and its periphery when cutting the wafer 9 on the aluminum pad 7 and on which a large number of semiconductors are formed into chip-shaped semiconductor devices 13, the semiconductor device is covered with the protective film 8. For the protective film 8, an insulating resin made of an inorganic material having a thickness of about 1 to 10 micrometers is used alone or in combination with an insulating resin made of an organic material. As the protective film 8, an insulating film made of an inorganic material having a thickness of about 1 to 10 micrometers is used alone, or a composite film in which an organic insulating film made of an organic material is laminated on the inorganic insulating film is used. When using this composite film, it is desirable to use a photosensitive resin material for the organic film. Examples of a photosensitive material suitable for the organic film of the protective film 8 in this embodiment include photosensitive polyimide, photosensitive benzocyclobutene, and photosensitive polybenzoxazole. In the present embodiment, not limited to this, a known and commonly used inorganic material, organic material, or a composite film thereof can be used as the protective film. For example, as an inorganic film,
SiN or SiO2 can be used. Further, the organic film may be formed so as to cover almost the entire surface of the inorganic film, but may be formed only in a region near the aluminum pad 7 as shown in FIG. FIG.
As shown in (2), it may be formed only at arbitrary plural places on the surface of the inorganic film. By limiting the region of the organic film in this manner, the warpage of the wafer 9 due to the internal stress of the protective film 8 is reduced, which is advantageous in handling in the manufacturing process, focusing during exposure, and the like. In this embodiment, the region near the aluminum pad 7 refers to a region having a maximum distance of 1 mm from the end of the aluminum pad 7. In FIGS. 33 and 34, the organic film around the aluminum pad 7 is formed in a continuous region, but may be formed in an independent region for each aluminum pad. Specifically, for example, the region is as shown in FIG. Which one of FIGS. 33 to 35 is used is determined in consideration of the pattern accuracy of the photosensitive resin used for the organic film, the internal stress of the film, and the element characteristics of the semiconductor device.
An example of the element characteristics mentioned here indicates that the level of the energy barrier in each active cell (transistor) inside the element fluctuates due to stress acting on the semiconductor device.

On the protection film 8, a stress relaxation layer 5 having a thickness of 35 to 150 micrometers is selectively formed. Although the thickness of the stress relaxation layer depends on the size of the semiconductor element, the elastic modulus of the stress relaxation layer, the thickness of the semiconductor element, and the like, it cannot be unambiguously determined, but a generally used semiconductor element thickness is about 150 to When a stress simulation experiment was performed using a bimetal model composed of a semiconductor element and a stress relaxation layer formed on the surface of the semiconductor element, the required thickness of the stress relaxation layer was preferably 10 to 200 micrometers, and more preferably 750 micrometers. Is 35 to 1
Since the thickness was found to be 50 micrometers, this example was formed in this thickness range. This corresponds to a thickness of about 1/20 to 1/5 of the thickness of the semiconductor element. If the film thickness is smaller than 35 micrometers, the desired stress relaxation cannot be obtained. If the film thickness exceeds 150 micrometers, the warpage of the wafer occurs due to the internal stress of the stress relaxation layer 5 itself. Occurs,
There is a problem that out-of-focus in an exposure process, handling troubles in a wiring forming process, and the like are likely to occur, and productivity is reduced. The stress relaxation layer 5 is formed of a semiconductor wafer 9
A much lower modulus of elasticity, e.g.
It is formed of a resin material having an elastic coefficient of GPa to 10 GPa. If the stress relaxation layer has an elastic coefficient in this range, a reliable semiconductor device can be provided. That is, in the case of a stress relaxation layer having an elastic coefficient of less than 0.1 GPa, it is difficult to support the weight of the semiconductor element itself, and a problem that characteristics are not stable when used as a semiconductor device is likely to occur. On the other hand, 10GPa
When a stress relaxation layer having an elastic coefficient exceeding the above is used, the warpage of the wafer occurs due to the internal stress of the stress relaxation layer 5 itself, causing a focus shift in an exposure process, a handling failure in a wiring formation process, and the like. And there is even the danger that the wafer may be broken. The edge portion of the stress relaxation layer 5 has a slope, and the average slope is about 5 to 30%. If the inclination angle is less than 5%, the inclination becomes too long and a desired film thickness cannot be obtained. For example, in order to obtain a thickness of 100 micrometers with an average inclination of 3% and a thickness of 100 micrometers, a horizontal distance of more than 3 millimeters is required. Will be. On the other hand, when the inclination angle is more than 30%, there is no problem in terms of the horizontal distance, but on the contrary, there is a high risk that sufficient step coverage cannot be obtained when wiring is formed. In particular, there is no process margin in the steps of plating resist rotation and exposure and development, and special skills or techniques are required. Further, when the inclination angle is large, a so-called stress concentration effect acts to concentrate the stress on the edge portion, and as a result, disconnection of the rewiring wiring 4 tends to occur at the edge portion. May require special measures. In the case of FIG. 1, the average gradient is 10% because the thickness is 50 μm at a horizontal distance of 500 μm from the edge of the stress relaxation layer 5. The rewiring wiring 4 is formed of a conductor such as copper, and connects the aluminum pad 7 to a protruding electrode on the surface of the stress relaxation layer 5, for example, the bump pad 3. On the bump pad 3,
Gold plating 2 for preventing oxidation of the bump pad 3 may be provided. The surface of the semiconductor device 13 is covered with the surface protection film 6 except for a cut portion 24 when the wafer 9 on which the bump pads 3 and a large number of semiconductors are formed is cut into the respective semiconductor devices 13.

Since the protective film 8 and the stress relieving layer 5 are completely covered with the surface protective film 6 for sealing, the protective film 8 and the stress relieving layer 5 are separated from the surface of the wafer 9 on which the semiconductor elements are formed. And the intrusion of foreign substances such as ions that cause deterioration of the performance of the semiconductor can be reduced. Also,
Since the protective film 8, the stress relieving layer 5, and the surface protective film 6 are all recessed from the cut portion 24, they are not damaged when the semiconductor device 13 is cut and separated.

As the surface protective film 6, various resin materials having electric insulating properties can be used. Since it is necessary to form a pattern, a photosensitive material is preferable, but a film may be formed by printing using a material compatible with high-precision printing, such as an inkjet method. In addition, after forming an insulating film solidly by an inexpensive coating method such as curtain coating, an etching resist is formed and patterned using a photolithography process, and using the resist pattern, the insulating film is etched and the resist is removed. May be formed. As such a material, various materials can be used in the present embodiment. Some examples thereof include (1) acrylic-modified photosensitive epoxy resin, photosensitive polyimide resin,
(2) Polyamide imide resin and polyimide resin are preferably used as ink jet printing materials, and (3) modified triazole resin, modified melamine resin, polyimide resin and the like are preferably used as solid film forming materials. More specifically, the photosensitive material may be, for example, a solder resist suitably used in a printed circuit board manufacturing process as an inexpensive photosensitive resin material, or a photosensitive polyimide used for a surface cover of a flexible printed circuit board. It is preferably used. On the other hand, as a solid film forming material, for example, Photo Nice TM of Toray Industries, Inc. is suitable. In this example, a solder resist was used. Bump pad 3
The bump 1 is formed thereon. This bump 1
Generally, it is formed of a solder material. Here, the bump 1 becomes an external connection terminal.

FIG. 2 is a plan view showing a state in which the semiconductor device 13 shown in FIG. 1 is continuously formed on a wafer, from which the bumps 1 originally existing are omitted. In FIG. 2, a hatched portion is a solder resist that is the surface protective film 6. Further, the stress relaxation layer 5 is formed in a state of being formed in a rectangular shape with rounded corners, and there is a cut portion 24 between each semiconductor device 13 as a margin when separating each semiconductor device 13. I do. The cutting margin is desirably located, for example, 10 to 100 micrometers from the end of the surface protective film 6. If it is shorter than 10 micrometers, chipping tends to be induced when each semiconductor device is separated, while if it is longer than 100 micrometers, the effective area usable as a semiconductor element decreases.
Therefore, in order to improve the yield of the semiconductor device 13, the gap between the margin and the surface protection layer 6 is set to 10 to 10 in this embodiment.
It is desirable to be located at 0 micrometer. In addition,
Although not shown, an aluminum pad 7 exists below one end of the rewiring wire 4.

According to this semiconductor device structure, since the stress relieving layer 5 exists between the rewiring wiring 4 and the wafer 9, the semiconductor device 13 is connected on the circuit board 14, and the bump 1 It is possible to disperse the distortion caused by the heat applied to the substrate. Therefore, even when the semiconductor device 13 is mounted on the circuit board 14, the connection life can be extended without performing the underfill 15. Further, since the stress relieving layer 5 has a gentle slope, there is no wiring bent portion which becomes a stress concentration portion in the middle of the rewiring wiring 4.

An example of a manufacturing process of the semiconductor device 13 in this embodiment will be described with reference to the drawings. FIG. 3 illustrates the first to third steps, FIG. 4 illustrates the fourth to sixth steps, and FIG. 5 illustrates the seventh to ninth steps. In each of the drawings, a part of the cross-sectional view is taken out so that the cross-sectional structure of the semiconductor device 13 in this embodiment can be easily understood.

First step: The wafer 9 on which the semiconductor on which the aluminum pad 7 for external connection has been formed is formed in the same step as the conventional semiconductor device 13. In the semiconductor device used in this embodiment, the material of the external connection pad is aluminum, but the external connection pad may be copper. This is because in the present embodiment, wire bonding is not used as an external connection, so that it is not necessary to consider a bonding problem that is likely to occur when the external connection pad is made of copper. If the external connection pad is made of copper, the electric resistance of the wiring can be reduced, which is desirable from the viewpoint of improving the electric characteristics of the semiconductor element.

Second step: If necessary, a protective film 8 is formed. The protective film 8 may be already formed in a so-called pre-process in a semiconductor manufacturing process using an inorganic material, or may be further formed using an organic material on an inorganic material. In this embodiment, an insulating film made of an inorganic material formed in a so-called previous step in a semiconductor process, such as silicon nitride formed by a CVD method or the like, silicon dioxide formed by tetraethoxysilane, or a composite thereof A photosensitive polyimide, which is an organic material, is applied on an insulating film made of a film, and is exposed, developed, and cured to form a protective film 8 having a thickness of about 6 micrometers. Thereby, the protective film 8 is formed on the wafer 9 on which the semiconductor is formed. In this embodiment, the protective film 8 is used.
Was set to 6 micrometers, but the required film thickness differs depending on the type of the semiconductor element.
To about 10 micrometers. It is needless to say that the organic film may be formed so as to cover almost the entire surface of the inorganic film as shown in FIG.
5, it may be formed only in a region near the aluminum pad 7. In the case of an insulating film made of only an inorganic material, the thickness range is 3 micrometers or less. In addition to the photosensitive polyimide used in the examples of the present application, polybenzoxazole, polybenzocyclobutene, polyquinoline, polyphosphazene, and the like can also be used.

Third step: A paste-like polyimide material is printed and applied to a place where the stress relaxation layer 5 is to be formed, and then cured by heating. Thereby, the stress relaxation layer 5 is formed on the protective film 8.

Fourth step: After forming a power supply film 16 for use in electroplating by a method such as sputtering, a reverse pattern 17 of wiring is formed using a photoresist.

Fifth step: Electroplating is performed using the power supply film 16 and the reverse pattern 17 of the wiring to form the wiring 4 for rewiring and the bump pad 3. Further, by repeating electroplating as necessary, the wiring 4 for rewiring has a multilayer structure.

Sixth step: The reverse pattern 17 of the wiring made of photoresist and the power supply film 16 for electroplating are removed by etching.

Seventh step: A surface protective film 6 is formed using a solder resist. Then, electroless gold plating 2 is performed on the outermost surface of the bump pad 3 using this pattern.

Eighth step: A solder ball is mounted on the bump pad 3 together with the flux, and the solder ball is connected to the bump pad 3 by heating to form the bump 1.

Ninth step: Wafer 9 on which semiconductor is formed
Is cut into semiconductor devices 13 by a wafer dicing technique.

Hereinafter, the third to eighth steps will be described in detail.

First, the third step will be described. As a mask used for printing, a mask having the same structure as a printing mask used for solder paste printing on a printed wiring board can be used. For example, as shown in FIG. 6, a metal mask in which a stencil 25 made of a nickel alloy is attached to a frame 27 via a resin sheet 26 can be used. The pattern opening 28 of the printing mask may be made smaller by about 50 μm because the paste spreads after printing by about 50 μm. As shown in FIG. 7, in paste printing, the printing mask and the pattern of the wafer 9 on which the semiconductor is formed are brought into close contact with each other in an aligned state, and the squeegee moves on the stencil 25 in this state, so that the pattern opening is performed. After filling the portion 28 and then raising the printing mask relative to the wafer 9 on which the semiconductor is formed, so-called contact printing for printing is performed. Here, the close contact between the wafer and the printing mask does not necessarily mean that there is no gap between them. This is because, since the protective film 8 is already partially formed on the wafer, it is practically difficult to bring the print mask into close contact therewith without any gap. In this example, printing was performed under printing conditions such that the gap between the wafer and the printing mask was 0 to 100 micrometers. In addition, the entire squeegee surface of the printing mask is coated with a paste using a first squeegee, and then the pattern openings 28 of the printing mask are filled with a second squeegee, and excess paste is removed. Thereafter, there is also a printing method in which the printing mask is raised relatively to the wafer 9 on which the semiconductor is formed. As shown in FIG. 8, when the print mask is raised relatively to the wafer 9, the print mask may be raised vertically, but may be moved while having a relatively inclined angle. By providing an inclination angle, the plate separation angle when the print mask is separated from the wafer tends to be uniform in the wafer surface. In addition, the print mask moves away from one end of the wafer toward the other end, and the last moment of plate separation where plate skipping tends to be unstable is performed in an area without semiconductor devices. This is also advantageous in terms of yield improvement. Further, when performing continuous printing on a plurality of wafers using the same printing machine, a step of wiping the back side of the mask plate at an appropriate timing may be inserted. For example, in the present embodiment, the back side of the mask plate was cleaned once when ten sheets were continuously printed, and then the eleventh sheet was printed.
The timing, number of times and method of cleaning the back side of the mask need to be appropriately adjusted depending on the viscosity of the paste material, the solid content concentration, the amount of the filler, and the like.

Subsequently, the wafer 9 on which the semiconductor on which the paste is printed and applied is gradually heated using a hot plate or a heating furnace, whereby the paste is hardened, and the formation of the stress relaxation layer 5 is completed.

The material for forming the stress relaxation layer 5 used here is a paste-like polyimide, which can be cured by heating after being printed and applied on the protective film 8. The paste-like polyimide is composed of a polyimide precursor, a solvent, and a large number of polyimide fine particles dispersed therein. As the fine particles, specifically, fine particles having an average particle size of 1 to 2 micrometers and a particle size distribution with a maximum particle size of about 10 micrometers were used. The polyimide precursor used in this embodiment becomes the same material as the polyimide microparticles when cured, so that when the paste-like polyimide is cured, a uniform stress relaxation layer 5 made of one kind of material is used. Is formed. In this embodiment, polyimide is used as the material for forming the stress relaxation layer, but in this embodiment, besides polyimide, amide imide resin, ester imide resin, ether imide resin, silicone resin, acrylic resin, polyester resin, resin modified from these, etc. It is also possible to use. When a resin other than polyimide is used, a treatment for imparting compatibility to the surface of the polyimide microparticles may be performed, or a resin composition may be modified so as to improve affinity with the polyimide microparticles. desirable. Among the above-listed resins, resins having an imide bond, for example, polyimide, amide imide, ester imide, ether imide, etc., have excellent thermomechanical properties, such as high-temperature strength, due to the strong skeleton by the imide bond. As a result, options for forming a plating power supply film for wiring are widened. For example, a plating power supply film forming method involving high-temperature processing such as sputtering can be selected. In the case of silicone resin, acrylic resin, polyester resin, amide imide, ester imide, ether imide and other resins that have a portion condensed by a bond other than an imide bond, thermomechanical properties are slightly inferior, but they are advantageous in terms of processability and resin price. There are cases. For example, polyesterimide resin is generally easier to handle because it has a lower curing temperature than polyimide. In the present embodiment, these resins are appropriately used in consideration of device characteristics, price, thermo-mechanical characteristics, and the like from among these resins.

By dispersing the polyimide fine particles in the paste-like polyimide, the viscoelastic properties of the material can be adjusted, so that a paste having excellent printability can be used. The thixotropic properties of the paste can be controlled by adjusting the composition of the fine particles, so that the printing properties can be improved by combining the adjustment with the viscosity. Further, the inclination angle of the stress relaxation layer 5 can be adjusted. The thixotropy characteristic of the paste suitable in the examples of the present application is a so-called thixotropy index determined from the ratio of the viscosity at a rotation speed of 1 rpm to the viscosity at a rotation speed of 10 rpm measured using a rotational viscometer.
To 3.0 is desirable. In the case of a paste having a temperature dependency in the thixotropic index, the thixotropic index is 2.0 to 3.0.
Printing is performed in a temperature range that falls within the range described above.

After the printed paste-like polyimide is cured by heating, a stress relaxation layer 5 having a sectional shape as shown in FIG. When the stress relaxation layer 5 is formed by printing in this manner, a bulge may be present at a position 200 to 1000 micrometers from the edge of the stress relaxation layer 5. By adjusting the composition of the paste-like polyimide or changing various conditions relating to printing, it is possible to control to some extent. In addition,
Various conditions related to printing in this case include metal mask thickness, squeegee speed, squeegee material, squeegee angle,
Examples include squeegee pressure (printing pressure), plate separation speed, wafer temperature during printing, and humidity in the printing environment. The control of the height and the shape of the bulging portion can be achieved by the above printing conditions. As another control method, there is a method of adjusting the structure of the protective layer 8. For example, as shown in FIG. 36, if the formation region of the organic layer of the protective film 8 is limited only to the vicinity of the pad 7, it is easy to raise the stress relaxation layer in a portion corresponding to the upper part of the organic layer.

When the bulge portion is positively formed in the stress relieving layer 5 as shown in FIG. 1, the flexure portion of the wiring 4 can be formed, thereby easily absorbing stress due to thermal expansion or the like. It becomes a structure and disconnection can be prevented more. Specifically, the maximum thickness of the stress relaxation layer 5 is about 25 micrometers, preferably 7 micrometers.
It is preferable to form a bulge portion having a height of about 12 to 12 micrometers. With such a vertex, it can be formed sufficiently by mask printing. For example, assuming that this bulge has a semicylindrical shape with a radius of 10 micrometers, the length of the half arc of the bulge is (2 × 3.1).
4 × 10 μm) /2=31.4 μm, and the redundant length of the wiring is 31.4−10 = 21.4 μm per bulge, and one wiring is formed on each side of the stress relaxation layer. In this case, it becomes 42.8 micrometers. As described above, since the redundant portion can be provided in the wiring 4, the thermal stress acting on the wiring structure and the solder joint portion is reduced, and therefore, a highly reliable wiring structure can be provided. The required thickness of this bulge is
The thickness and elastic modulus of the stress relaxation layer 5, the size of the semiconductor element 13, the power consumption of the semiconductor element, and the physical properties of the circuit board 14 on which the semiconductor element is mounted are determined from experiments and simulations. For example, in this embodiment, the diagonal length of the semiconductor element 13 is L millimeters, and the semiconductor element 13
The difference between the coefficient of linear expansion of the
Assuming that the maximum temperature range generated by the on / off operation of the semiconductor element 13 during the operation of mounting the semiconductor element 13 on the substrate is 200 degrees Celsius, the maximum thermal deformation that the wiring portion undergoes when the substrate mounted product is used in an actual use environment is: , 15 (ppm / ° C.) × L / 2 (m
m) × 200 (° C.) = 0.015 × L millimeter. Therefore, it was considered that the redundant length required for the bulge portion was sufficient if it was about 0.002 × L millimeter. From this calculation, the bulge portion is approximated by a semi-cylindrical shape. In this embodiment, the height of the bulge portion falls within a range of about L / 2000 to L / 500 mm with respect to the average thickness of the stress relaxation layer 5. I did it.

When the required thickness of the stress relaxation layer 5 is not formed by one printing and heating and curing, a predetermined thickness can be obtained by repeating printing and curing of the material a plurality of times. For example, when a metal mask having a thickness of 65 μm is used using a paste having a solid concentration of 30 to 40%, the cured film thickness obtained by two printings is about 50 μm.
Micrometers can be obtained. In particular, the thickness of the bumps 1 arranged at locations where distortion tends to concentrate when the semiconductor device 13 is connected to the circuit board 14 is limited to only the stress relaxation layers 5 at the corresponding locations and the thickness is increased. By doing so, the concentration of distortion can be reduced. For this purpose, for example, a paste-like polyimide may be printed a plurality of times on the wafer 9 on which a semiconductor is formed, using a metal mask different from that used in the first printing. In addition, as a second method, the thickness of the stress relaxation layer can be partially changed by adjusting the structure of the protective layer 8. For example, as shown in FIG. 37, only a protective layer made of an inorganic film is used in a region directly below the bump X where strain tends to concentrate, and a composite layer in which an organic film is formed on the inorganic film is protected in other regions. A membrane. When a stress relieving layer is formed on such a protective film, a gentle slope is formed in the portion A of the stress relieving layer where the organic film has the protective film and where it is not. Now, the thickness of the stress relaxation layer is 50 micrometers, its elastic modulus is 1 GPa, and the thickness of the organic film is 1
Assuming that the elastic modulus is 3 GPa at 0 micrometer, the average elastic modulus (GPa / micrometer) of the portion composed of the organic protective film and the stress relaxation layer is (3 × 10 + 1 × 5).
0) /60≒1.3, while the average elastic modulus of the inclined portion in the portion A is 1. Therefore, by adopting such a structure, the thermal stress of the stress relieving layer is dispersed from the peripheral portion to the portion where the organic protective film is formed. Can be prevented. Note that it is not always necessary to have fine particles in the stress relaxation layer, and even when fine particles are not dispersed in the paste, it is sufficient that the minimum viscoelastic properties required for printing are secured. However, when the fine particles are not dispersed in the paste, the margin of various conditions relating to printing may be extremely narrow.

Next, the fourth step will be described. In this embodiment, the wiring 4 for rewiring has two layers, namely, copper electroplating and nickel electroplating. Note that one end of the rewiring wiring 4 is connected to the bump pad 3.
May also be used. Here, a method of forming a conductor using electroplating for both copper and nickel has been described, but electroless plating can also be used.

First, a power supply film 16 for performing electroplating is formed on the entire surface of a semiconductor wafer. Here, vapor deposition, electroless copper plating, CVD, or the like can be used, but a sputter having a strong adhesive strength to the protective layer 8 and the stress relaxation layer 5 is used. As a pretreatment for the sputtering, sputter etching was performed to ensure conduction between the bonding pad 7 and the conductor 4 for rewiring.
As the sputtered film in this example, a multilayer film of chromium (75 nanometers) / copper (0.5 micrometer) was formed. The function of chromium here is to ensure adhesion between the copper located above and below it and the stress relaxation layer, etc.
The film thickness is desirably the minimum that maintains their adhesion.
When the chromium film thickness is increased, the film formation time is increased and the production efficiency is reduced.
Is exposed to the high-energy plasma generated in the sputtering chamber for a long time, and there is a risk that the materials forming these layers may be deteriorated. The required film thickness varies depending on sputter etching and sputtering conditions, chromium film quality, and the like.
The maximum is about 0.5 micrometers. In addition, instead of the chromium film used in this embodiment, a titanium film or titanium /
A platinum film, tungsten, etc. can be substituted. On the other hand, the thickness of the sputtered copper is preferably a minimum thickness that does not cause a thickness distribution of the plated film when performing the electrolytic copper plating and the electrolytic nickel plating performed in a later step. The film thickness that does not induce the film thickness distribution is determined in consideration of the amount of film loss due to washing or the like. When the thickness of the sputtered copper is made unnecessarily thick, for example, when the thickness of the copper exceeds 1 micrometer, in addition to the problem that the sputtering time becomes long and the production efficiency is reduced, the power supply to be performed in a later step is performed. When the film 16 is removed by etching, etching is inevitable for a long time, and as a result, side etching of the wiring 4 for rewiring becomes large. According to a simple calculation, when a 1 μm power supply film is etched, wiring is etched by 1 μm on one side and 2 μm on both sides. In actual production, over-etching is generally performed so as not to cause etching residue of the power supply film. Therefore, when etching the power supply film of 1 μm, the wiring is side-etched by about 5 μm. Will be. When the side etching is increased as described above, the wiring resistance is increased or the disconnection is easily caused, and a problem is likely to occur from the viewpoint of the wiring performance. Therefore, the thickness of the sputtered copper is approximately 1 micrometer at the maximum.

Next, using photolithography technology,
The reverse pattern shape 17 of the rewiring wiring 4 is formed using a resist. The thickness of the resist at the edge portion of the stress relieving layer 5 indicated by B in FIG. 4 is larger than that of other portions due to the resist flowing out from the slope portion. Therefore, in order to ensure the resolution, the negative type is preferable. When a liquid resist is used as the resist, the resist film thickness tends to be thinner at the upper part of the slope of the edge portion of the stress relaxation layer 5 shown by B in FIG. There is. A wide development margin is required to pattern resists having different film thicknesses on the upper slope and the lower slope under the same exposure amount and the same developing conditions. In general, a negative-type photosensitive resist is wider than a positive-type photosensitive characteristic resist in developing latitude with respect to the film thickness. Therefore, in this embodiment, a negative-type liquid resist is used. When a film resist is used, the film heat difference does not occur above and below the slope, so that the negative type or the positive type can be used. Therefore, in this case also, good results are often obtained by using the negative type. When the inclination of the edge portion of the stress relaxation layer 5 is large or when a film resist having weak bleaching characteristics is used, the negative type is particularly preferable. In this embodiment, FIG.
As shown in FIG. 2, an exposure machine of a type in which an exposure mask 21 and a resist 22 are in close contact with each other and a gap 20 is partially provided.
The resolution limit of the exposure machine was about 10 micrometers when the exposure mask 21 and the resist 22 were in close contact with each other. According to our experimental results, the relationship between the gap 20 below the exposure mask 21 and the wiring width to be resolved is as shown in Table 1. The values in Table 1 indicate the optical system of the exposure machine, the developing conditions,
It changes depending on the sensitivity of the resist, the resist curing condition, the ratio of the wiring width / interval, and the like. The experimental results shown in Table 1 are values obtained when the ratio of wiring width / interval is 1.0.

[0043]

[Table 1]

FIG. 11 shows a state where the connection portion 23 to the aluminum pad and the bump pad 3 are connected by the rewiring wiring 4. In the case of the exposure apparatus used in this embodiment, the gap below the exposure mask, which is the horizontal axis in Table 1, almost corresponds to the thickness of the stress relaxation layer.
If it is 0 micrometers, the width of the wiring can be resolved up to 25 micrometers. Therefore, it is also possible to set the wiring width of the signal line to 25 micrometers and the power supply or ground line to the wiring width of 40 micrometers. Further, it is also possible to make the wiring of the signal line 25 micrometers and make a part of the signal line thicker.

FIG. 12 is an enlarged view of the rewiring wiring 4 near the inclined portion of the stress relaxation layer 5. As described above, since the resist film thickness is non-uniform in the vicinity of the edge portion of the stress relieving layer 5, the development tends to be insufficient in that region. FIG. 13 shows a state in which insufficient development actually occurs at the edge portion of the stress relaxation layer 5. In this embodiment, this problem was solved by improving the wraparound of the developer. More specifically, it is a measure such as changing the wiring pattern shape as shown in FIGS.

FIG. 14 shows the case where the wiring width is increased from the connection portion 23 with the aluminum pad to the vicinity of the top of the stress relaxation layer 5.
FIG. 15 shows a case where the wiring width of only the edge portion of the stress relaxation layer 5 having poor resolution is increased. In addition, these FIG.
4 and FIG. 15 are determined in consideration of the thickness of the stress relaxation layer 5 and the resolution characteristics shown in Table 1. As another solution, a method of eliminating the undeveloped portion by extending the developing time can be considered. Further, since light is diffracted on the mask surface, the presence of the gap 20 below the exposure mask 21 may cause a reduction in resolution and a reduction in pattern accuracy.

As solutions to this phenomenon, (1) changing the optical system of the exposure machine, (2) improving the bleaching property of the resist,
(3) Optimization of pre-bake conditions for resist, (4) Multi-stage exposure, and the like. One specific example of the change of the optical system of the exposure machine is that the NA value is 0.0001 or more and 0.2 or more.
The following measures can be taken to use an exposure machine. The resolution and accuracy of the pattern can be improved by appropriately combining not only the examples given here but also known and commonly used processes.

Since the edge of the stress relaxation layer 5 has a structural feature in which stress generated due to the difference in physical properties between the wafer and the stress relaxation layer 5 tends to concentrate, it is necessary to make the wiring thick at the inclined portion of the stress relaxation layer 5. Accordingly, disconnection can be effectively prevented. Note that it is not necessary that all the wirings have the same thickness. For example, as shown in FIG. 16, the widths of the power supply / ground lines and the signal lines may be changed. In this case, it is generally desirable to make the power supply / ground line thicker than the signal line in consideration of electrical characteristics. This is because when the signal line is made thicker, the capacitance component of the wiring increases, which has an effect during high-speed operation. Conversely, power /
It is rather preferable to make the ground line thicker because the effect of stabilizing the power supply voltage can be expected. Therefore, as shown in the figure, the pattern for the signal wiring should be thickened around the edge so that only the portion where stress is concentrated can be reduced at a minimum, and the slope for the power supply or ground wiring should be uniformly thickened. Is desirable. On the other hand, in the flat portion where the stress relaxation layer is not formed, the thickness of the signal wiring is reduced in consideration of the influence of the capacitance component of the wiring. However, this must be considered each time depending on the type of semiconductor element and its wiring pattern. For example, although it depends on the semiconductor element and its wiring pattern, increasing the thickness of the protective film 8 has a great effect on reducing the capacitance of the wiring. Therefore, it is necessary to make the signal wiring thick in a flat portion where the stress relaxation layer is not formed. If not, it is desirable to form the protective film 8 thick.
Specifically, when increasing the wiring width by 10%, it is desirable to increase the thickness of the protective film 8 by about 10%.
On the other hand, the wiring width at the upper flat portion of the stress relaxation layer is limited by the wiring density rather than the signal line capacitance. That is, the upper limit value of the wiring width in the upper flat portion of the stress relieving layer is determined from the number of wirings passing through the interval between the bump pads, the diameter of the bump pad, the alignment accuracy in the wiring forming step, and the like. Specifically, as an example, the bump pad interval is 0.5
In millimeters, when the pad diameter is 300 micrometers and three wirings are drawn between the pads, (500-300) /
(3 × 2-1) = 40 From this calculation result, in this example, the average wiring width / wiring interval was set to 40 micrometers.

The fifth step will be described. In this example, copper plating was performed using a sulfuric acid acidic copper plating solution. The electrolytic copper plating was performed by washing with a surfactant, washing with water, washing with diluted sulfuric acid, and washing with water, and then connecting the power supply film 16 to the cathode and connecting the copper plate containing phosphorus to the anode.

Subsequently, electro nickel plating is performed. Before electro-nickel plating, cleaning with a surfactant,
When washing with water, washing with dilute sulfuric acid, and washing with water are performed, there is a tendency that an electro-nickel plated film having good film quality is easily obtained. The electric nickel plating was performed by connecting the power supply film 16 to the cathode and connecting the nickel plate to the anode. The electro-nickel plating suitable in this embodiment can be used in any known and commonly used nickel plating bath, and may be a watt bath system or a sulfamine bath system. Was carried out under plating conditions adjusted so as to fall within an appropriate range. Sulfamine baths have the disadvantage that the plating solution components are more expensive than the Watt bath and tend to be slightly decomposed, but the film stress is easy to control. On the other hand, the coating stress of the Watt bath generally tends to increase. Therefore, when plating with a thick film, there is a disadvantage that the risk of cracks in the wiring layer increases due to the coating stress (tensile stress) of the plating. Although a watt bath was used in this example, even when a sulfamine bath was used or a watt bath was used,
It is advisable to carry out a model experiment in advance to determine the appropriate range of the type and concentration of the additive (film stress inhibitor), plating current density, and plating solution temperature beforehand. In the present embodiment, these conditions were appropriately controlled, and before the film thickness was reduced to 10 μm or less, the conditions under which cracks did not occur in the wiring were obtained before execution. In addition, the plating film stress is one of indexes related to the metal crystal orientation of the deposited nickel, and it is necessary to appropriately control the plating film stress in order to suppress the growth of a solder diffusion layer described later. When plating is performed under conditions where the film stress is appropriately controlled, the plating film will eutect a specific amount of a minor component. For example, in the case of a film containing 0.001 to 0.05% of sulfur, the content of a specific crystal orientation plane increases. More specifically, the orientation planes 111, 220, 200, 3
11, the total content is 50% or more. The thickness of the electro-nickel plating depends on the type of solder used in the subsequent steps, reflow conditions, and product characteristics of the semiconductor device (mounting form)
To determine the optimal value. Specifically, the thickness of the alloy layer of solder and nickel formed at the time of solder reflow or mounting repair may be determined so as to be equal to or greater than the nickel plating film thickness. The thickness of the alloy layer increases as the concentration of tin in the solder increases, and increases as the upper limit of the reflow temperature increases. As described above, when the nickel layer is formed on the copper wiring as the wiring for rewiring, the wiring for rewiring is deformed by thermal stress acting between the semiconductor device and the circuit board, and when the stress is released thereafter. The wiring for rewiring can return to the shape before deformation due to the spring property of the nickel layer. For example, due to the action of thermal stress caused by the operation of the semiconductor device, the stress relieving layer and the rewiring wiring 4 formed thereon are deformed in close contact with each other. At this time, the bent portion of the redundant portion of the rewiring wiring at the bulge portion of the stress relieving layer is used for the deformation of the rewiring wiring. Thereafter, when the stress relaxation layer returns to the original shape by being released from thermal stress or the like, when the wiring for rewiring is only the copper wiring, the copper wiring does not easily return to the original wiring shape due to the spring property of the copper wiring itself. . On the other hand, when a nickel layer is formed on copper wiring,
Rewiring wiring (copper wiring) due to the spring property of the nickel layer
Can easily return to its original shape. Note that what is formed on the copper wiring is not limited to the nickel layer, but may be one having the same degree of spring property as the nickel layer on the copper wiring. In addition, when an elastic wiring is formed instead of the copper wiring, the nickel layer is not necessarily required.

In the sixth step, after performing the copper electroplating and the nickel electroplating, the resist 17 which is the reverse pattern of the wiring is removed, and the power supply film 16 formed in advance by etching is removed. For copper etching,
There are various types such as iron chloride and an alkaline etching solution. In this embodiment, an etching solution containing sulfuric acid / hydrogen peroxide as a main component was used. If the etching time is not longer than 10 seconds, control becomes difficult and disadvantageous from a practical point of view. Since there is a problem in that the etching solution becomes longer and the tact time becomes longer, the etching solution and the etching conditions may be appropriately determined by experiments. In this embodiment, an etching solution containing potassium permanganate and metasilicic acid as main components was used for the subsequent etching of the chromium portion of the power supply film 16. The electric nickel plating film is used as the power supply film 16.
It also functions as an etching resist at the time of etching. Therefore, the composition of the etching solution and the etching conditions may be determined in consideration of the etching selectivity between nickel and copper or between nickel and chromium. For example, specifically, in a sulfuric acid hydrogen peroxide etchant used for etching copper, the sulfuric acid content is 50% or less at the maximum, and preferably 15% or less. Thus, copper can be etched at an etching selectivity about 10 times that of nickel.

In the seventh step, the bump pad 3 and the cut portion 24 and the surface protective film 6 opened only at the periphery thereof were formed, and subsequently electroless gold plating was performed to deposit gold on the bump pad portion 3. . Here, a solder resist is used as the surface protective film 6, and is applied to the entire surface of the semiconductor device 13, and then exposed and developed to form a pattern. In addition, it is also possible to form the surface protective film 6 using a material such as a photosensitive polyimide or a printing polyimide other than the solder resist. Through the above steps, the surface protective film 6 completely covers the rewiring wiring 4, the stress relaxation layer 5, the protective film 8, and the like. For this reason, the surface protection film 6 includes the wiring 4 for rewiring, the stress relaxation layer 5,
Deterioration, peeling, and corrosion of the protective film 8 by the irritating substance can be suppressed.

By the seventh step, the rewiring wiring 4 and the bump pad 3 from the aluminum pad 7 to the bump pad 3 are formed on the wafer 9 on which the semiconductor is formed, as shown in FIGS. .

In the eighth step, bumps are formed using a solder ball mounting device and a reflow furnace. That is, a predetermined amount of flux and solder balls are mounted on the bump pads 3 by using the solder ball mounting device. On this occasion,
The solder balls are temporarily fixed on the bump pads by the adhesive force of the flux. When the semiconductor wafer on which the solder balls are mounted is put into a reflow furnace, the solder balls are once melted and then solidified again to form the bumps 1 connected to the bump pads 3 shown in FIG. In addition, there is also a method of printing and applying a solder paste on the bump pad 3 using a printing machine and reflowing the solder paste to form the bump 1. In any method, various solder materials can be selected, and many of the solder materials currently available on the market can be used.
In addition, although the solder material is limited, there is a method of forming the bump 1 by using a plating technique. Also,
A bump using a ball having gold or copper as a nucleus or a bump formed using a resin mixed with a conductive material may be used.

Through the steps from the first step to the ninth step, the wiring 4 for rewiring having the stress relaxation layer 5 shown in FIG. The semiconductor device 13 having no bent portion where stress concentrates in the middle of 4 can be realized. Further, by using the printing technique, the stress relaxation layer 5 which is a thick insulating layer can be formed in a pattern without using exposure and development techniques. Can have a bevel.

According to this embodiment, even when the semiconductor device 13 is flip-chip connected without underfilling, the connection reliability of the semiconductor device 13 is greatly improved. For this reason, according to the present embodiment, flip-chip connection without using an underfill can be made in many electric products, and it can be seen that the price of various electric products can be reduced. Further, since the underfill is not performed, the semiconductor device 13 can be removed. In other words, if the semiconductor device 13 connected to the circuit board is defective, the semiconductor device 13 can be removed from the circuit board and the circuit board can be regenerated, thereby also reducing the price of various electric products. It becomes possible.

Next, the material of the stress relaxation layer 5 according to this embodiment will be described. The material for forming the stress relaxation layer 5 most preferably used in the present embodiment is a paste-form polyimide, but is not limited thereto, and is a modified amide imide resin, an ester imide resin, an ether imide resin, a polyester resin, a modified silicone resin, Modified acrylic resin may be used. Among the above-listed resins, resins having an imide bond, for example, polyimide, amide imide, ester imide, ether imide, etc., have excellent thermomechanical properties, such as high-temperature strength, due to the strong skeleton by the imide bond. As a result, options for forming a plating power supply film for wiring are widened. For example, a plating power supply film forming method involving high-temperature processing such as sputtering can be selected. In the case of silicone resin, acrylic resin, polyester resin, amide imide, ester imide, ether imide and other resins that have a portion condensed by a bond other than an imide bond, thermomechanical properties are slightly inferior, but they are advantageous in terms of processability and resin price. There are cases. For example, a polyesterimide resin is generally easier to handle because it has a lower curing temperature than polyimide.
In the present embodiment, among these resins, device characteristics, price,
These resins are appropriately used in consideration of thermo-mechanical characteristics and the like. The material for forming the stress relaxation layer 5 is, for example, a resin such as epoxy, phenol, polyimide, or silicone, alone or in combination with two or more resins, and a coupling agent or a coloring agent for improving adhesion to various interfaces. Can be used in combination.

The modulus of elasticity of the stress relaxation layer 5 can be about 0.1 to 10.0 GPa at room temperature, but is preferably lower than that of general polyimide. If the elastic modulus is less than 0.1 GPa and is too small, a wiring portion is likely to be deformed when forming a protruding electrode described later or performing a function test of the semiconductor device, which may cause a problem such as disconnection. If the elastic modulus of the stress relaxation layer 5 exceeds 10.0 G, a sufficient effect of reducing stress cannot be obtained,
There is a concern that connection reliability when the semiconductor device is mounted on a substrate is reduced.

Further, it is desirable to use a material having a curing temperature of 100 ° C. to 250 ° C. for the material for the stress relaxation layer 5. If the curing temperature is lower than this, it is difficult to control in the process of manufacturing the semiconductor, and if the curing temperature is higher than this, there is a concern that the wafer stress will increase due to heat shrinkage during curing and cooling, and the characteristics of the semiconductor element will change. Because there is. After curing, the stress relaxation layer is exposed to various processes such as sputtering, plating, and etching.
Characteristics such as solvent resistance are also required. Specifically, the glass transition temperature (Tg) is preferably higher than 150 ° C. and 400 ° C. or less as heat resistance, and more preferably, the Tg is 180 ° C.
As described above, the Tg is most preferably 200 ° C. or higher. FIG.
Is an experimental result showing the relationship between the glass transition temperature (Tg) and the coefficient of linear expansion. From this, it is understood that cracks did not occur when the glass transition temperature (Tg) was 200 ° C. or higher. From the viewpoint of suppressing the amount of deformation in various temperature treatments during the process, the smaller the coefficient of linear expansion (α1) in the region of Tg or less, the better. Specifically, the closer to 3 ppm, the better. In general, the low elasticity material often has a large linear expansion coefficient. However, in this embodiment, the preferable range of the linear expansion coefficient of the material of the stress relaxation layer 5 is preferably 3 ppm to 300 ppm. More preferably, it is in the range of 3 ppm to 200 ppm, and the most desirable linear expansion coefficient is 3 ppm to 150 pp.
m. On the other hand, the thermal decomposition temperature (Td) is about 300 ° C
It is desirable that this is the case. If Tg or Td is lower than these values, there is a risk that the resin may be deformed, deteriorated or decomposed in a thermal step in the process, for example, a sputtering or sputter etching step. From the viewpoint of chemical resistance, it is desirable that the resin does not undergo any deterioration such as discoloration or deformation when immersed in a 30% aqueous sulfuric acid solution or a 10% aqueous sodium hydroxide solution for 24 hours or more. Solvent resistance includes solubility parameter (S
(P value) is desirably 8 to 20 (cal / cm3) 1/2.
When the material for the stress relaxation layer 5 is a material obtained by modifying some components to the base resin, it is desirable that most of the composition falls within the range of the solubility parameter.
More specifically, the solubility parameter (SP value) is 8
It is desirable that less than or more than 20 components do not exceed 50% by weight. If these chemical and solvent resistances are insufficient, applicable manufacturing processes may be limited, and may not be preferable from the viewpoint of reducing manufacturing costs. Practically, it is preferable to determine the material for the stress relaxation layer 5 after considering the material cost and the process flexibility satisfying these characteristics comprehensively.

Next, the relationship between the thickness of the stress relaxation layer, the wafer stress, and the α-ray will be described. FIG. 18 shows the relationship between the thickness of the stress relaxation layer and the wafer stress.
As shown in FIG. 18, when the stress relaxation layer is applied to an 8-inch diameter wafer and cured, when the film thickness exceeds 150 micrometers, the wafer stress increases, the wafer warpage increases, and the wafer warpage increases. crack,
Peeling of the insulating film or the like is likely to occur.

FIG. 19 shows the relationship between the thickness of the stress relaxation layer and the amount of α transmitted through the stress relaxation layer. α rays are generated by the decay of uranium and thorium etc. contained as impurities in the solder used for semiconductor devices,
This causes a malfunction of the transistor section. As shown in FIG. 19, when the thickness of the stress relaxation layer is larger than 35 micrometers, almost no α-rays are transmitted, and the problem of malfunction due to α-rays does not occur. Conversely, when the thickness of the stress relaxation layer is smaller than 35 micrometers, α-rays are transmitted, so that a malfunction due to α-rays is likely to occur.

From these relationships, the thickness of the stress relaxation layer is set to 3
By setting the thickness to 5 μm or more and 150 μm or less, it is possible to prevent α rays from reaching the circuit portion formed on the surface of the semiconductor element, and to ensure the reliability of connection between the semiconductor device and the substrate on which the semiconductor device is mounted. Can be.
Note that, depending on the configuration of the semiconductor device, there are a portion that is easily affected by α-rays in the same element, such as a memory cell 110 that is easily affected by transistor malfunction and a portion that is not easily affected by α-rays. Therefore, as shown in FIGS. 20 and 21, the thickness of the stress relaxation layer is set to be 35 μm or more and 150 μm or less for the portion which is particularly susceptible to α-rays, so that it is formed on the surface of the semiconductor element. Α-rays can be prevented from reaching the circuit portion. Note that, even if the thickness of the stress relaxation layer formed in a region that is hardly affected by α rays is less than 35 micrometers, there is no problem from the viewpoint of α ray shielding. Therefore, for example, as shown in FIG. 21, the stress relaxation layer is formed thick in a region where α-ray shielding is required, and the stress relaxation layer is formed thin in other regions, and the average thickness of the entire stress relaxation layer is 35 μm or more. It can be less than 150 micrometers. In such a case, it is desirable to configure the semiconductor device in consideration of the magnitude of the thermal stress strain applied to each bump. In general, a thermal stress strain tends to be increased toward the outer periphery of the semiconductor device 13 and a thicker stress relaxation layer is required. Therefore, a transistor region which is susceptible to α-rays is arranged on the outer periphery of the semiconductor device 13 and the It is preferable to arrange a region that is hardly affected by the semiconductor device 13 near the center of the semiconductor device 13. For example, as shown in FIG. 38, the thickness of the stress relaxation layer 5 can be thin near the center of the semiconductor device 13 and gradually increased toward the outer periphery. In this case, since the bump near the center has a higher connection height and a smaller connection angle than the other bumps, the stress relaxation function of the bump itself increases, and the stress relaxation function of the thinned stress relaxation layer 5 increases. Has been replaced. In the case of the semiconductor device 13 having a region that is not affected by α rays at all, if the region that is not affected by α rays is arranged near the center of the semiconductor device 13 as shown in FIG.
The stress relaxation layer 5 may not be formed in the vicinity of the center. Next, as another embodiment, an embodiment of a stress relaxation layer containing fine particles having a composition different from that of the stress relaxation layer will be described.

The fine particles contained in the stress relaxation layer 5 are made of the same material and have the same physical properties as the stress relaxation layer 5. By dispersing the fine particles in the stress relaxation layer, viscoelastic properties required for printing can be obtained.

However, in this structure, since the physical property value changes abruptly at the boundary between the wafer and the stress relaxation layer 5, there is a possibility that thermal stress or the like is concentrated at the boundary and the wiring is disconnected.

Therefore, in the present embodiment, the characteristics of the stress relaxation layer 5 formed on the circuit forming surface of the wafer are made different in the thickness direction so that the characteristics of the stress relaxation layer on the wafer surface side are close to the characteristics of the wafer. I made it.

As a result, the difference in characteristics at the boundary between the upper surface of the wafer and the lower surface of the stress relieving layer is reduced. By preventing the stress from being applied to the wiring portion, disconnection of the wiring portion can be prevented.

Furthermore, the characteristics of the stress relaxation layer 5 on the wafer side are close to those of the wafer, and the characteristics of the substrate on which the semiconductor device is mounted are close to the characteristics of the substrate. It is also effective for improving the connection life of the connection between the device and the substrate.

Here, as a characteristic that gradually changes in the thickness direction of the stress relaxation layer 5, a coefficient of thermal expansion or an elastic modulus can be considered. As a specific means for changing the characteristics of the stress relaxation layer, as shown in FIG. 22, silica particles 102 which are insulating particles are blended, and the silica particles 102 are blended in the thickness direction of the stress relaxation layer 5. The thermal expansion coefficient and the elastic modulus are gradually changed by having a distribution of the amount. In a portion where a large amount of the silica particles 102 are distributed, the thermal expansion coefficient of the stress relaxation layer 5 is small and the elastic modulus is high. On the other hand, when the blending amount of the silica particles 102 decreases, the thermal expansion coefficient increases and the elastic modulus decreases.

In the manufacturing process of the semiconductor device in this embodiment, circuit formation on a wafer, formation of a stress relaxation layer, distribution of silica particles, formation of wiring on the stress relaxation layer, and the like are performed in a wafer state, thereby simplifying the entire process. It is possible to improve the life of the wiring part with less variation during manufacturing and the like.

In this embodiment, one or two or more kinds of particles made of an inorganic material such as silica, alumina, and boron nitride, which are insulating particles for adjusting the elastic modulus and thermal expansion, are blended in the stress relaxation layer 5. If necessary, particles composed of an organic material such as polyimide or silicone may be appropriately blended.

Further, a coupling agent such as an alkoxysilane or a titanate for improving the adhesion to various interfaces constituting the silica particles and the insulating resin layer, and a thermoplastic resin for improving the breaking elongation and the breaking strength of the resin are improved. Compounding agents, dyes and pigments for coloring the insulating resin layer to prevent malfunction of the circuit section formed on the wafer due to ultraviolet rays, etc., and a curing accelerator for promoting the curing reaction of the resin layer. Is also possible.

Stress relief layer 5 whose characteristics are changed in the thickness direction
As a method of forming, for example, a liquid stress relaxation layer 5 containing the above-described material is applied on the circuit surface of the wafer, and the stress relaxation layer 5 is heated and hardened. There is a method in which insulating particles are gradually settled on the wafer side. If there is a distribution in the particle size of the silica particles,
Particles with a large particle diameter sediment faster, particles with a small particle diameter are less likely to sediment, and when heat-curing the stress relaxation layer with the wafer on the lower side, a characteristic distribution is formed in the thickness direction of the stress relaxation layer. .

As a method for controlling the concentration distribution in the thickness direction of the silica particles blended in the stress relaxation layer 5, the curing temperature and the curing temperature profile of the insulating resin are appropriately adjusted,
The amount and type of curing accelerator used to accelerate the progress of curing,
Alternatively, there is a method of appropriately blending a reaction inhibitor or the like for delaying curing, or a method of changing the particle size distribution of insulating particles such as silica particles.

The silica particles applicable to this example were obtained by crushing a lump of fused silica and ingot, or obtained by crushing a silica ingot and then heating and melting the silica particles again to form a sphere, and further synthesized. Silica particles and the like are applicable. The particle size distribution and compounding amount of the silica particles depend on the size, thickness, integration degree, thickness of the stress relaxation layer 5, particle size of the semiconductor device to which the structure of the present embodiment is applied, and the type of substrate to be mounted. Various changes are possible.

When the stress relaxation layer 5 is formed by a printing method, it may be necessary to change the particle size distribution depending on the size of a mask to be applied, depending on the printing method.

The stress relaxation layer 5 does not need to be formed by one printing, but may be formed by at least two printings as shown in FIG. Further, printing may be performed by changing the blending amount of the silica particles contained in each layer.

In this embodiment, since the physical properties of the portion where the wiring is formed do not change abruptly from the circuit portion of the wafer to the electrode provided on the stress relaxation layer, a large force is concentrated on a part of the wiring. Without breaking, the disconnection of the wiring can be prevented.

Next, an example of an embodiment of the semiconductor device 13 in which the thickness of the stress relaxation layer 5 immediately below the bump 1 near the periphery of the semiconductor device 13 is made thinner than other portions will be described with reference to FIG. . In this embodiment, the outermost bump 1a is
The height is lower by δ than the bump 1b inside one of them.

Methods for reducing the thickness of the stress relaxation layer 5 in the peripheral portion of the semiconductor device 13 include the presence or absence of fine particles, and the shape and composition of the particles contained in the stress relaxation layer forming material such as a paste-like polyimide material. There are methods for changing printing conditions such as printing speed, printing speed, printing speed, the number of printings, etc., and the ratio of solvent in the paste.

Generally, the bumps 1a located near the periphery of the semiconductor device 13 are greatly distorted as compared with the other bumps 1b and the like due to various loads after the semiconductor device 13 is connected to the circuit board 14. For example, since the linear expansion coefficient of the semiconductor device 13 is different from that of the circuit board 14, the distortion increases as the temperature of the semiconductor device 13 increases toward the bump 1 a near the periphery of the semiconductor device 13. If the distortion is large or acts repeatedly, the bump 1 from the periphery of the semiconductor device 13
a is easily broken.

When the thickness of the stress relaxation layer 5 is reduced near the periphery of the semiconductor device 13 as in this embodiment, the shape of the bump 1 at the corresponding location can be controlled, and the bump 1 is connected to the circuit board 14. At this time, the bump 1 becomes a vertically long bump 1aa as shown in FIG. In such a vertically long bump 1aa, since the volume itself is the same as the other bumps 1, the contact angle between the bump 1 and the bump pad 3 and the contact angle between the bump 1 and the pad on the circuit board 14 are increased. That is, in FIG. 25, α1> α2, β1> β
It becomes 2.

As the contact angle increases, stress concentration on the connection between the bump and the pad is reduced. As described above, the thickness of the stress relaxation layer 5 is made smaller at the peripheral portion of the semiconductor device 13 where the bump pad 3 is formed than at the other portions, and the shape of the bump 1 is made vertically long. Connection reliability can be improved. The cross-sectional shape of the stress relaxation layer 5 can be designed so that the height of the bump 1 does not hinder the connection of the semiconductor device 13 to the circuit board 14.
Various things can be considered.

The magnitude of δ is (1) the stress relaxation characteristic required for the vertical bump 1aa located at the outermost periphery, (2) the allowable value of the bump height variation at the time of the function test of the semiconductor device 13, and (3) the semiconductor. The determination is made in consideration of an allowable value of variation in bump height when the device 13 is connected to the circuit board 14. More specifically, the stress relaxation characteristics are obtained from the elastic modulus of the stress relaxation layer 5 and the size of the semiconductor device 13. On the other hand, regarding the variation at the time of functional inspection and connection,
The allowable values are determined in consideration of the deformation of the solder balls and the stress relaxation layer 5. For example, in the function inspection, if the stress relaxation layer 5 is deformed by pressing an inspection jig from the upper surface of the bump, the function inspection can be performed in a state where there is substantially no variation in bump height. Even if such an operation is performed, since the stress relieving layer 5 has a considerably lower elastic modulus than the solder bump material, the deformation of the stress relieving layer 5 takes precedence over the deformation of the solder bump. There is no scratch. Therefore, even if the value of δ required from the stress relaxation characteristics becomes larger than the variation in bump height required in the function inspection device, it is acceptable as long as the value can be accommodated by the deformation of the stress relaxation layer 5. . Further, since the stress relaxation material is an elastic body, the shape is restored after the inspection is completed, so that there is no particular problem when connecting to the substrate. Taking this into account, δ is practically determined from the above (1) and (3). As described above, the stress relaxation characteristic is such that the thickness of the stress relaxation layer 5 is 35.
Since good results can be obtained at 150 to 150 μm, δ = 150−35 = 115 μm from the stress relaxation characteristic. Further, the value of δ = 115 micrometers is almost equal to the upper limit value allowed when connecting to the circuit board 14. Therefore, the value of δ is an upper limit value in many cases of 115 micrometers.

Further, the structure of the present embodiment can be applied to a case where the miniaturization of the semiconductor device is advanced and a bump must be formed on the inclined portion of the stress relaxation layer due to the wiring of the semiconductor device. In FIG. 24, the thickness of the stress relieving layer 5 is controlled so as to make a difference in height between the outermost bump 1a and the bump 1b located inside the outermost bump 1a. There is also a method by adjusting the structure. For example,
As shown in FIG. 40, the organic layer of the protective film 8 is not formed immediately below the outermost peripheral bump 1a, or is formed only very thinly, and the organic layer of the protective film 8 is formed thicker inside the bump 1b. There is a method. There is no problem in achieving the desired height difference δ by appropriately adjusting and controlling the thickness of the stress relaxation layer 5 and the thickness of the organic layer of the protective layer 8 as necessary.

Further, since an external force is easily applied to the bumps located on the outermost periphery of the semiconductor device and cracks may be formed in the solder in some cases, some of the bumps located on the outermost periphery may be used as cushioning members. . In this case, it is desirable that the bumps used as the buffer members are not electrically connected to the aluminum pad 7 and are unnecessary for the semiconductor device to operate electrically. As a result, it is possible to extend a period until a break occurs in another bump necessary for electrically operating the semiconductor device. For some bumps used as cushioning members, the period up to the breakage of the bumps can be further extended by increasing the diameter of the bumps. In the present embodiment, any known and commonly used method may be used to increase the suitable bump diameter.
One particularly suitable method is to increase the bump land (pad) while keeping the volume of the solder identical to that of the other bumps. The larger the pad, the larger the connection diameter, while the volume of the solder is the same as the others, so the bump height decreases, and as a result,
When the bump and the pad are connected to the circuit board 14, the contact angle between the bump and the pad increases, so that stress concentration at the contact point between the bump and the pad can be avoided. Eliminating stress concentration slows the crack propagation in the solder, and the increased bump diameter increases the absolute value of the crack length before fracture, which increases the bump diameter. It greatly contributes to extension.

Further, from the viewpoint of facilitating the design of the wiring lead of the circuit board for connecting the semiconductor device, it is desirable to dispose a power supply or a ground line near the center of the semiconductor device. (A)
As shown in (b), the rewiring wiring 4 connecting the aluminum pad 7 and the bump pad which is short from the aluminum pad is a signal line, and the most wiring wiring 4 connecting the far bump pad is a power supply or ground line. It is desirable to use. In this case, a bump that is short from the aluminum pad may be located on the inclined portion of the stress relaxation layer 5. Further, the power supply or ground line may have a wider wiring width than the signal line.

FIG. 27 shows another embodiment of the semiconductor device.
In this embodiment, the stress relaxation layer 5 is formed so as to extend over the adjacent semiconductor device 13 on the wafer 9 on which the semiconductor is formed. The aluminum pad 7, the bump pad 3, and the rewiring wiring 4 connecting these are designed in such a way that the rewiring wiring 4 does not cross the boundary between the semiconductor device 13 and the adjacent semiconductor device 13. Has been made. The manufacturing process is basically the same as that described above, but differs from the seventh process.

When cutting the semiconductor wafer, it is necessary to cut the stress relieving layer 5. However, since the stress relieving layer 5 is made of a low elastic material, a semiconductor composed mostly of silicon and having different strengths is formed. It is difficult to cut the wafer 9 together. For this reason, first, after cutting the stress relaxation layer 5, the wafer 9 on which the semiconductor is formed is diced. This will be described below with reference to FIG.

First, only the stress relaxation layer 5 is cut in the seventh improvement step. As a cutting method, it is preferable to use a rotary blade suitable for cutting a low elastic resin material. In addition, a carbon dioxide laser, sand blast, or the like can be used.

In the eighth improvement step, a solder resist is applied as a surface protective film 6 on the entire surface. As an application method, printing using a mesh mask or curtain coating may be used in addition to the spin coating method. In order to apply the solder resist, it is desirable that the wall surface of the cut portion of the stress relaxation layer 5 in the seventh improvement step is not vertical but has an inverted V shape. By performing this coating after cutting the stress relaxation layer in the seventh improvement step, the stress relaxation layer 5 may cause separation from the surface of the wafer 9 on which the semiconductor is formed, ions such as ions that cause performance deterioration of the semiconductor, and the like. It is possible to provide a device that can reduce intrusion of foreign matters and ensure durability and the like.

In the ninth improvement step, a pattern of the surface protective film 6 is formed by performing photosensitive development. As a result, only the bump pad 3 and the cut portion 24 and the periphery thereof are exposed from the surface protection film 6. Further, gold is formed on the bump pads 3 by performing electroless gold plating using the surface protective film 6 as a mask. Although only gold plating is used in the embodiment, palladium or platinum plating may be applied before gold plating, or tin plating after gold plating has no particular problem.

In the tenth improvement step, the wafer 9 on which the semiconductor has been formed by dicing is divided into semiconductor devices 13. In general, dicing is performed using a rotary blade.

Through the above steps, it is possible to manufacture the semiconductor device 13 including the step of cutting the stress relaxation layer 5.

According to the present embodiment, even when the external dimensions of the semiconductor device 13 are small, the stress relaxation layer 5 can be formed without any problem. More specifically, when the stress relaxation layer 5 is formed over two adjacent semiconductor devices, it is not necessary to change the film formation technique of the stress relaxation layer 5 even when the external dimensions are almost halved. By using the same print mask even if the size of the semiconductor device is changed by adjusting the shape and external dimensions of the semiconductor device 13 and the width and shape of the cut portion 24 as a margin for separating the semiconductor device 13 from each other. In some cases, this is possible. Further, since the wiring 4 for rewiring connects the aluminum pad 7 and the bump pad 3 via the inclined portion of the stress relieving layer 5 as in the first embodiment, the stress concentration portion also exists in the wiring 4 for rewiring. Flip chip connection that does not exist and does not require underfill can be performed.

The structure according to the present embodiment is particularly applicable to a semiconductor device in which pads are laid out at the center of the semiconductor device, such as a DRAM.

In the figures of the present embodiment, the stress relaxation layer 5 extending over two adjacent semiconductor devices 13 is cut. As long as the portion exists, it is also possible to adopt a structure in which the stress relaxation layer 5 connected to at least two or more semiconductor devices 13, for example, four semiconductor devices adjacent to each other, is cut. As a matter of course, the stress relaxation layers 5 connected in two adjacent rows may be formed and cut. In this case, since the manufacturing method is such that positional displacement in the column direction can be tolerated, the method can be applied to finer processing.

In each embodiment, for example, FIG.
As shown in FIG. 7, the corners of the stress relaxation layer 5 may be rounded. In the case where the rounding is not performed, a defect that air bubbles are involved when printing the stress relaxation layer 5 using the paste-like polyimide material is sometimes observed. Further, the stress relaxation layer 5 is easily peeled from the corner. If air bubbles remain in the stress relieving layer 5, when the semiconductor device 13 is heated, the air bubbles burst, causing problems such as disconnection of the rewiring wiring 4. For this reason, it is desirable that the corners of the pattern openings 18 of the printing metal mask used for forming the stress relaxation layer 5 be rounded.

The stress relieving layer 5 in each embodiment can be formed by printing using a printing metal mask or a dispenser.

Not only the printing method but also a method such as stamping, spraying using air or an inert gas, an ink-jet method, attaching an uncured or semi-cured resin sheet, or the like, may be used. It can be formed by combining them. When forming the stress relaxation layer by the printing method, the inclination of the end of the printed portion may be caused by the flow of the insulating layer at the end when the insulating material is printed and the print mask is removed, or during the heat curing process, and the slope of the end may be reduced. It is formed. According to this method, it is possible to collectively form a stress relaxation layer and an end portion having a specific inclination for each wafer. On the other hand, when a stress relaxation layer is formed by stamping, an insulating material for stress relaxation is applied to a stamping mold and the shape of the stress relaxation layer is transferred onto a wafer, so that the shape of the end portion changes when the insulating material is cured. This allows the selection of no insulating material. In this case, there is a feature that the shape of the end portion tends to be constant as compared with the printing method. Furthermore, in the method in which the insulating material is sprayed using a gas or the like, since a printing mask or a stamping die is not used, there is a degree of freedom in the shape at the time of forming the stress relaxation layer. It is possible to form a stress relaxation layer that is difficult to form with a mold. Further, compared to the printing method and the stamping method, the thickness of the stress relaxation layer can be adjusted by adjusting the spray amount, and the range of the thickness adjustment is widened. The method of attaching a semi-cured or uncured resin sheet allows the formation of a thick-film stress-relaxation layer and uses a sheet-like insulating resin in advance, and thus has a feature that the surface of the stress-relaxation layer is excellent in flatness. These methods can be used alone or in combination as appropriate to obtain the desired stress relaxation layer thickness and end inclination.

Next, another embodiment of the semiconductor device will be described. FIG.
9 is a schematic cross-sectional view showing a state in which the protruding electrodes of the semiconductor device are mounted on a substrate for converting the same, and FIG. It is a figure.

The protruding electrode 1 formed on the semiconductor device 13 is mounted on the corresponding electrode 120 on the substrate via a solder paste or a flux or the like, and the protruding electrode is melted by a reflow furnace or the like so that the substrate 115 and the semiconductor The connection of the device 13 is performed. The substrate on which the semiconductor device is mounted has electrodes 120 for mounting on substrates used for various electronic devices and, if necessary, protruding electrodes 12 on the back surface of the semiconductor element mounting surface.
One.

When the semiconductor device 13 is mounted on a substrate used for various electronic devices, it is necessary to heat and melt the protruding electrode 121 provided on the substrate 115. In order to further improve the reliability in these mounting processes and various tests, particularly the reliability results in a drop impact test, the semiconductor device 1
3 and the substrate 115 are reinforced with a resin 118.

As the resin 118 filling the space between the semiconductor device 13 and the substrate 115, a liquid epoxy resin, phenol resin, polyimide resin, silicone resin or the like used for general semiconductor encapsulation can be used. In order to adjust the coefficient of thermal expansion and elastic modulus of silica, alumina, particles of inorganic materials such as boron nitride, one or two or more kinds are blended, and if necessary, a resin such as silicone or thermoplastic resin, alkoxysilane or It is possible to compound a coupling agent such as titanate, a coloring agent, a flame retardant for imparting flame retardancy, a curing accelerator for accelerating the curing reaction of the flame retardant auxiliary resin layer, and the like.

In this embodiment, even when the pitch of the protruding electrodes on the semiconductor device is different from the pitch of the electrodes of the substrate used for various electronic devices, the electronic devices can be connected to various electronic devices via a predetermined substrate. It becomes possible to connect.

It is to be noted that, similarly to the case where the semiconductor device is mounted on a substrate to be a semiconductor device, the same applies to the case where the semiconductor device is mounted on a circuit board used for general electronic equipment.

In the embodiments described above, if necessary, for example, a low-elastic material is used for the insulating layer of the semiconductor device and an insulating layer having a thickness of 35 μm or more is formed. Can be prevented from being destroyed.
Further, the presence of the low-elasticity insulating layer makes it possible to greatly reduce the stress generated at the connection part. For this reason,
The connection life of the semiconductor device is greatly improved.

In the case where a thick insulating layer having a thickness of about 35 μm or more is employed, the conventional wiring forming method is difficult to apply. When the insulating layer is formed to have a large thickness, the material for forming the insulating layer has a high viscosity, so that the spin coating method results in an insulating layer containing air bubbles, and does not function as the insulating layer. Even if a new method for forming a thick film is developed separately, the light transmittance is reduced at a film thickness of 35 micrometers, so that the opening and the like of the insulating layer can be formed with high precision by exposure and development. Can not.
Even if this problem can be solved, the side wall of the opening of the insulating layer is approximately vertical of about 80 degrees or more, and the height is much larger than the wiring thickness, so that the metal wiring is formed on the side wall. It is hard to be done. Even if it can be formed, the bent portion of the metal wiring is formed at the boundary between the side wall and the upper layer, so that stress is easily concentrated at this location, and the crack is easily developed. For this reason, the connection life when connecting the circuit board is shortened.

Therefore, it is preferable to form a thick insulating layer by mask printing the insulating material containing fine particles as described above, and to make the shape of the opening of the insulating layer a gentle slope. As a result, the wiring on the insulating layer can be formed by the conventional method, and since there is no bent portion of the metal wiring where stress is concentrated, disconnection of the wiring hardly occurs.

[0109]

According to the present invention, it is possible to realize a semiconductor device capable of flip-chip connection that does not require underfill, and to suppress disconnection of its wiring.

[Brief description of the drawings]

FIG. 1 is a partial sectional view showing a structure of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a plan view showing a state where the semiconductor device of the present embodiment is formed continuously.

FIG. 3 is a diagram (1) showing an example of the manufacturing process of the semiconductor device of the present invention.

FIG. 4 is a diagram (2) showing an example of the manufacturing process of the semiconductor device of the present invention.

FIG. 5 is a diagram (3) showing an example of the manufacturing process of the semiconductor device of the present invention;

FIG. 6 is a view showing a printing mask used for forming a stress relaxation layer of the present invention.

FIG. 7 is a diagram showing a process of printing a stress relaxation layer.

FIG. 8 is a view showing a plate separation process in which a print mask is raised from a wafer.

FIG. 9 is a diagram showing a semiconductor device on which a stress relaxation layer is formed.

FIG. 10 is a diagram showing a state in which an exposure mask is closely attached to a resist.

FIG. 11 is a diagram showing an example of rewiring wiring;

FIG. 12 is a diagram showing another example of the rewiring wiring;

FIG. 13 is a diagram showing insufficient development of an actual wiring pattern for rewiring;

FIG. 14 is a diagram showing another example of the rewiring wiring;

FIG. 15 is a diagram showing another example of the wiring for rewiring.

FIG. 16 is a diagram showing another example of the rewiring wiring;

FIG. 17 is a view showing a semiconductor device which has gone through the seventh step in the present invention.

FIG. 18 is a diagram showing the relationship between the thickness of a stress relaxation layer and stress.

FIG. 19 is a diagram showing the relationship between the thickness of a stress relaxation layer and α rays.

FIG. 20 is a diagram showing one embodiment of the structure of the semiconductor device of the present invention;

FIG. 21 is a diagram showing an embodiment of the structure of the semiconductor device of the present invention.

FIG. 22 is a view showing one embodiment of the structure of the semiconductor device of the present invention;

FIG. 23 is a diagram showing one embodiment of the structure of the semiconductor device of the present invention.

FIG. 24 is a diagram showing a semiconductor device in which the thickness of a stress relaxation layer is partially reduced.

FIG. 25 is a diagram showing a state in which a semiconductor device in which the thickness of a stress relaxation layer is partially reduced is connected to a circuit board;

FIG. 26 is a diagram showing one embodiment of the structure of the semiconductor device of the present invention;

FIG. 27 illustrates a state in which a stress relaxation layer is formed across a boundary between a semiconductor device and an adjacent semiconductor device.

FIG. 28 is a view showing a method of cutting the stress relaxation layer.

FIG. 29 is a diagram of an embodiment in which a semiconductor device is mounted on a substrate.

FIG. 30 is a view of another embodiment in which a semiconductor device is mounted on a substrate.

FIG. 31 shows a conventional semiconductor device.

FIG. 32 shows a state in which a conventional semiconductor device is connected to a circuit board.

FIG. 33 is a diagram showing one embodiment of the structure of the semiconductor device of the present invention.

FIG. 34 is a view showing another embodiment of the structure of the semiconductor device of the present invention.

FIG. 35 is a view showing another embodiment of the structure of the semiconductor device of the present invention;

FIG. 36 is a view showing another embodiment of the structure of the semiconductor device of the present invention;

FIG. 37 is a diagram showing one embodiment of the structure of the semiconductor device of the present invention;

FIG. 38 is a view showing another embodiment of the structure of the semiconductor device of the present invention;

FIG. 39 is a view showing another embodiment of the structure of the semiconductor device of the present invention;

FIG. 40 is a view showing another embodiment of the structure of the semiconductor device of the present invention.

FIG. 41 is a diagram showing a relationship between a glass transition temperature and a linear expansion coefficient.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Bump, 1aa ... Vertical bump, 2 ... Au plating, 3
... Bump pad, 4 ... Rewiring wiring, 5 ... Stress relaxation layer,
6 ... surface protective film, 7 ... aluminum pad, 8 ... protective film, 9 ...
Semiconductor-formed wafer, 10 bump, 11 metal wiring, 12 insulating layer, 13 semiconductor device, 14 circuit board, 15 underfill, 16 power supply film, 17 reverse wiring pattern, 18 Connection portion between aluminum pad and wiring, 19: boundary between lower layer portion, 20: gap, 21: exposure mask, 22: resist, 23: connection portion with aluminum pad, 24: cut portion, 25: stencil made of nickel alloy,
26 ... resin sheet, 27 ... frame, 28 ... pattern opening of print mask, 102 ... silica particles, 110 ... memory cell, 115 ... substrate, 116 ... electrode, 118 ... resin, 12
0 ... electrode, 121 ... electrode

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kosuke Inoue 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. Production Technology Research Institute (72) Inventor Noriyuki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address: Within Hitachi, Ltd. Production Technology Research Laboratories (72) Inventor Hiroyuki Hozoji 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Within Hitachi Manufacturing Co., Ltd. 292 Machi-cho, Hitachi, Ltd.Production Technology Research Laboratories (72) Inventor Shigeharu Tsunoda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Ltd.Hitachi Manufacturing Technology Research Laboratory (72) Inventor Naoya Isada, Yokohama-shi, Kanagawa Prefecture 292 Yoshida-cho, Totsuka-ku, Hitachi, Ltd. Within Hitachi Semiconductor Co., Ltd. 5-2-1, Josuihoncho, Kodaira-shi, Tokyo (72) Inventor Asao Nishimura Within Hitachi Semiconductor Co., Ltd. 5-2-1, Josuihoncho, Kodaira-shi, Tokyo ( 72) Inventor Kenji Ujiie 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Hitachi, Ltd.Semiconductor Group (72) Inventor Akira Yajima 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Co., Ltd. Hitachi Semiconductor Group

Claims (12)

[Claims] A semiconductor element; an insulating layer formed on the semiconductor element; an external connection terminal formed on the insulating layer; and a semiconductor element formed on the insulating layer. Wherein the shape of the power supply wiring or the ground wiring is different from the shape of the signal wiring in the inclined portion of the insulating layer. Characteristic semiconductor device. 2. A wiring width of said power supply wiring or said ground wiring in said inclined portion is wider than a wiring width of said signal wiring in said inclined portion.
3. The semiconductor device according to claim 1. 3. The semiconductor according to claim 1, wherein an average wiring width of said power supply wiring or said ground wiring in said inclined portion is wider than an average wiring width of said signal wiring in said inclined portion. apparatus. 4. A semiconductor device, an insulating layer formed on the semiconductor device, an external connection terminal formed on the insulating layer, and a semiconductor device formed on the insulating layer. A semiconductor device having a circuit electrode and a wiring for electrically connecting the external connection terminal, wherein the width of the wiring is increased at an end of the insulating layer. 5. The semiconductor device according to claim 1, wherein the slope of the insulating layer has a slope of about 5% to about 30% with respect to the semiconductor element surface. 6. The semiconductor device according to claim 1, wherein said insulating layer has a thickness of about 35 to about 150 micrometers. 7. The semiconductor device according to claim 1, wherein said insulating layer is formed by printing using a mask. 8. The semiconductor device according to claim 1, wherein said insulating layer has particles. 9. The signal wiring according to claim 1, wherein the minimum wiring width of the signal wiring is about 25 μm when the thickness of the insulating layer is 60 μm to 80 μm. Semiconductor device. 10. The semiconductor device according to claim 1, wherein one end of said wiring also serves as a bump pad. 11. The wiring according to claim 1, wherein said wiring includes a wiring layer formed by nickel plating and copper plating.
Or the semiconductor device according to 4. 12. A semiconductor element, an insulating layer formed on the semiconductor element and having a thickness of 35 to 150 micrometers, an external connection terminal formed on the insulating layer, A semiconductor device having a nickel layer formed on a copper wiring, wherein the semiconductor device has a wiring formed thereon and electrically connecting the circuit electrode of the semiconductor element and the external connection terminal. A semiconductor device, comprising: