JP2002006790A - Circuit and method for processing digital display signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately perform asynchronous sampling to an input digital display signal. SOLUTION: A discriminant circuit 10 makes a comparison between undelayed sampling data obtained by sequentially latching the input digital display signal at the 1st edge of a PLL clock asynchronizing therewith and delayed sampling data obtained by sequentially latching at the 1st edge of an asynchronous clock by delaying the input digital display signal by a short period, and thereby discriminates whether both data coincide with each other. As a result of the discrimination by this discriminant circuit 10, a selection circuit 30 selects and outputs the sampling data obtained by sequentially latching the input digital display signal at the 1st edge of the PLL clock for the period that the undelayed data coincide with the delayed data, and selects and outputs the sampling data obtained by sequentially latching the input digital display signal at the 2nd edge of the PLL clock for the period that the data do not coincide with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a sampling process of an asynchronous clock for a digital display signal input to a liquid crystal display device or the like.

[0002]

2. Description of the Related Art With the rapid spread of digital still cameras (DSCs) and digital video cameras (DVCs), liquid crystal display devices (hereinafter, LCDs) for small audiovisual (AV) applications have been rapidly increasing as these monitors. ing. LCDs for such small AV applications are required to display very high-definition images while being small. Therefore, a so-called delta arrangement LCD panel in which the same colors of RGB pixels are arranged at a predetermined pitch from each other between adjacent rows is employed to enable high-definition video display. There are many.

[0003]

In the delta array panel, the number of pixels in the horizontal direction is strictly smaller than that in the stripe array in which pixels of the same color are arranged without being shifted from each other in the column direction. In particular, the DS described above
In a delta array panel used in LCDs for small AV applications such as C and DVC, various numbers of pixels smaller than the standard are often adopted in order to cope with miniaturization.

[0004] On the other hand, since the input video signal conforms to the standard, there may be a situation where the number of pixels of the actual panel is smaller than the number of horizontal pixels of the input video signal. In such a case, it is necessary to resample the input video signal in accordance with the number of pixels of the panel. Pixel display data is created from an input video signal according to the number of pixels.

Here, if the input video signal is an analog signal as in a conventional liquid crystal television, a view finder, etc., the analog I / F section operates with a clock having a frequency suitable for the actual number of pixels created by a PLL circuit or the like. May be used to resample the input analog video signal.

However, the monitor of the DSC or DVC is
The input video signal is a digital signal. When creating display data suitable for a delta array LCD panel from a digital video signal, in principle, digital data may be resampled at a frequency corresponding to the number of panel pixels. If the timing coincides with the change timing of the digital data, a sampling error occurs, and a problem occurs that normal display data cannot be created.

FIG. 4 shows a problem that occurs when such an input digital video signal is resampled based on a clock that is asynchronous with the input digital video signal. In FIG. 4, (b) shows an input digital video signal (8-bit data), and (a) shows an external input clock CLK.
Here, the frequency is four times the frequency of the master clock MCLK synchronized with the input digital video signal, and is used when generating a timing signal in the display signal processing circuit. FIG. 4C shows a PLL clock created by a PLL circuit.
It is asynchronous with the clock of the input video signal and has a frequency corresponding to the number of pixels in the horizontal direction of the LCD panel.

Using a PLL clock that is asynchronous with the input video signal and latching the input video signals sequentially supplied from A, for example, at each rising edge of the PLL clock, in the example of FIG. The rising timing of the PLL clock overlaps the switching timing of data D and data E. The change period of data D and E is shown in FIG.
As shown in (f), it is not known which of data D and E is latched. In addition, taking a video signal of a total of 8 bits as an example, as shown in an enlarged manner in FIG. 4D, each bit (Data [0] to [7]) has a slightly different data delay amount. Therefore, if the video signal is latched at the timing of FIG. 4E, erroneous data that does not match the data D or E will be latched. When such error data that does not match any data is written to the pixels of the display unit, display fluctuations and flickers occur in the corresponding pixels, which causes a reduction in display quality.

As a method of preventing such unstable sampling, the present applicant has proposed a resampling process using an external input clock synchronized with an input digital video signal without using an internal PLL clock. In this signal processing method, an input digital video signal is temporarily latched using, for example, an external input clock shown in FIG.
The obtained latch data is thinned out according to the number of panel pixels.

According to this method, it is possible to create display data according to the number of pixels. However, unlike the case where an analog input video signal is sampled by an internal clock, the display data created by the thinning process is pseudo. Is the data corresponding to the number of pixels. Also, if the clock of the input digital video signal is different, the resampling clock will also change, and in some cases, it may be necessary to change the thinning rules such as the thinning timing and the number of data thinning. It takes time.

In order to solve the above problems, the present invention provides:
Digital signal processing that can sample input digital data asynchronously with it, for example, for display devices, such as for accurately and reliably resampling the input digital video signal with a clock corresponding to the actual number of pixels of the display panel An object is to provide a suitable signal processing method and a signal processing circuit.

[0012]

To achieve the above object, the present invention has the following features.

The present invention is a signal processing circuit for sampling an input digital display signal by using a clock that is asynchronous with the clock of the signal. The signal processing circuit sequentially latches the input digital display signal at a first edge of the asynchronous clock. The obtained non-delayed sampling data is compared with the delayed sampling data obtained by delaying the input digital display signal for a short period and sequentially latching the first edge of the asynchronous clock to determine whether or not both data match. As a result of the determination by the determination circuit and the determination circuit, during the data coincidence period, the sampling data obtained by sequentially latching the input digital display signal at the first edge of the asynchronous clock is selected and output. During the data mismatch period, the input digital display signal is sequentially latched at the second edge of the asynchronous clock. Characterized in that it comprises a selection circuit for selectively outputting the sampling data obtained by.

According to the present invention, the digital display signal processing circuit further includes a sampling data generating circuit, and the discriminating circuit includes a delay circuit for delaying the input digital display signal for a short period, and an asynchronous clock. A first sampling circuit for sequentially latching the non-delayed input digital display signal at a first edge of the first clock signal; and a second sampling circuit for sequentially latching the delayed input digital display signal at a first edge of the asynchronous clock signal. A circuit that compares the non-delayed sampling data output from the first sampling circuit with the delayed sampling data output from the second sampling circuit. A sampling circuit for latching the non-delayed or delayed sampling data obtained by sequentially sampling at a second edge of the asynchronous clock at a first edge of the asynchronous clock; A fourth sampling circuit for sequentially latching the input digital display signal or the delayed input digital display signal at a second edge of the asynchronous clock; The sampling data is output from the sampling circuit, and the sampling data is output from the fourth sampling circuit during the data mismatch detection period.

Another feature of the present invention is a signal processing method for sampling an input digital display signal using a clock that is asynchronous with the clock of the signal, wherein the input digital display signal is sampled at a first edge of the asynchronous clock. The non-delayed sampling data obtained by sequentially latching and the delayed sampling data obtained by sequentially latching the input digital display signal at the first edge of the asynchronous clock by delaying the input digital display signal for a minute period are compared. Determining whether they match, and as a result of the determination, during the data matching period, at the first edge of the asynchronous clock, sequentially output the sampling data obtained by latching the input digital display signal, During the data mismatch period, the input digital display signal is obtained by sequentially latching the input digital display signal at the second edge of the asynchronous clock. Amplifier and to output the ring data.

With the signal processing circuit having the above configuration,
Further, by adopting the processing method as described above, the execution of each sampling and the determination of whether or not a sampling error occurs can be performed at low cost and with a small number of circuits by using a combination of, for example, a flip-flop, a gate circuit, and a multiplexer. It can be executed with the number of elements. Furthermore, if it is determined that a sampling error occurs, sampling is performed at a timing at which no error occurs, so that display data can always be obtained accurately.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention (hereinafter, embodiments) will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of a display device using a digital display signal processing circuit according to the present invention. This display device is a flat display device such as an LCD mounted on a digital camera such as a DSC or DVC as described above, and includes a panel 200, a digital display signal processing circuit 100, and a PLL circuit 150.

In this embodiment, the panel 200 is an LCD panel in which liquid crystal is sealed between a pair of substrates,
In particular, in a small active matrix type LCD panel suitable for DSC, DVC, etc., a plurality of R, G, B pixels are arranged in a delta in a display area.

The digital display signal processing circuit 100 generates analog display data according to the actual number of pixels on the LCD panel 200 from external R, G, B digital display signals, and also generates various necessary signals. The circuit includes a sample-and-hold circuit 110, a gamma correction, a brightness and contrast adjustment circuit 120, a digital / analog (D / A) conversion circuit (not shown), a polarity inversion and amplification circuit 130, a timing controller 140, and a counter electrode signal (common electrode signal). And a circuit 160 for generating.

The sample and hold circuit 110 has a digital I
/ F section, and has a configuration as shown in FIG. 2 to be described later, and samples digital display signals of R, G, and B supplied from the outside at a frequency corresponding to the number of pixels of the LCD panel 200. Of digital display data equal to the actual number of pixels of.

The adjustment circuit 120 adjusts R, G, and B digital data corresponding to the number of panel pixels obtained by sampling by the sample and hold circuit (digital I / F unit) 110 in accordance with the characteristics of the panel 200. Perform gamma correction, brightness adjustment, and contrast adjustment. The D / A conversion circuit converts the digital data adjusted by the adjustment circuit 120 into analog data, and converts the obtained analog data into a circuit 130.
, The polarity is inverted every horizontal scanning period, every vertical scanning period, and the like, is amplified to an amplitude suitable for display on the LCD panel 200, and is output to the LCD panel 200.

The PLL circuit 150 includes the LCD panel 200
Generates a clock PLLCLK having a frequency corresponding to the number of pixels in the horizontal direction.
0 is supplied to the sample and hold circuit 110.
Note that the PLL circuit generally includes a phase comparator, a loop filter, and a VCO. In the present embodiment, the phase comparator is provided in the timing controller 140. Therefore, a phase detection pulse obtained as a result of the phase comparison is supplied from the timing controller 140 to the PLL circuit 150.

The timing controller 140 has a master clock MC synchronized with an external input digital display signal.
LK, a horizontal synchronizing signal HD, and a vertical synchronizing signal VD are supplied. Based on these, timing control signals such as a polarity inversion signal FRP, a horizontal start pulse STH, a horizontal transfer clock CKH, a vertical start pulse STV, and a vertical transfer clock CKV are generated. And the circuit 130 and the panel 20
0 horizontal and vertical scanners. In addition, the above PL
The internal clock PLLCLK generated by the L circuit 150 is supplied to the sample and hold circuit 110.

The counter electrode signal generation circuit 160 generates a counter electrode signal (common electrode signal) COM, and transmits this to the T of the LCD panel.
The power is supplied to a common electrode formed on a substrate arranged opposite to the FT formation substrate.

In the display area of the LCD panel 200, R, G, and B pixels are arranged in a delta as described above, and each pixel has a thin film transistor (TF) as a switching element.
T) is provided, and the on / off of the TFT is controlled by a gate line extending in the row (horizontal scanning) direction of the panel. Further, R, G, B analog display data output from the amplifier 130 of the signal processing circuit 100 is supplied to a data line extending in the column (vertical scanning) direction of the panel, and from this data line to each pixel via a TFT. The display data is written, and display according to the display data is performed for each pixel.
In the periphery of the display area, a vertical scanner for sequentially driving gate lines and a horizontal scanner for selecting display of data lines at a predetermined timing and outputting display data to be written to pixels are formed. The vertical and horizontal scanners are not limited to a configuration formed as a built-in circuit on a panel substrate like TFTs in a display area, and may be formed as a part of a signal processing circuit 100 provided as an IC, or may be formed as an independent circuit. It may be constituted by a circuit.

Next, the configuration of the sample and hold circuit 110 and the asynchronous sampling operation of the input digital display signal in this circuit will be described with reference to FIGS.

In the following description, the externally input digital display signal is a QVGA (Quater Video Graphics Array) standard signal (320 horizontal pixels × RGB × 240 vertical).
The clock of this signal (master clock MCLK) is 6
MHz, whereas the LCD panel 20 in the delta arrangement
The actual number of pixels at 0 is, for example, horizontal 521 × vertical 21
8 or 557 horizontal × 234 vertical, and a case where the PLL clock PLLCLK corresponding to the actual number of pixels is 11 MHz will be described as an example.

FIG. 2 shows the configuration of the sample-and-hold circuit 110. The sample-and-hold circuit 110 is roughly divided into a determination circuit 10, a data creation circuit 20, and a selection circuit (multiplexer) 30 for switching the output.

The discrimination circuit 10 includes a delay circuit FF2 for delaying the input digital display signal for a short period based on the external input CLK, a first sampling circuit FF3, a second sampling circuit FF4, an exclusive OR (ExOR) gate, and an AND gate. The comparison circuit 12 includes a gate, and a flip-flop FF5 for adjusting a determination output timing that outputs a comparison result to the selection circuit 30 at a predetermined timing.

The data creation circuit 20 has a third sampling circuit FF6 and a fourth sampling circuit FF7, and the selection circuit 30 operates according to the data determination result output from the Q terminal of the FF5 of the determination circuit 10. , One of the Q output of the third sampling circuit FF6 and the Q output of the fourth sampling circuit FF7. The output side of the selection circuit 30 further includes an FF for adjusting output timing.
8 are provided.

Here, the PLL clock generated by the PLL circuit according to the actual number of pixels on the LCD panel 200 is supplied as a non-inverted clock to the first and second sampling FFs 3 and FF4. The third and fourth sampling circuits FF6 and FF7 and the timing adjustment FF5 are supplied as inverted clocks, respectively.

FIG. 3 shows an asynchronous sampling operation in such a sample and hold circuit 110.
In FIG. 3, (II) is a non-delay signal of R, G, B input digital video signals (8-bit data), and (III) is
FIG. 3 (I) is a delay signal obtained by delaying the R, G, B input digital video signals by the delay circuit FF2 of FIG.
This is an external input clock CLK having a frequency four times (24.54 MHz) the master clock MCLK synchronized with the input digital video signal. FIG. 3 (IV) shows the PLL
A PLL clock generated by the circuit 150, which is asynchronous with the clock of the input video signal and has a frequency (11 MHz) corresponding to the number of pixels in the horizontal direction of the LCD panel.

The first sampling circuit FF of the discrimination circuit 10
3 is connected to the D terminal of the FF1 existing at the previous stage of the
3 (II) is supplied to the first sampling circuit FF3 at the rising edge (first edge) of the PLL clock shown in FIG. 3 (IV) supplied to the CK terminal. ) Is latched and output (FIG. 3 (V)).

The delay circuit FF2 receives the input digital display signal output from the same FF1 as the first sampling circuit FF3 at the D terminal, and sequentially latches this display signal at the timing when the external clock of FIG. 3 (I) falls. As shown in FIG. 3 (III), the D terminal of the second sampling circuit FF4 receives the input display signal (non-delayed input display signal) input to the D terminal of the first sampling circuit FF3. On the other hand, the input digital display signal delayed by 0.5 clock of the external input clock (delayed input display signal)
Is supplied. Although the delay circuit is configured by a flip-flop in the example of FIG. 2, the delay circuit is not necessarily limited to the flip-flop as long as the signal can be delayed for a short period, and may be configured by a buffer, for example.
If a buffer is used as the delay circuit, it is not necessary to supply the external clock shown in FIG.
If the delay circuit is configured by the FF as in the present embodiment,
Although an external clock is required, the amount of delay can be less affected by variations in the circuit manufacturing process.

The second sampling circuit FF4 sequentially latches the input digital display signal output from the delay circuit FF2 and delayed by 0.5 clock at the rising edge (first edge) of the PLL clock supplied to the CK terminal and outputs the latched signal. (FIG. 3 (VI)).

Eight ExOR gates are provided here in accordance with the number of bits of the digital signal. Each gate has a first sampling circuit FF3.
3 (V) output from the second sampling circuit FF4 and the non-delayed sampling data shown in FIG.
The delay sampling data of (VI) is compared for each bit, and when the two data do not match, the L level is output, and when the two data match, the H level is output. The AND gate takes the logical product of the ExOR outputs provided for the bits, so that the H level output is output only when the non-delayed sampling data and the delayed sampling data match for all bits.
If the bits do not match, an L level output is generated (FIG. 3 (VII)).

For example, in FIG.
At the rise of the L clock, since the non-delayed input digital display signal of FIG.
The first sampling circuit FF3 can latch this data A. However, when the PLL clock rises at the next t2, the first sampling circuit FF3 overlaps with the transition period from data A to data B, so that accurate data can be latched. No, the sampling output becomes an error (indicated by xx in FIG. 3 (V)). In the first sampling circuit FF3, a similar sampling error occurs at timings t4 and t11.

On the other hand, in the second sampling circuit FF4,
At timing t2, since the delayed input digital display signal of FIG. 3 (III) is still data A, data A can be sampled. Similarly, at timing t11, an error occurs in the first sampling circuit FF3. In the second sampling circuit FF4, sampling is performed normally. At timing t4, a sampling error occurs as in the case of the first sampling circuit FF3, and at timings t6 and t13, the first sampling circuit FF3
Although sampling is performed normally, an error occurs in the second sampling circuit FF4.

Here, when a sampling error occurs in both the first and second sampling circuits, each data 8
Since the comparison is performed on the bits, it is extremely unlikely that the error data coincidentally coincides with all the bits in the comparison circuit 12. Therefore, the comparison result from the comparison circuit 12 becomes L level, for example, when a sampling error occurs in one or both of the first and second sampling circuits FF3 and FF4. Further, since the delay amount in the delay circuit is set to a predetermined minute amount, the result of sampling the non-delayed display signal by the PLL clock and the result of sampling the delayed display signal by the PLL clock are the first and the second. When both the sampling circuits FF3 and FF4 are performing normal sampling, they match, and the output from the comparison circuit 12 becomes H level (FIG. 3 (VII)).

Since the inverted PLL clock is supplied to the CK terminal of the FF 5 for timing adjustment, FIG.
As shown in (X), the comparison circuit 12 supplied to the D terminal
Are latched at the falling (second edge) timing of the PLL clock in FIG. 3 (IV), and supplied to the selection circuit 30 composed of a multiplexer. Therefore, the output selection operation of the selection circuit 30 is controlled in synchronization with the falling timing of the PLL clock (FIG. 3).
(XI)).

Next, the operation of the data creation circuit 20 will be described. The third sampling circuit FF6 has, at its D terminal, the non-delayed sampling data from the first sampling circuit FF3, that is, the rising edge of the PLL clock (the first rising edge of the PLL clock).
(Edge) input digital display signal. The CK terminal receives an inverted PLL clock, similarly to the fourth sampling circuit FF7 described below, and sequentially latches the non-delayed sampling data at the falling edge (second edge) of the PLL clock in FIG. 3 (IV). Output to the selection circuit 30 (FIG. 3 (VIII)). The third sampling circuit FF6 latches the non-delayed sampling data. However, since the delay amount in the delay circuit FF2 is very small as described above, the third sampling circuit FF6 latches the delayed sampling data, that is, the output of the second sampling circuit FF4. Is also good.

The fourth sampling circuit FF7 receives the non-delayed input digital display signal of FIG. 3 (II) at its D terminal, and receives the inverted PLL clock at its CK terminal. Therefore, at each falling edge (second edge) of the PLL clock, the non-delayed input digital display signal is latched and output to the selection circuit 30 (FIG. 3 (IX)). Further, here, the fourth sampling circuit FF7 also latches the non-delayed input digital display signal as in the third sampling circuit FF6, but latches the delayed input digital display signal (FIG. 3 (III)). Is also good.

The selection circuit 30 selects the sampling data from the third sampling circuit FF6 during the period in which the non-delayed sampling data and the delayed sampling data match all the bits and the H-level discrimination data is supplied, and adjusts the timing. To the FF 8 for use. In addition, the sampling data from the fourth sampling circuit FF7 is selected during the period in which the non-delayed sampling data and the delayed sampling data do not match even by one bit and the L-level determination data is supplied, and this is output to the timing adjustment FF8. I do. Since the FF terminal receives the PLL clock at the CK terminal, the FF 8 sequentially outputs sampling data from one of the third or fourth sampling circuits FF6 and FF7 as display data in synchronization with the PLL clock.

As described above, as a result of the discrimination by the discrimination circuit 10, the selection circuit 30 substantially obtains the data obtained by sampling the input digital display signal at the rising edge of the PLL clock during the data coincidence period. Is output as display data, and during the data mismatch period, data obtained by sampling the input digital display signal opposite to the match period at the falling edge of the PLL clock is output as display data. Therefore, for example, in the example of FIG.
PL at timings t2, t4, t6, t11 and t13
When it is detected that the latch of the input digital display signal (delayed or non-delayed) causes an error at the rising edge of the L clock, the data obtained by latching at the rising edge of the PLL clock during that period is replaced by 0. The data obtained by latching the input digital display signal at the falling edge of the PLL clock shifted by 5 clocks is output.

Here, the frequency of the clock of the input digital display signal (for example, 6 MHz) is sufficiently lower than the frequency of the PLL clock (for example, 11 MHz). The relationship is such that the data of the input digital display signal is determined. Therefore, if sampling error occurs at one timing of the PLL clock, accurate display data can be always obtained by asynchronously sampling the input digital signal by using data sampled at the other timing. It is.

Further, in the present embodiment, the discriminating circuit 10
In addition to detecting only the error of the non-delayed sampled data, the occurrence of the sampling error is determined using both the delayed sampled data sampled with a delay for a short period and the non-delayed sampled data. Therefore, even if a slight delay occurs due to data processing or the like in the sample and hold circuit 110 and the sampling timing is slightly shifted, a possible sampling error can be reliably prevented beforehand.

[0048]

As described above, according to the present invention, an accurate sampling can be performed on an input digital display signal by using an asynchronous clock.

Further, such accurate asynchronous sampling can be realized by a simple configuration having a small circuit scale, and it is possible to cope with a space saving and a power saving of a circuit required in a small display device or the like.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a display device according to the present invention.

FIG. 2 is a diagram showing a configuration of a sample and hold circuit 110 of FIG.

FIG. 3 is a timing chart illustrating the operation of the circuit of FIG. 2;

FIG. 4 is a diagram for explaining a problem of conventional input digital video signal processing.

[Explanation of symbols]

10 discrimination circuit, 20 data creation circuit, 30 selection circuit, 100 digital display signal processing circuit, 110 sample hold circuit, 120 γ correction, brightness and contrast adjustment circuit, 130 polarity inversion circuit and amplifier,
140 timing controller, 150 PLL circuit, 200 LCD panel.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) G09G 3/36 G09G 3/36 5C080 H04N 5/04 H04N 5/04 Z 5/66 5/66 C 102 102B 9/30 9/30 F term (reference) 2H093 NC21 NC23 NC26 ND37 ND39 ND42 5C006 AA16 AB01 AC21 AF46 AF47 AF72 BB11 BC12 BC16 BF11 FA16 FA43 5C020 AA01 AA35 CA20 5C058 AA06 BA04 BA12 BB19 BB21 5C060 BC01 A09 H09A DD22 EE21 EE29 FF12 GG07 JJ02 JJ04

Claims (3)

[Claims] 1. A signal processing circuit for sampling an input digital display signal using a clock that is asynchronous with a clock of the signal, the input digital display signal being a first signal of the asynchronous clock.
The non-delayed sampling data obtained by sequentially latching at the edge is compared with the delayed sampling data obtained by sequentially latching at the first edge of the asynchronous clock by delaying the input digital display signal for a short period of time. A discriminating circuit for discriminating whether or not they match each other; and as a result of discrimination by the discriminating circuit, during the data matching period, sampling data obtained by sequentially latching the input digital display signal at a first edge of the asynchronous clock. And a selection circuit for selecting and outputting sampling data obtained by sequentially latching the input digital display signal at the second edge of the asynchronous clock during the data mismatch period. A digital display signal processing circuit, characterized in that: 2. The digital display signal processing circuit according to claim 1, further comprising a sampling data generating circuit, wherein said discriminating circuit is a delay circuit for delaying said input digital display signal for a short period, and said asynchronous circuit. A first sampling circuit for sequentially latching the non-delayed input digital display signal at a first edge of a clock; and a second sampling circuit for sequentially latching the delayed input digital display signal at a first edge of the asynchronous clock. A sampling circuit, and a comparison circuit that compares whether the non-delayed sampling data output from the first sampling circuit and the delayed sampling data output from the second sampling circuit match each other, The sampling data generation circuit sequentially executes the second edge of the asynchronous clock at a second edge of the asynchronous clock. A third sampling circuit for latching the non-delayed or delayed sampled data obtained by sampling at a first edge of the asynchronous clock; and a second edge of the asynchronous clock, wherein the input digital display signal or the delayed input is sequentially output. A fourth sampling circuit for latching a digital display signal, wherein the selection circuit outputs sampling data from the third sampling circuit during the data coincidence period, and detects the data non-coincidence period during the fourth sampling period. A digital display signal processing circuit for outputting sampling data from the circuit. 3. A signal processing method for sampling an input digital display signal using a clock that is asynchronous with a clock of the signal, wherein the input digital display signal is sampled using a first clock of the asynchronous clock.
The non-delayed sampling data obtained by sequentially latching at the edge and the delayed sampling data obtained by sequentially latching at the first edge of the asynchronous clock by delaying the input digital display signal by a small period are compared. It is determined whether or not the data matches. As a result of the determination, during the data matching period, the sampling data obtained by sequentially latching the input digital display signal at the first edge of the asynchronous clock is output. And a step of sequentially latching the input digital display signal and outputting sampling data obtained at the second edge of the asynchronous clock during the data mismatch period.