JP2002094607A - Data transmission device and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a data transmission device which can change the timing of a transmission and in width the transmission and a reception can be changed over and used by one port, and to obtain its control method. SOLUTION: A microprocessor 1 is provided with an SI part and an SO part which transmit and receive data with reference to a transmission control unit LSI2 and an SCLK part which outputs a clock signal for synchronization when the data is transmitted from the SO part. The transmission control unit LSI2 is provided with a TX part and an RX part which transmit and receive data with reference to the microprocessor 1, an SCLK part which outputs a clock signal for synchronization when the data is transmitted from the RX part and an ILD part which controls whether the data from the SO part can be transmitted with reference to the microprocessor 1. In the transmission control part LSI2, whether the data from the SO part can be transmitted by the ILD part is controlled on the basis of transmission data from the microprocessor 1. The SO part, the SI part, the TX part and the RX part are constituted of one common port, and the input/output of the common port is changed over on the basis of the clock signal for synchronization by the SCLK part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device and a control method therefor, and more particularly to data transmission control between a microprocessor and a transmission control LSI.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram of a conventional data transmission apparatus, showing an interface between a microprocessor and a transmission control LSI. FIGS. 11A and 11B are time charts when a transmission and reception of a frame in a conventional data transmission device collide. FIG. 11A shows a case where the transmitting side of the frame wins, and FIG. 11B shows a case where the receiving side of the frame wins. . FIG. 12 is a diagram showing a time chart at the end of frame transmission / reception in a conventional data transmission apparatus,
The timing at which (described later) changes from “L” to “H” is shown, (a) at the end of frame transmission, and (b) at the end of frame reception.

In the figure, reference numeral 11 denotes a transmission control LSI, 12
Is a microprocessor, and 13 is a transmission line. In the transmission control LSI 11, DI is an input port for inputting a command transmitted from the microprocessor 12, RO is an output port for transferring a command to the microprocessor 12, SO is an output port for transmitting a frame to the transmission line 13, and SI is a transmission port. An input port for receiving a frame from the path 13 and an ILD is a no-signal detection port (Idle Line Detec
t), which is a port that goes “H” when there is no signal on the transmission line 13 for a 10-bit period.

Next, the operation will be described. First, FIG.
In (a), since the ILD is “H”, the microprocessor 12 stores the 8-bit data 1 (character 1) in the DI.
Send Even when a frame from the transmission line 13 is received by the SI simultaneously with the transmission of the 8-bit data 1, if the 8-bit data 1 transmitted by the microprocessor 12 is output from the RO, the microprocessor 12 determines that the transmission has been won. Then, 8-bit data 2 (character2) is transmitted.

In FIG. 11 (b), after the microprocessor 12 transmits 8-bit data 1, the
Since data different from the bit data 1 has been output, the microprocessor 12 determines that the transmission has been lost, and
Do not send bit data.

Further, in FIG. 12, at the time of transmission / reception of a frame, after 10 bits have passed from the end of the output of the RO, the IL
D is changed to "H", whereby the time from the transmission / reception of a frame to the permission of the next frame transmission is matched.

[0007]

In the conventional data transmission apparatus as described above, the timing when the ILD becomes "H" in a plurality of microprocessors is the same time after a lapse of 10 bit times from the end of the output of the RO. For this reason, the transmission timing from one microprocessor 12 overlaps with the transmission timing from another microprocessor 12, and there is a problem that the frequency of transmission collisions increases. In addition, the transmission control LSI 11 and the microprocessor 12 require two ports, a transmission port and a reception port, and the two ports cannot be used as a single port. there were.

The present invention has been made in order to solve the above-mentioned problems, and is characterized in that transmission timing can be changed, and that one port can be used by switching between a transmission port and a reception port. And a control method thereof.

[0009]

In the data transmission apparatus according to the present invention, the microprocessor has a first output port for transmitting data to a transmission control LSI, and a data output from the transmission control LSI. First to receive
And when transmitting data from the first output port, the synchronization clock signal is transmitted to the transmission control LSI.
A first synchronization clock output port for outputting to the
The transmission control LSI includes a second output port for transmitting data to the microprocessor, a second input port for receiving data transmitted from the microprocessor, and a case where data is transmitted from the first output port. A second synchronization clock output port that outputs a synchronization clock signal to the microprocessor, and a control port that controls whether the microprocessor can transmit data from the first output port, Transmission control LS
I controls whether or not data can be transmitted from the first output port by the control port based on data transmitted from the microprocessor.

The first output port and the first input port, and the second output port and the second input port are each constituted by one common port, and the first synchronization clock is provided. The input / output of the common port is switched based on the synchronization clock signal from the output port and the second synchronization clock output port.

Further, in the data transmission control method according to the present invention, the microprocessor has a first output port for transmitting data to the transmission control LSI and a second output port for receiving data transmitted from the transmission control LSI. And a first synchronization clock output port for outputting a synchronization clock signal to the transmission control LSI when data is transmitted from the first output port. The transmission control LSI includes: A second output port for transmitting data to the microprocessor, a second input port for receiving data transmitted from the microprocessor, and a clock signal for synchronization when transmitting data from the first output port. A second synchronization clock output port for outputting to the microprocessor; A control port for controlling whether data can be transmitted from a power port, and the transmission control LSI determines whether data can be transmitted from the first output port by the control port based on data transmitted from the microprocessor. To control.

The first output port and the first input port, and the second output port and the second input port are each configured by one common port, and the first output port and the second input port are configured by one common port.
And the input / output of the common port is switched based on the synchronization clock signal from the synchronization clock output port and the second synchronization clock output port.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram of a data transmission device according to a first embodiment of the present invention, showing a configuration of a transmission control line between a microprocessor and a transmission control LSI. FIG. 2 is a diagram showing a time chart when data output from a microprocessor to a transmission control LSI is output to a transmission line in this data transmission device, and FIG. 3 is a diagram showing a data transmission from the microprocessor to the transmission control LSI in this data transmission device. FIG. 4 is a diagram showing a time chart when data output is completed, and FIG. 4 is a diagram showing a format of a command transmitted between the microprocessor of the data transmission device and the transmission control LSI.

FIG. 5 is a time chart for changing an ILD control line in accordance with a transmission command from a microprocessor of the data transmission apparatus. FIG.
FIG. 7 is a diagram showing a time chart for transferring a frame received from a transmission line to a microprocessor in the data transmission device, and FIG. 8 is a diagram showing a time chart for transferring the frame received from the transmission line to the microprocessor. FIG. 6 is a state transition diagram of the ILD of the transmission control LSI 2 in the device.

In the figure, 1 is a microprocessor, 2
Denotes a transmission control LSI, 3 denotes a transmission path, and 4 denotes an amplifier. S
CLK is a data synchronization clock, and the side that outputs data outputs SCLK. For example, when the microprocessor 1 outputs data, the microprocessor 1 outputs SCLK, and when the transmission control LSI 2 outputs data, the transmission control LSI 2 outputs SCLK. The data output side outputs the data in synchronization with the fall of the clock. The side that takes in the data is SC
Data is taken in at the rise of LK.

SO is a serial output port of the microprocessor 1, SI is a serial input port of the microprocessor 1, TX is a serial input port of the transmission control LSI 2, RX is a serial output port of the transmission control LSI 2, I
LD is a terminal for controlling transmission and reception of the microprocessor 1, and P1 is an input port of the microprocessor 1 for a control signal from the ILD.

The first output port, the first input port, the first synchronization clock output port, the second output port, the second input port, the second synchronization clock output port, and the control port , SO, SI, SCLK, RX, TX of the microprocessor 1 and SCLK, ILD of the transmission control LSI 2, respectively.

Next, the operation of transmitting a frame to a transmission line will be described. First, the microprocessor 1 controls the transmission control LS
The operation of transferring a command to I2 will be described with reference to FIG. The microprocessor 1 uses P1 to output IL
After confirming that D is "L" (C1 in FIG. 2), S
CLK, and outputs a command from SO in synchronization with this. The transmission control LSI 2 captures the output command at the rise of SCLK from TX. After that, the transmission control LSI 2 transmits the frame to the amplifier 4,
After the frame is amplified by the amplifier 4, it is transmitted to the transmission path 3.

Next, the microprocessor 1 controls the transmission control L
FIG. 3 shows the operation of terminating the command transfer to SI2.
It will be described based on. The transmission control LSI 2 has a byte length counter (Length) as internal logic, and when the byte length counter becomes 0 (C2 in FIG. 3).
To set the ILD to "H". Then, the microprocessor 1 detects that the ILD has become “H”,
Is switched from the output side to the input side, and the command output from the SO is stopped. Further, when 20 ms elapses after transmitting the frame to the transmission path 3 (C3 in FIG. 3), the transmission control LSI 2
Set ILD to "L".

Here, a command sequence when the microprocessor 1 transfers data to the transmission control LSI 2 will be described. This command sequence is composed of a command, a byte length counter (Length) and data, as shown in FIG. The command is transmitted at a time interval of 20 ms after the transmission / reception of the frame (priority frame).
Transmit at an interval of 0 ms (general frame), 40
It specifies whether the transmission is to be performed at random time intervals after the ms time interval (random frame). The byte length counter (Length) describes the length of data following the byte length counter. The data is the content of the data to be transmitted. The byte length counter in FIG. 3 can be known from the value of the byte length counter.

Next, transmission of a priority frame, a general frame, and a random frame will be described with reference to FIG. First, as shown in FIG. 3, the transmission control LSI 2 sets the ILD to "H" upon completion of transmission or reception of the microprocessor 1, and then, after 20 ms elapses, sets the IL
D is set to “L” to transmit / receive a frame to / from the microprocessor 1. However, during the time period of 20 ms to 40 ms, a command other than the priority frame cannot be transmitted to the microprocessor 1. Therefore, if the command received during the time period of 20 ms to 40 ms is a general frame or a random frame, the transmission to the microprocessor 1 is temporarily stopped. There is a need.

Therefore, the transmission control LSI 2 determines the frame type using the first two bits of the command (for example,
“00” is a general frame, “01” is a random frame, “10” is a priority frame). In the case of a general frame or a random frame, the ILD is temporarily set to “H”.
(C4 in FIG. 5). Microprocessor 1 is IL
When D becomes "H", transmission is temporarily stopped.

Transmission control LSI that has received a command once
2, if the frame is a general frame, the ILD is set to "L" again after a lapse of 40 ms, and if the frame is a random frame, the ILD is set to "L" again at a time obtained by adding a random time to a time interval of 40 ms. " The microprocessor 1 reconfirms that the ILD has become “L”, and transmits a command sequence (after the command) to the transmission control LSI 2 again.

In the microprocessor 1, the ILD is "H".
, The direction of SCLK is switched to the receiving side within 1 ms. When the transmission control LSI 2 receives the frame from the transmission path 3, the transmission control LSI 2 sets the ILD to “H” and then sets the ILD to “H” for 5 ms.
After the elapse of the above, a clock is transmitted from SCLK, and a command string is transferred from RX to SI. Thereby, collision between SCLK and RX (SI) can be avoided.

Next, the operation of receiving a frame from a transmission line will be described with reference to FIG. First, the transmission control LSI 2
Indicates that the frame on the transmission line 3 is received (recognized) (FIG. 6)
In C5), the ILD is set to “H”, and after the frame recognition, the internal processing of the frame is performed for a period of 5 ms.
During this period, no command is transferred to the microprocessor 1. After a lapse of 5 ms, the command is transferred from the RX to the SI, and the microprocessor 1 receives the command from the SI.

Next, the operation of terminating the transfer of the received frame from the transmission path to the microprocessor 1 will be described with reference to FIG.
It will be described based on. The transmission control LSI 2 sets the ILD to "L" 20 ms after the byte length counter (Length) of the received frame becomes 0 (C6 in FIG. 7). Therefore, the microprocessor 1
Is changed to "L", SCLK is switched from the input side to the output side, and command reception by SI is stopped.

Here, the command sequence when the transmission control LSI 2 transfers a command to the microprocessor 1 has the same format as that of FIG.
ngth) and data. Further, since the ILD is always “H” until the reception of the frame is completed, the microprocessor 1 must always keep SCLK on the receiving side in accordance with this.

Next, the state transition of the ILD in the transmission control LSI 2 based on the transmission and reception of the frame with the transmission line 3 will be described with reference to FIG. First, when the data transmission device is reset, the ILD of S1 is set to "H". In this state, when the transmission control LSI 2 switches SCLK to input, the state transits to the state of S4, and command transfer from the microprocessor 1 becomes possible. When a command is transferred from the microprocessor 1, the transmission control LSI 2
Transmits a frame to the transmission path 3 and transitions to the state of S1 at the end of transmission. After 20 ms elapse after the frame transfer to the transmission path 3, the state transits to the state of S2 (ILD = "L").

When the command of the random frame is transmitted in the state of S2, the state transits to the state of S5 (ILD = “H”), and after the elapse of 20 ms + randomizing time from the state of S5, the state transits to the state of S4. Wait for command from. Further, when the transmission command of the general frame is transmitted in the state of S2, the state of S6 (ILD
= “H”), and after elapse of 20 ms, the state transits to the state of S3 and waits for a command of a general frame from the microprocessor 1. In each state, when a frame is received, the frame is reset, and the state transits to the state of S1,
After the transfer of the received frame on the transmission path 3 to the microprocessor 1, 20 ms elapses, and the state transits to S2.

Embodiment 2 FIG. In the first embodiment, the serial port is transmitted as viewed from the microprocessor 1 (SO)
Although the connection is made separately for the reception and the reception (SI), this may be used as a common port. FIG. 9 is a block diagram of a data transmission device according to a second embodiment of the present invention.
The same or corresponding parts as in the first embodiment are denoted by the same reference numerals. The microprocessor 1 is provided with a common serial port (SIO) for transmission and reception, and the transmission control LSI 2 is provided with a common serial port (TXRX) for transmission and reception.
The input / output of the SIO is switched in synchronization with the direction control of K. Thereby, a serial port can be realized by one port.

[0031]

Since the present invention is configured as described above, it has the following effects.

The microprocessor has a transmission control LSI
A first output port for transmitting data to the transmission control LS
A first input port for receiving data transmitted from I, and a first synchronization clock output port for outputting a synchronization clock signal to the transmission control LSI when transmitting data from the first output port. , Transmission control LSI,
A second output port for transmitting data to the microprocessor, a second input port for receiving data transmitted from the microprocessor, and a synchronization clock signal for transmitting data from the first output port to the microprocessor. A second synchronization clock output port for outputting data to the microprocessor and a control port for controlling whether or not the microprocessor can transmit data from the first output port. The control port controls whether the data can be transmitted from the first output port based on the command.
By changing the transmission timing, it is possible to output at different data transmission timings.

The first output port and the first input port, and the second output port and the second input port are each configured by one common port, and the first synchronization clock output port and the second Since the input / output of the common port is switched based on the synchronization clock signal from the synchronization clock output port, the number of ports used for transmission control can be reduced, and the number of signal lines can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data transmission device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a time chart when data output from a microprocessor to a transmission control LSI is output to a transmission line in the data transmission device according to the first embodiment of the present invention;

FIG. 3 is a diagram showing a time chart when the data output from the microprocessor to the transmission control LSI is ended in the data transmission device according to the first embodiment of the present invention;

FIG. 4 is a diagram showing a format of a command transmitted between a microprocessor and a transmission control LSI in the data transmission device according to the first embodiment of the present invention.

FIG. 5 shows a data transmission device according to the first embodiment of the present invention, which includes a microprocessor and a transmission control LSI;
ILD according to transmission command from microprocessor
It is a figure showing a time chart which changes a control line.

FIG. 6 is a diagram illustrating an example in which the data transmission apparatus according to the first embodiment of the present invention transmits a frame received from a transmission path to a transmission control LS.
FIG. 4 is a diagram showing a time chart for transferring data from I to a microprocessor.

FIG. 7 is a time chart when the transfer of the frame received from the transmission path to the microprocessor is completed in the data transmission device according to the first embodiment of the present invention;

FIG. 8 is a state transition diagram of the ILD of the transmission control LSI 2 in the data transmission device according to the first embodiment of the present invention.

FIG. 9 is a block diagram of a data transmission device according to a second embodiment of the present invention.

FIG. 10 is a block diagram of a conventional data transmission device.

FIG. 11 is a diagram showing a time chart when a frame collision occurs in the conventional data transmission apparatus.

FIG. 12 is a diagram showing a time chart at the end of a frame in a conventional data transmission device.

[Explanation of symbols]

1 microprocessor, 2 transmission control LSI, 3
Transmission path.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshiro Ito 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5K034 EE06 EE08 FF01 FF02 GG02 HH01 MM05 PP01 PP02

Claims (4)

[Claims] 1. A data transmission device comprising a microprocessor and a transmission control LSI for exchanging data between the two, wherein the microprocessor has: a first output port for transmitting data to the transmission control LSI; A first input port for receiving data transmitted from the transmission control LSI; and a first synchronization clock for outputting a synchronization clock signal to the transmission control LSI when transmitting data from the first output port. An output port, wherein the transmission control LSI has a second output port for transmitting data to the microprocessor, a second input port for receiving data transmitted from the microprocessor, and a first output. A second synchronization clock for outputting a synchronization clock signal to the microprocessor when transmitting data from the port. An output port; and a control port for controlling whether the microprocessor can transmit data from the first output port. The transmission control LSI is configured to control the control port based on data transmitted from the microprocessor. By the first
A data transmission device for controlling whether data transmission is possible from an output port of the data transmission device. 2. The first synchronizing clock, wherein the first output port and the first input port, and the second output port and the second input port are each configured by one common port. 2. The data transmission device according to claim 1, wherein input / output of a common port is switched based on a synchronization clock signal from an output port and the second synchronization clock output port. 3. A data transmission device comprising a microprocessor and a transmission control LSI for exchanging data between the two, wherein the microprocessor has a first output port for transmitting data to the transmission control LSI, A first input port for receiving data transmitted from the transmission control LSI; and a first synchronization clock for outputting a synchronization clock signal to the transmission control LSI when transmitting data from the first output port. An output port, wherein the transmission control LSI has a second output port for transmitting data to the microprocessor, a second input port for receiving data transmitted from the microprocessor, and a first output. A second synchronization clock for outputting a synchronization clock signal to the microprocessor when transmitting data from the port. An output port; and a control port for controlling whether the microprocessor can transmit data from the first output port. The transmission control LSI is configured to control the control port based on data transmitted from the microprocessor. By the first
A data transmission control method for controlling whether data transmission is possible from an output port. 4. The first synchronizing clock, wherein the first output port and the first input port, and the second output port and the second input port are each configured by one common port. 4. The data transmission control method according to claim 3, wherein input / output of a common port is switched based on a synchronization clock signal from an output port and the second synchronization clock output port.