JP2002083881A - Semiconductor device and production method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of contact by preventing short-circuiting caused by contacting the base of a recessed electrode and an adjacent pad. SOLUTION: This semiconductor device is provided with a pad 23 provided on a cell contact plug 9 under an interlayer dielectric 24 and a cylinder type lower storage capacitor electrode 26 as a recessed electrode, which has the base greater than that of the pad 23 and connects the relevant base to the pad 23. Then, a connection part 261 is formed from the base of the lower storage capacitor electrode 26 to one part on the pad 23 and between the remaining part on the pad 23 and the base of the lower storage capacitor electrode 26, a side wall 22 of a silicon oxide film is interposed as an insulating film for short-circuiting prevention.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for a semiconductor integrated circuit or the like, and more particularly, to a semiconductor device having a characteristic contact structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art At present, in semiconductor devices which have been highly miniaturized, particularly in dynamic random access memories (DRAMs), there is a margin for superposing a contact (bit contact, capacitance contact) in a memory cell on a gate electrode. There is known a memory cell in which a polysilicon pad is provided in order to increase the power consumption.

FIGS. 9 to 12 show, as a conventional example, a method of manufacturing a DRAM of the type in which a storage capacitor is formed below a bit line using a polysilicon pad.

First, an element isolation oxide film 2 and a gate electrode 4 are formed on a substrate 1, and an interlayer insulating film 7 such as a silicon oxide film (BPSG film) containing boron or phosphorus is deposited. Next, the interlayer insulating film 7 is flattened by a method such as chemical mechanical polishing (CMP). Subsequently, a cell contact hole 8 connected to the impurity diffusion layer 3 of the transistor of the memory cell is opened. The cell contact hole 8 can be opened in a self-aligned manner with respect to the gate electrode 4 by opening the silicon nitride films 5 and 6 provided on the upper surface and side surfaces of the gate electrode 4 as an etching stop layer. Further, polysilicon containing phosphorus or the like is deposited to form a cell contact plug 9. Next, a silicon oxide film is deposited and patterned to form a silicon oxide film 21 serving as a mask when processing a polysilicon pad. At this time, by forming the side wall 22 of the silicon oxide film on the side wall of the silicon oxide film 21, the interval between the adjacent polysilicon pads 23 can be made smaller than the lithography limit. [FIG. 9 (a)].

Subsequently, using the silicon oxide film 21 and the side walls 22 as a mask, the polysilicon is etched to form a polysilicon pad 23 [FIG.
(B)].

Then, the BP corresponding to the height of the lower electrode of the storage capacitor is obtained.
An interlayer insulating film 24 such as an SG film is deposited [FIG.
(C)].

Subsequently, a hole 25 for forming a cylindrical storage capacitor is formed [FIG. 10 (d)]. The etching of the hole 25 is performed until the polysilicon pad 23 is exposed.

Subsequently, a cylinder-type storage capacitor lower electrode 26 is formed thereon by depositing polysilicon containing phosphorus or the like and performing etch back [FIG. 11].
(E)].

Finally, a storage capacitor upper electrode 18, a bit contact 27, a metal wiring 20, etc. are formed to form a DRAM.
Is completed [FIG. 12 (f)].

[0010]

The above-mentioned prior art has the following problems.

Further, in the case where the storage capacitor portion is formed below the bit line as in the conventional example, when forming the hole for forming the cylinder-type storage capacitor portion, etching must be performed until the polysilicon pad is exposed. Therefore, the adjacent polysilicon pad for bit contact and the storage capacitor lower electrode are likely to be electrically short-circuited. Further, in order to secure a sufficient storage capacity, the hole needs to be as large as possible. However, when the size of the hole is increased, the possibility of a short circuit between the bit contact pad and the lower electrode of the storage capacitor is further increased.

[0012]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can improve the reliability of a contact.

[0013]

[Means for Solving the Problems]

A semiconductor device according to the present invention includes a pad provided on a lower layer of an interlayer insulating film, and a concave electrode having a bottom surface larger than the pad and having the bottom surface connected to the pad. is there. Then, a connection portion from the bottom surface of the concave electrode to a part on the pad is formed, and a short-circuit prevention insulating film is interposed between the remaining portion on the pad and the bottom surface. In other words, the present invention provides first and second pads provided adjacent to each other on a lower layer of an interlayer insulating film, a concave electrode connected to the first pad, and a connection to the second pad. In the semiconductor device provided with the contact plug, a short-circuit preventing insulating film for preventing a short circuit between the concave electrode and the second pad is provided around a connection portion between the concave electrode and the first pad. It is provided.

A large number of pads are provided on the same lower layer. Therefore, when the bottom surface of the concave electrode is in direct contact with the pad, the bottom surface of the concave electrode is larger than the pad, so that there is a possibility that the concave electrode may also contact an adjacent pad. Therefore, in the present invention, the bottom surface of the concave electrode is connected to a part of the pad through the connection portion, and the insulating film for preventing short circuit is inserted between the bottom surface of the concave electrode and the rest of the pad. The bottom surface of the electrode is sufficiently separated from the adjacent pad.

A first example of a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first mask made of a first insulator on a conductive film, and a step of forming a second mask on the entire side surface of the first mask. Forming a second mask made of an insulator, and forming the pad under the first and second masks by etching the conductive film using the first and second masks. Forming the interlayer insulating film on the first and second masks, opening holes reaching the first and second masks through the interlayer insulating film, Forming the short-circuit preventing insulating film made of the second mask by selectively removing only the first mask through the inner space of the space and the hole from which the first mask has been removed. The connection comprising a conductor And it is obtained by a step of forming the recessed electrode.

A second mask is formed on the entire side surface of the first mask, pads are formed below the first and second masks, and only the first mask is selectively removed. Thus, the short-circuit preventing insulating film can be easily formed by the second mask, and the connection portion can be easily formed in the space from which the first mask has been removed.

A second example of a method for manufacturing a semiconductor device according to the present invention includes a step of forming a first mask made of a first insulator on a conductive film, and a step of forming a second mask on the entire side surface of the first mask. Forming a second mask made of an insulator, and forming the pad under the first and second masks by etching the conductive film using the first and second masks. Forming an etching stop film on the first and second masks; forming the interlayer insulating film on the etching stop film; and forming the etching stop film through the interlayer insulating film. A step of opening a hole leading to the hole, a step of removing the etching stop film exposed in the hole to the first and second masks, and selectively removing only the first mask through the hole. Do Forming the short-circuit prevention film made of the second mask, and forming the connection portion and the concave electrode made of a conductor on the space from which the first mask is removed and on the inner wall surface of the hole. It is provided with.

The formation of holes is temporarily stopped by the etching stopper film on the first and second masks, and then the exposed etching stopper film is removed to form holes that accurately reach the first and second masks. it can.

[0020]

FIG. 1 is a schematic sectional view showing an embodiment of a semiconductor device according to the present invention. Hereinafter, description will be made based on this drawing.

The semiconductor device according to the present embodiment has an interlayer insulating film 2
4 pad 2 provided on cell contact plug 9 below
3 and a cylindrical storage capacitor lower electrode 26 having a bottom surface larger than the pad 23 and having a bottom surface connected to the pad 23 as a concave electrode.
Then, a connection portion 261 is formed from the bottom surface of the storage capacitor lower electrode 26 to a portion on the pad 23, and silicon as a short-circuit preventing insulating film is provided between the remaining portion on the pad 23 and the bottom surface of the storage capacitor lower electrode 26. An oxide film sidewall 22 is interposed.

A large number of pads 23 are provided on a plurality of cell contact plugs 9 in the same layer. Therefore, when the bottom surface of the storage capacitor lower electrode 26 is in direct contact with the pad 23, the bottom surface of the storage capacitor lower electrode 26 is larger than the pad 23, so that there is a possibility that the storage capacitor lower electrode 26 also contacts the adjacent pad 23. Therefore, in the present invention, the bottom surface of the storage capacitor lower electrode 26 is connected to a part of the pad 23 via the connection portion 261, and the sidewall 22 is formed between the bottom surface of the storage capacitor lower electrode 26 and the rest of the pad 23. By interposing,
The bottom surface of the storage capacitor lower electrode 26 is sufficiently separated from the adjacent pad 23.

2 to 4 are schematic sectional views showing a first example of a method for manufacturing the semiconductor device of FIG. Hereinafter, FIG.
4 through FIG.

This embodiment is characterized in that a contact for connecting a pad and a lower electrode of a storage capacitor is formed in a self-aligned manner in a DRAM of a type in which a storage capacitor is formed below a bit line.

First, as in the first embodiment, the substrate 1
An element isolation oxide film 2 and a gate electrode 4 are formed thereon, and a cell contact hole 8 connected to the impurity diffusion layer 3 of the transistor of the memory cell is opened. Further, after the cell contact plug 9 is formed, a silicon nitride film mask 28 for forming the polysilicon pad 23 is formed (FIG. 2A).

Subsequently, using the silicon nitride film mask 28 and the side wall 22 of the silicon oxide film as a mask, the polysilicon is etched to form a pad 23 (FIG. 2B).

Subsequently, an interlayer insulating film 24 made of a silicon oxide film such as a BPSG film is deposited [FIG. 3 (c)]. The thickness of the interlayer insulating film 24 is determined by a required storage capacity, and is deposited, for example, in a range of about 600 to 1200 nm.

Subsequently, a hole 25 for forming a cylindrical storage capacitor is formed in the interlayer insulating film 24. The etching of the hole 25 is stopped when the silicon nitride film mask 28 on the pad 23 is exposed [FIG.
(D)].

Subsequently, by selectively removing the silicon nitride film mask 28 exposed at the bottom of the hole 25, a contact hole can be opened in a self-aligned manner with the pad 23 [FIG. 4 (e)]. Silicon nitride mask 28
Is selectively removed by dipping in a heated phosphoric acid solution.

Subsequently, a cylinder-type storage capacitor lower electrode 26 is formed by depositing polysilicon containing phosphorus and performing etch back [FIG. 3 (f)].

Finally, a storage capacitor upper electrode 18, a bit contact plug 27 and a metal wiring 20 are formed, and a DRAM is formed.
Is completed [FIG. 1 (g)].

FIGS. 5 to 8 are schematic sectional views showing a second example of the method for manufacturing the semiconductor device of FIG. Hereinafter, FIG.
A description will be given based on FIGS.

This embodiment is characterized in that a contact for connecting a pad and a lower electrode of a storage capacitor is formed in a self-aligned manner in a DRAM of a type in which a storage capacitor is formed below a bit line. An etching stop film for etching a hole for forming a storage capacitor is provided on a pad.

First, as in the first example, an element isolation oxide film 2 and a gate electrode 4 are formed on a substrate 1 and a cell contact hole 8 connected to an impurity diffusion layer 3 of a transistor of a memory cell is opened. Then, a cell contact plug 9 is formed by embedding polysilicon containing phosphorus. Thereafter, a silicon oxide film mask 21 for forming a polysilicon pad 23 and a side wall 29 of a silicon nitride film are formed (FIG. 5A).

Subsequently, using the silicon oxide film mask 21 and the sidewalls 29 as a mask, the polysilicon is etched to form the pads 23 [FIG.
(B)].

Subsequently, after a silicon nitride film 30 serving as an etching stop film is deposited to a thickness of about 20 to 100 nm, the BPS
An interlayer insulating film 24 made of a silicon oxide film such as a G film is deposited [FIG. 6 (c)]. The thickness of the interlayer insulating film 24 is determined by a required storage capacity, and is deposited, for example, in a range of about 600 to 1200 nm.

Subsequently, a hole 25 for forming a cylindrical storage capacitor is formed in the interlayer insulating film 24 [FIG.
(D)]. The etching of the hole 25 is stopped once when the silicon nitride film 30 serving as an etching stop film is exposed. Further, the silicon nitride film 30 is etched until the silicon oxide film mask 21 used as a mask for forming the pad 23 is exposed.

Subsequently, by selectively removing the silicon oxide film mask 21 exposed at the bottom of the hole 25, a contact hole can be opened in a self-aligned manner with respect to the pad 23 [FIG. 7 (e)].

Subsequently, a cylinder-type storage capacitor lower electrode 26 is formed by depositing polysilicon containing phosphorus and performing etch back [FIG. 7 (f)].

Finally, the storage capacitor upper electrode 18, the bit contact plug 27, and the metal wiring 20 are formed, and the DRAM is formed.
Is completed [FIG. 8 (g)].

According to this embodiment, the etching of the hole for forming the lower electrode of the cylinder type storage capacitor is stopped once with a thin silicon nitride film layer, and then the contact with the polysilicon pad is formed in a self-aligned manner. Therefore, the reliability of electrical insulation between the bit contact pad and the storage capacitor lower electrode can be further improved.

[0042]

According to the semiconductor device of the present invention, the bottom surface of the concave electrode is connected to a part of the pad via the connecting portion, and the insulation for short-circuit prevention is provided between the bottom surface of the concave electrode and the rest of the pad. By inserting the film, the bottom surface of the concave electrode can be sufficiently separated from the adjacent pad. Therefore, a short circuit caused by contact between the bottom surface of the concave electrode and the adjacent pad can be prevented. Thereby, the reliability of the contact can be improved.

According to the method of manufacturing a semiconductor device of the present invention, the second mask is formed on the entire side surface of the first mask,
By forming a pad under the first and second masks and selectively removing only the first mask, a short-circuit preventing insulating film can be easily formed by the second mask,
The connection portion can be easily formed in the space from which the first mask has been removed. Therefore, the semiconductor device according to the present invention can be easily manufactured.

According to the method of manufacturing a semiconductor device of the present invention, the formation of holes is temporarily stopped at the etching stopper films on the first and second masks, and then the exposed etching stopper film is removed. Since the accuracy of the etching can be improved, holes can be formed to reach the first and second masks accurately.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing one embodiment of a semiconductor device according to the present invention.

FIG. 2 is a schematic cross-sectional view showing a first example of a method for manufacturing the semiconductor device of FIG. 1, and the process proceeds in the order of FIG. 2 (a) and FIG. 2 (b).

FIG. 3 is a schematic cross-sectional view showing a first example of a method for manufacturing the semiconductor device of FIG. 1, and the process proceeds in the order of FIG. 3 (c) and FIG. 3 (d).

FIG. 4 is a schematic cross-sectional view showing a first example of a method for manufacturing the semiconductor device of FIG. 1, and the process proceeds in the order of FIG. 4 (e) and FIG. 4 (f).

FIG. 5 is a schematic cross-sectional view showing a second example of a method for manufacturing the semiconductor device of FIG. 1, in which steps proceed in the order of FIGS. 5 (a) and 5 (b).

FIG. 6 is a schematic cross-sectional view showing a second example of the method for manufacturing the semiconductor device of FIG. 1, and the process proceeds in the order of FIG. 6 (c) and FIG. 6 (d).

FIG. 7 is a schematic cross-sectional view showing a second example of the method for manufacturing the semiconductor device of FIG. 1, and the process proceeds in the order of FIG. 7 (e) and FIG. 7 (f).

FIG. 8 is a schematic sectional view showing a second example of the method for manufacturing the semiconductor device of FIG. 1;

FIG. 9 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device in a conventional example, and the process proceeds in the order of FIGS. 9 (a) and 9 (b).

FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in a conventional example, and the process proceeds in the order of FIGS. 10 (c) and 10 (d).

FIG. 11 is a schematic sectional view illustrating a method for manufacturing a semiconductor device in a conventional example.

FIG. 12 is a schematic sectional view illustrating a method for manufacturing a semiconductor device in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Element isolation oxide film 3 Impurity diffusion layer 4 Gate electrode 5 Silicon nitride film on gate electrode 6 Silicon nitride film on gate electrode side wall 7 Interlayer insulating film (BPSG film) 8 Cell contact hole 9 Cell contact plug 18 Upper storage capacitance Electrode 19 Metal contact 20 Metal wiring 21 Silicon oxide film mask 22 Side wall of silicon oxide film 23 Polysilicon pad 24 Interlayer insulating film (BPSG film) 25 Hole for forming cylinder type storage capacitance part 26 Cylinder type storage capacitance lower electrode 261 Connection part 27 Bit contact plug 28 Silicon nitride film mask 29 Side wall of silicon nitride film 30 Etching stop film of silicon nitride film

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB01 BB04 CC01 DD02 DD04 DD09 DD71 DD72 DD75 EE09 GG16 HH14 HH20 5F033 HH04 HH07 JJ04 KK01 KK04 LL04 NN31 QQ08 QQ10 QQ19 QQ25 QQ28 VQ15 Q03 VOQ XX15 XX31 5F083 AD31 AD49 MA03 MA04 MA15 MA17 MA20 PR05 PR06 PR07 PR10 PR29 PR43 PR44 PR45 PR53 PR54 PR55

Claims (10)

[Claims] 1. A first and a second pad provided adjacent to each other on a lower layer of an interlayer insulating film, a concave electrode connected to the first pad, and a second electrode connected to the second pad. A semiconductor device including a contact plug, wherein around a connection portion between the concave electrode and the first pad,
A semiconductor device, comprising: a short-circuit preventing insulating film for preventing a short circuit between the concave electrode and the second pad. 2. The semiconductor device according to claim 1, further comprising an etching stop film between said first pad and said second pad. 3. The semiconductor device according to claim 1, wherein a bottom surface of said concave electrode is larger than said first pad. 4. The semiconductor device according to claim 1, wherein said interlayer insulating film and said short-circuit preventing insulating film are formed of different materials. 5. A semiconductor device comprising: a pad provided on a lower layer of an interlayer insulating film; and a concave electrode having a bottom surface larger than the pad and having the bottom surface connected to the pad. A method of manufacturing a semiconductor device, comprising: forming a connection part extending to an upper part thereof; and interposing a short-circuit prevention insulating film between the remaining part on the pad and the bottom surface. A step of forming a first mask made of a first insulator; a step of forming a second mask made of a second insulator over the entire side surface of the first mask; Forming the pad under the first and second masks by etching the conductive film using the mask; and forming the interlayer insulating film on the first and second masks. Through this interlayer insulating film Forming a hole reaching the first and second masks, and selectively removing only the first mask through the holes to form the short-circuit preventing insulating film made of the second mask. And a step of forming the connecting portion and the concave electrode made of a conductor on the space from which the first mask has been removed and on the inner wall surface of the hole. 6. A pad provided on a lower layer of an interlayer insulating film, and a concave electrode having a bottom surface larger than the pad and having the bottom surface connected to the pad. A method of manufacturing a semiconductor device, comprising: forming a connection part extending to an upper part thereof; and interposing a short-circuit prevention insulating film between the remaining part on the pad and the bottom surface. A step of forming a first mask made of a first insulator; a step of forming a second mask made of a second insulator over the entire side surface of the first mask; Forming the pad under the first and second masks by etching the conductive film using the mask, and forming an etching stop film on the first and second masks, On this etch stop film Forming the interlayer insulating film; opening a hole penetrating the interlayer insulating film to reach the etching stop film; forming the first and second masks on the etching stop film exposed in the hole; Removing the first mask only through the holes to form the short-circuit prevention film composed of the second mask; and removing the first mask. Forming the connecting portion and the concave electrode made of a conductor on the inner space of the hole and the inner wall surface of the hole. 7. The method according to claim 5, wherein said first insulator is silicon nitride, said second insulator is silicon oxide, and said interlayer insulating film is a silicon oxide film. . 8. The method according to claim 5, wherein said first insulator is silicon oxide, said second insulator is silicon oxide, and said interlayer insulating film is a silicon oxide film. . 9. The method according to claim 1, wherein the first insulator is silicon nitride, the second insulator is silicon oxide, the interlayer insulating film is made of a silicon nitride film, and the etching stop film is made of a silicon oxide film. A method for manufacturing a semiconductor device according to claim 6. 10. The first insulator is silicon oxide, the second insulator is silicon nitride, the interlayer insulating film comprises a silicon oxide film, and the etching stop film comprises a silicon nitride film. A method for manufacturing a semiconductor device according to claim 6.