JP2002071744A - Burn-in testing device and method, and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a test by one burn-in test using one kind of a burn-in board even with respect to a case performing the burn-in test of an IC requiring the arrangement of a plurality of pins. SOLUTION: A macroprogram for indicating the practice order of a plurality of test programs and the pin condition corresponding to a plurality of the test programs are stored in a memory 32. A CPU 31 reads the test programs from the memory 32 in the indicated order according to the macroprogram and also sets the pin condition to allow a pattern control part 2 to perform the test content thereof. The CPU 31 forms one file wherein respective test results are collected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention
A burn-in test device for testing at high or low temperature,
The present invention relates to a test method and a storage medium storing the test program.

[0002]

2. Description of the Related Art Conventionally, semiconductor integrated circuits (ICs) and LSIs (Laser Integrated Circuits) used in various electronic devices have been developed.
rge Scale Integrated-circuit) etc.
That. In (2), the functions of each element such as a resistor, a capacitor, and a transistor are realized by a circuit formed by printing, vapor deposition, or the like. However, there is some variation in characteristics between mass-produced products. For this reason, it is necessary to ensure the reliability of the IC by testing whether or not the characteristics of the IC satisfy the standard to determine whether or not the characteristics are satisfactory. IC is IC
Done by the test system.

As one form of this IC test system, I
There is a burn-in test system in which C is placed in a thermostat, and a power supply voltage or a test pattern signal is externally applied to an IC in the bath for testing.

In a burn-in test system, an IC
The temperature in the thermostat chamber containing the test sample is set constant, a test pattern is applied to the IC for a long time to apply stress, and an initial failure is detected. In addition, since the test time per IC is long, thousands to 10,000 ICs are accommodated in a thermostat, thereby reducing the test time per IC and increasing the efficiency.

In the thermostat, there is a board called a burn-in board on which the IC is mounted in order to externally apply a power supply voltage, a test pattern signal and the like to the IC. Hundreds of ICs can be mounted on a burn-in board, and several to several tens of burn-in boards can be accommodated in a thermostat.

In general, a test program is created for each type of IC because the applied voltage, test pattern, and pin conditions during the burn-in test vary depending on the type of IC. In addition, the test program is executed by dividing test items for each function in order to test each function of the IC.

[0007]

However, when performing a burn-in test on an IC, a test is performed for each function. However, pins used for the burn-in test may be different from pins required for a test for each function. in this case,
Two types of burn-in boards corresponding to each pin arrangement were used. Also, a test program for a burn-in test is prepared for each type of IC, and the test is performed in a plurality of steps. Therefore, a large amount of test time and cost has been generated.

An object of the present invention is to provide a burn-in test for an IC requiring a plurality of pin arrangements.
The purpose of the present invention is to enable a test to be performed in one burn-in test using various types of burn-in boards.

[0009]

Means for Solving the Problems In order to solve the above-mentioned problems, the invention according to the first aspect of the present invention is directed to a method in which I
In a burn-in test apparatus (for example, burn-in test apparatus 10 in FIG. 1) for executing a burn-in test on C, a plurality of test programs for executing the burn-in test and a plurality of ICs corresponding to the plurality of test programs are provided. A storage means (for example, the memory 32 in FIG. 1) for storing a pin condition and a macro program for designating the execution order of the plurality of test programs, and tests are sequentially performed from the storage means in accordance with the macro program read from the storage means. A control unit (for example, CPU 31 in FIG. 1) for reading a program and an IC pin condition corresponding to the program, and instructing a test execution unit on the test execution content based on the read test program and the IC pin condition in the order; The test execution unit (for example, FIG. Characterized in that it comprises a pattern control unit 2) and the.

According to the first aspect of the present invention, a plurality of tests having different pin conditions can be executed by one type of burn-in board in one burn-in test.
Therefore, it is not necessary to prepare a burn-in board set to the pin condition for each of the plurality of tests, and the cost and time required for the tests can be reduced.

According to a second aspect of the present invention, in the burn-in test apparatus according to the first aspect (for example, the burn-in test apparatus 10 of FIG. 1), the control unit controls the plurality of test execution results by the test execution unit. And generating a test execution result according to the macro program.

According to the second aspect of the present invention, the operator can obtain a test result by executing a plurality of tests having different pin conditions as one test result only by executing the macro program.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment will be described below in detail with reference to FIGS. First, the configuration will be described. FIG.
FIG. 1 is a block diagram showing a configuration of a burn-in test apparatus 10 to which the present invention is applied. In the figure, the burn-in test apparatus 10 includes a thermostat 1, a pattern control unit 2, and a control computer 3.

The thermostat 1 houses a plurality of burn-in boards 11 on which ICs for performing a burn-in test are mounted.

The pattern control section 2 includes a driver section 21, a comparator section 22, a pattern generation section 23, and a control section 24 for controlling these sections.

The pattern generator 23 generates a test pattern to be applied to an IC mounted on the burn-in board 11 in accordance with an instruction from the controller 24. The driver unit 21 applies a test pattern generated by the pattern generation unit 23 to an IC mounted on the burn-in board 11 based on a test program instructed by the control unit 24, and executes a burn-in test.

The control unit 24 controls the CP of the control computer 3
In accordance with the test program instructed by U31, the pattern generation unit 23 generates a test pattern and causes the driver unit 21 to execute a burn-in test based on the instructed test program. Then, a test result obtained by executing the burn-in test is output to the CPU 31.

The control computer 3 includes a CPU 31 and a memory 32. The memory 32 stores a macro program, I / O pin information for pin setting, and a test program for each type of IC.

FIG. 2 shows a macro program “XYZ00”
1. MIX "is a diagram showing a setting example. As shown in the figure, the macro program is a test program (ABC1) suitable for each type of IC mounted on the burn-in board 11.
23. DEV, DEF446. DEV etc.) are listed in the test execution order. Each of these test programs defines pin information, and when executing the test program, pin conditions are set according to the pin information.

The CPU 31 sequentially reads out the test programs from the memory 32 according to the macro program, and sets pin conditions at the time of executing the test program according to the defined pin information. Then, the pattern control unit 2
Instructs execution of the read test program. In addition, a result file storing test results obtained by executing the test program in the pattern control unit 2 is created.

Next, the operation will be described. The operation of the burn-in test apparatus 10 shown in FIG. 1 will be described based on a flowchart shown in FIG. Before starting the burn-in test,
It is assumed that a macro program (see FIG. 2) suitable for the IC to be tested is created in advance and stored in the memory 32.

When the burn-in board 11 on which a plurality of types of ICs are mounted is housed in the thermostat 1 and the burn-in test is started (step S1), the CPU 31 follows the macro program read from the memory 32 (step S2).
From the memory 32, the first test program “ABC12
3. "DEV" is read (step S4). At the same time, the CPU 31 sets pin conditions based on the I / O pin information “8I / O” (step S5), and executes the read test program “ABC123.DEV” by the control unit 24 of the pattern control unit 2. To instruct.

Test program "ABC123.DEV"
The control unit 24 instructed to execute the pattern generation unit 23
Then, a test pattern suitable for the type of IC to be tested is generated, and the driver unit 21 executes the test program “ABC123.DEV”.

Then, the control unit 24 transmits the test result obtained from the comparator unit 22 by executing the test program “ABC123.DEV” to the C
It outputs to PU31 (step S6).

Test program "ABC123.DEV"
CPU 31 having obtained the test result according to the second test program “DEF4” according to the macro program.
56. DEV ”is read from the memory 32, and thereafter, the pattern controller 2 is instructed to execute the same.

As described above, when all the other test programs listed in the macro program have been sequentially executed (step S3: NO), the CPU 31
Creates a result file that outputs test results obtained by executing the respective test programs (step S
7).

By configuring the burn-in test apparatus 10 as described above, a single burn-in test can test an IC having different pin conditions for screening and function tests. Further, since a burn-in test for a plurality of types of ICs can be performed with a single burn-in board, there is no need to prepare a plurality of burn-in boards, and costs and test time can be reduced.

Also, by defining the execution order and pin conditions of a plurality of test programs in a macro program, a plurality of tests having different pin conditions can be performed by an operator using only one test program (ie, a macro program). The program can be easily executed.

[0029]

According to the first, third or fifth aspect of the present invention, a plurality of tests having different pin conditions can be executed by one kind of burn-in board in one burn-in test. Therefore, there is no need to prepare a burn-in board set to the pin conditions for each of the multiple tests.
Test costs and time can be reduced.

According to the invention described in claim 2, 4, or 6, in addition to the effects of the invention described in claim 1, 3, or 5, the operator can execute a plurality of tests having different pin conditions only by executing the macro program. The test result by execution can be obtained as one test result.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a burn-in test apparatus to which the present invention is applied.

FIG. 2 is a diagram showing an example of a macro program.

FIG. 3 is a flowchart illustrating the operation of the burn-in test apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Burn-in test apparatus 1 Constant temperature chamber 11 Burn-in board 2 Pattern control part 21 Driver part 22 Comparator part 23 Pattern generation part 24 Control part 3 Control computer 31 CPU 32 Memory

Claims (6)

[Claims] 1. A burn-in test apparatus for executing a burn-in test on an IC housed in a thermostat, comprising: a plurality of test programs for executing the burn-in test; and a plurality of test programs corresponding to the plurality of test programs. Storage means for storing an IC pin condition and a macro program designating the execution order of the plurality of test programs; and IC pin conditions corresponding to the test program in order from the storage means in accordance with the macro program read from the storage means. And a control unit for instructing the test execution unit on the test execution contents based on the test program and the IC pin conditions read in the order, and the test execution for executing the test in accordance with the test execution contents instructed by the control unit A burn-in test apparatus, comprising: 2. The burn-in test apparatus according to claim 1, wherein the control unit collects the plurality of test execution results by the test execution unit and creates a test execution result according to the macro program. Burn-in test equipment. 3. A burn-in test method for executing a burn-in test on an IC housed in a thermostat, comprising: a plurality of test programs for executing the burn-in test; and a plurality of test programs corresponding to the plurality of test programs. A storage step of storing an IC pin condition and a macro program for designating the execution order of the plurality of test programs; and reading out the test program and the corresponding IC pin conditions in order according to the macro program. A burn-in test method, comprising: an instruction step of instructing test execution contents based on the test condition and an IC pin condition; and a test execution step of executing a test in accordance with the instructed test execution contents. 4. The burn-in test method according to claim 3, further comprising: a test result creating step of combining the plurality of test execution results in the test execution step to create a test execution result according to the macro program. A burn-in test method. 5. A storage medium storing a computer-executable program for executing a burn-in test on an IC housed in a constant temperature bath, wherein a plurality of test programs for executing the burn-in test are provided. A computer-executable program code for storing: a plurality of IC pin conditions corresponding to the plurality of test programs; and a macro program for designating an execution order of the plurality of test programs. A computer-executable program code for sequentially reading out the test program and the corresponding IC pin condition, and instructing the test execution contents based on the read out test program and the IC pin condition in this order; Computer run to execute test according to test execution content Storage medium characterized by storing a program code capability, the. 6. The storage medium according to claim 5, further comprising a computer-executable program code for compiling the plurality of test execution results and creating a test execution result according to the macro program. A storage medium characterized by the above-mentioned.