JP2002064162A - Semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip for absorbing stress caused by a difference in coefficient of thermal expansion with an outer board. SOLUTION: A second insulating layer 236 has a double layered structure made up of an insulating layer 236A with relatively low coefficient of thermal expansion and an insulating layer 236B with relatively high coefficient of thermal expansion. Since there is a difference in coefficient of thermal expansion, a heat is generated at the operation of the semiconductor chip 30, but each stress is absorbed by the insulating layers 236A and 236B with different coefficient of thermal expansion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip, and more particularly to a semiconductor chip that can be mounted on a substrate.

[0002]

2. Description of the Related Art FIG.
30 and its mounting form are shown. The nickel plating layer 3 is formed on the aluminum electrode pads 332 of the semiconductor chip 330.
The solder 344 for forming the bump 310 is provided via the gold plating layer 338 and the solder 34. Here, the semiconductor chip 330 is electrically connected to the electrode pad 352 on the package 350 side via the bump 310.

Incidentally, since the semiconductor chip 330 and the package 350 have different coefficients of thermal expansion, it is necessary to reduce the stress generated between the two. In the mounting form shown in FIG. An underfill 336 is provided between the package 330 and the package 350, and the two are fixed so that stress is not concentrated on the electrical connection, so that the electrical connection does not break. Have been.

[0004]

However, with the recent increase in the degree of integration of the semiconductor chip, the bumps of the semiconductor chip have been reduced in size, and the stress between the semiconductor chip 330 and the package 350 has been reduced by the above-described mounting mode. In some cases, the miniaturized electrical connection part is broken.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor chip capable of absorbing a stress generated by a difference in thermal expansion with an external substrate. is there.

[0006]

In order to achieve the above object, an object of the present invention is to provide an insulating layer formed on the surface on the electrode pad side and connecting the electrode pad formed on the insulating layer to an external substrate. And vias, wherein the insulating layer is made of two or more insulating films, the insulating film on the semiconductor chip side has a relatively low coefficient of thermal expansion, and the insulating film on the external substrate side has A technical feature is that the coefficient of thermal expansion is relatively high.

According to a second aspect of the present invention, the thermal expansion coefficient of the insulating film on the semiconductor chip side is larger than the intermediate value between the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the external substrate. It is a technical feature that the thermal expansion coefficient of the insulating film on the external substrate side is set to a value closer to the thermal expansion coefficient of the external substrate than the intermediate value.

A third aspect of the present invention is a semiconductor chip in which an insulating layer formed on the surface on the electrode pad side and a via formed on the insulating layer for connecting the electrode pad to an external substrate are formed. The technical feature is that the thermal expansion coefficient of the insulating layer is relatively low on the semiconductor chip side and relatively high on the external substrate side.

In the semiconductor chip of the first aspect, an insulating film having a relatively low coefficient of thermal expansion is provided on the semiconductor chip side, and an insulating film having a relatively high coefficient of thermal expansion is provided on the external substrate side. Since the two layers of insulating films having different coefficients of thermal expansion absorb the stress generated by the difference in thermal expansion between the semiconductor chip and the external substrate, the semiconductor chip can be firmly connected to the substrate.
The connection reliability of the semiconductor chip can be improved.

In the semiconductor chip of the second aspect, the coefficient of thermal expansion of the insulating film on the semiconductor chip side is closer to the coefficient of thermal expansion of the semiconductor chip than the intermediate value between the coefficient of thermal expansion of the semiconductor chip and the coefficient of thermal expansion of the external substrate. The thermal expansion coefficient of the insulating film on the external substrate side is set to a value closer to the thermal expansion coefficient of the external substrate than an intermediate value between the thermal expansion coefficients of the semiconductor chip and the external substrate.
Therefore, the stress generated by the difference in thermal expansion between the semiconductor chip and the external substrate can be absorbed by the respective insulating films, and the connection reliability of the semiconductor chip can be improved.

In the semiconductor chip of the third aspect, the coefficient of thermal expansion of the insulating layer is set to be relatively low on the semiconductor chip side and relatively high on the external substrate side. The stress generated by the expansion difference is absorbed, and the connection reliability of the semiconductor chip can be improved.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor chip and a method for manufacturing a semiconductor chip according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor chip according to a first embodiment of the present invention. On the lower surface of the semiconductor chip 30, an aluminum electrode pad 32 is formed in which an opening of the passivation film 34 is zincated. In the present embodiment, a first insulating layer 136 is provided on the lower surface of the passivation film 34, and the first insulating layer 136 has a non-through hole 136 a that extends in a tapered shape that reaches the aluminum electrode pad 32. I have. A nickel plating layer 38 and a composite plating layer 4 of nickel and copper are provided on the aluminum electrode pad 32 at the bottom of the non-through hole 136a.
A via 42 filled with copper plating is formed with 0 interposed.

On the first insulating layer 136, an insulating film 23 is formed.
Second insulating layer 236 having a two-layer structure of 6A and insulating film 236B
Are formed. In the second insulating layer 236, the thermal expansion coefficient of the insulating film 236A on the semiconductor chip side is set relatively low, and the thermal expansion coefficient of the insulating film 236B on the external substrate side is set relatively high. Specifically, the insulating film 236 on the semiconductor chip side
The coefficient of thermal expansion of the semiconductor chip (silicon wafer) 30
Value (9 ppm) between the coefficient of thermal expansion (3-4 ppm) of the substrate and the coefficient of thermal expansion (15 ppm) of the external substrate (epoxy substrate)
The thermal expansion coefficient is set to a value closer to the thermal expansion coefficient of the semiconductor chip (7 ppm), and the thermal expansion coefficient of the insulating film 236B on the external substrate side is set to a value (11 ppm) closer to the thermal expansion coefficient of the external substrate than the intermediate value. A copper plating post (via) 46 made of copper plating is formed on the second insulating layer 236, and a protruding conductor (bump) 54 made of a low melting point metal such as solder is provided on the copper plating post 46. Have been. The semiconductor chip 30 is connected to a pad 92 on the substrate 90 via a protruding conductor (bump) 54.

Here, the thickness of the second insulating layer 236 and
The height of the copper plating post 46 is formed in the range of 5 to 250 μm. On the other hand, the diameter of the copper plating post 46 is 20 μm or more.
It is formed to a thickness of 300 μm. Here, the semiconductor chip 3
0 and the substrate 90 have different coefficients of thermal expansion, and the heat generated during operation of the semiconductor chip 30 causes the semiconductor chip 30 and the substrate 9 to have different thermal expansion coefficients.
Although a stress is generated between the semiconductor chip 30 and the substrate 90, the stress is absorbed by the insulating films 236A and 236B having different coefficients of thermal expansion. It gives high connection reliability in between.

The thickness of the second insulating layer 236 is preferably 5 μm or more. This is because when the thickness is 5 μm or less, the stress cannot be sufficiently absorbed. On the other hand, the thickness is 250μ
m or less. This is because if the thickness is larger than 250 μm, the connection reliability between the semiconductor chip 30 and the substrate 90 is reduced.

Subsequently, a method of manufacturing the semiconductor chip 30 according to the present embodiment will be described with reference to FIGS. Here, copper plating posts and bumps are formed on the semiconductor chip 30 in which the aluminum electrode pads 32 are formed in the openings of the passivation film 34 shown in the step (A) of FIG. First, as shown in step (B) of FIG.
The zinc electrode treatment is performed on the aluminum electrode pad 32 by immersing it in a mixture of zinc oxide as a metal salt and sodium hydroxide as a reducing agent for 0 second. This facilitates the deposition of the nickel plating layer or the composite plating layer.

Subsequently, as shown in FIG. 2C, the semiconductor chip 30 is immersed in a nickel electroless plating solution to deposit a nickel plating layer 38 on the surface of the aluminum electrode pad 32. Note that, even if the step of forming the nickel plating layer is omitted, a composite plating layer described later can be directly formed on the aluminum electrode pad 32.

Then, as shown in step (D) of FIG.
The semiconductor chip 30 is immersed in a nickel-copper composite plating solution, and is placed on the nickel plating layer 38 by 0.01 to 5 μm.
The nickel-copper composite plating layer 40 is formed. By making this composite plating layer 1-60% by weight of nickel and the remainder mainly copper, in addition to being able to form the composite plating layer on the aluminum electrode pad, it is possible to easily form copper plating on the surface. To Further, by setting the thickness of the composite plating layer to 0.01 μm or more, it becomes possible to form copper plating on the surface. On the other hand, when the thickness is 5 μm or less, precipitation can be performed in a short time.

Next, as shown in FIG. 3E, an insulating resin is applied. In this embodiment, a thermosetting epoxy resin or a polyimide resin is used as the insulating resin in order to form a non-through hole by laser processing. When a non-through hole is formed by a chemical treatment, a photosensitive epoxy resin or a polyimide resin can be used.
Next, after performing a drying process as shown in the step (F) of FIG. 3, the first non-through holes 136a are formed by laser. Then, the aluminum electrode pad 32 is further heated.
A first insulating layer 136 having a non-through hole 136a reaching the first insulating layer 136 is formed.

Next, as shown in step (G) of FIG. 3, the first non-through hole 136a is filled with copper plating to form the via 42, and the re-wiring layer 46 is formed on the first insulating layer 136. To form These are formed by electroless plating.

Next, as shown in the step (H) of FIG. 3, a thermosetting epoxy resin or a polyimide resin to which silica filler is added is applied, followed by drying to perform insulation.
Form A. Here, about 75 vol% of the silica filler is mixed, so that the thermal expansion coefficient of the insulating film 236A is 7 ppm as described above. Then, as shown in step (I) of FIG. 4, a thermosetting epoxy resin or a polyimide resin to which silica filler is added is applied, and then a drying process is performed to form an insulating film 236B. Here, the thermal expansion coefficient of the insulating film 236A is set to 11 ppm as described above because the silica filler is mixed at about 67 vol%.

Subsequently, a non-through hole reaching the redistribution layer 46 is formed by laser as shown in the step (J) of FIG. 4, and the surface is roughened as shown in the step (K) of FIG. After that, the second insulating layer 236 having the second non-through holes 236a is formed by heating. In the present embodiment, since the non-through holes are formed by the laser, resins of various materials other than photosensitive can be used as the insulating layer.

Next, as shown in step (M) of FIG. 4, the semiconductor chip 30 is immersed in an electroless plating solution, and the second non-through hole 236a of the second insulating layer 236 is filled with copper. Then, a copper plating post 46 is formed.

Next, as shown in the step (N) of FIG. 5, after the surface of the second insulating layer 236 is uniformly subjected to electroless plating, pattern etching is performed except for the periphery of the copper plating post 46. A metal film 48 is added to the copper plating post.

Subsequently, as shown in step (O), after applying a resin to be a solder resist, an opening is formed on the metal film 46 by etching, and heating is performed to form a solder resist layer 52 having an opening 52a. .

Thereafter, as shown in step (P), the opening 5
After solder is printed in 2a, reflow is performed to form solder bumps 54. The height of the bump is 3 to 6
0 μm is desirable. The reason for this is that if the thickness is less than 3 μm, variations in the height of the bump cannot be tolerated due to the deformation of the bump. .

The bump 54 of the semiconductor chip 30 and the substrate 90
The semiconductor chip 30 is mounted so that the pads 92 correspond to the pads 92, and the semiconductor chip 30 is mounted on the substrate 90 as shown in FIG. 1 by reflow. In this embodiment, the insulating layer 136 is composed of two insulating films. However, three or more insulating films may be arranged with a gradient in the coefficient of thermal expansion. Further, in the structure shown in FIG. 1, the first insulating layer 136 and the insulating films 236A and 236B of the second insulating layer 236 can be set so that the coefficient of thermal expansion is inclined.

Next, a semiconductor chip and a method of manufacturing the semiconductor chip according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 shows a semiconductor chip according to a second embodiment of the present invention. In the first embodiment described above,
The second insulating layer 236 has a two-layer structure, and the coefficient of thermal expansion differs between the insulating film on the semiconductor chip side and the insulating film on the substrate side. On the other hand, in the second embodiment, the number of the second insulating layers 236 is one, but the coefficient of thermal expansion of the second insulating layers 236 is relatively low on the semiconductor chip side and relatively low on the external substrate side. Inclined to be high. Thereby, the stress generated by the difference in thermal expansion between the semiconductor chip and the external substrate is absorbed. Further, in the first embodiment, the via (copper plating post) 46 formed in the second insulating layer 236 is filled with copper, but the via 146 of the second embodiment has a resin 147 having elasticity inside. Is filled.

Next, a method of manufacturing the semiconductor chip 30 according to the second embodiment will be described with reference to FIG. First, a process of forming the first insulating layer 136, the via 42, and the redistribution layer 44 on the semiconductor chip 30 is the same as that of the first embodiment, and thus the description is omitted. As shown in step (A), a thermosetting epoxy resin or a polyimide resin to which silica filler is added is applied on the first insulating layer 136 of the semiconductor chip, and then left for 24 hours to settle the silica filler. Let it. Accordingly, as described above, the second insulating layer 236 is inclined such that the coefficient of thermal expansion is relatively low on the semiconductor chip side and relatively high on the external substrate side.

Next, as shown in step (B), a non-through hole reaching the redistribution layer 44 is formed by a laser, and after roughening the surface, the second non-through hole is heated. 236
A second insulating layer 236 having a is formed.

As shown in the step (C), the non-through holes 236a
A via 146 is formed therein by electroless copper plating, and the inside of the via 146 is filled with a filler of a thermosetting epoxy resin or a polyimide resin to which a copper filler is added. Thereafter, heating is performed to form an elastic resin 147 in the via 146. Dipping the semiconductor chip 30 in an electroless copper plating solution,
A lid plating 148 is formed in the opening of the via 146. Here, since the elastic resin 147 filled in the via 146 includes the copper filler as described above, the lid plating 148 is easily formed.
Can be formed.

In the step (D), bumps (protruding conductors) 54 are formed on the surface of the cover plating 148 as in the first embodiment. The height of the bump is preferably 3 to 60 μm. The reason is that if the thickness is less than 3 μm, variations in bump height cannot be tolerated due to deformation of the bump,
On the other hand, if it exceeds 60 μm, when the bump is melted, it spreads in the horizontal direction and causes a short circuit.

Next, a semiconductor chip and a method of manufacturing the semiconductor chip according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 8 shows a semiconductor chip according to a third embodiment of the present invention. First Embodiment, Second Embodiment
In the embodiment, the first insulating layer 36 and the second insulating layer 136 are formed. However, in the third embodiment, only one insulating layer 36 is formed. However, the insulating layer 36 is composed of three insulating films 36A, 36B and 36C having different coefficients of thermal expansion. In the first and second embodiments, the wiring is routed by the rewiring layer 44. In the third embodiment, the copper plating posts 246 are formed directly on the electrode pads 32.

In the third embodiment, of the three insulating films 36A, 36B, and 36C, the insulating film 36A on the semiconductor chip side has a relatively low coefficient of thermal expansion, and the intermediate insulating film 36B has a medium thermal expansion coefficient. The insulating film 36B on the external substrate side is set relatively high. Also, the insulating film 3 on the semiconductor chip side
The elastic modulus of 6A is set relatively high, the middle insulating film 36B is set low, and the insulating film 36B on the external substrate side is set relatively high. Thereby, the stress generated between the semiconductor chip 30 and the substrate 90 due to the heat generated during the operation of the semiconductor chip 30 is reduced by the insulating films 36A having different coefficients of thermal expansion and elasticity.
36B and 36C, respectively, to provide high connection reliability between the semiconductor chip 30 and the substrate 90.

Next, a method of manufacturing the semiconductor chip 30 according to the third embodiment will be described with reference to FIGS. As shown in step (A) of FIG. 9, a semiconductor chip is coated with a thermosetting epoxy resin or a polyimide resin to which silica filler has been added, and then dried to form an insulating film 3.
6A is formed. Here, by increasing the amount of the silica filler, the thermal expansion coefficient of the insulating film 36A is relatively reduced as described above.

As in the step (B), a thermosetting epoxy resin or a polyimide resin to which a silica filler and a Si rubber filler are added is applied to the semiconductor chip, followed by drying to form an insulating film 36B. Here, by adding a Si rubber-based filler to the silica filler, the coefficient of thermal expansion of the insulating film 36B is adjusted to a medium level and the elastic modulus is increased as described above.

As shown in the step (C), a thermosetting epoxy resin or a polyimide resin to which silica filler is added is applied, followed by drying to form an insulating film 36C. Here, by reducing the amount of silica filler, the thermal expansion coefficient of the insulating film 36C is relatively increased as described above.

Subsequently, as shown in a step (D) of FIG. 9, a non-through hole reaching the redistribution layer 46 is formed by a laser, the surface is roughened, and then the non-through hole 3 is heated.
An insulating layer 36 having 6a is formed.

Next, the surface of the aluminum electrode pad 32 is subjected to a zincate treatment for facilitating the deposition of a nickel plating layer or a composite plating layer of nickel and copper. The zincate treatment can be performed, for example, by immersing the semiconductor chip 30 in a mixed solution of zinc oxide as a metal salt and sodium hydroxide as a reducing agent at room temperature for 10 to 30 seconds.

Subsequently, as shown in a step (E) of FIG. 10, the semiconductor chip 30 is immersed in a nickel electroless plating solution to deposit a nickel plating layer 38 on the surface of the aluminum electrode pad 32. Note that, even if the step of forming the nickel plating layer is omitted, a composite plating layer described later can be directly formed on the aluminum electrode pad 32.

Then, as shown in step (F) of FIG. 10, the semiconductor chip 30 is immersed in a nickel-copper composite plating solution,
A μm nickel-copper composite plating layer 40 is formed.

Next, as shown in FIG. 3G, a copper plating post 246 is formed in the non-through hole 36a. This plating is performed by electroless plating.

Subsequently, in step (H) of FIG. 11, bumps (protruding conductors) are formed on the surfaces of the copper plating posts 246. The bump 154 may be formed by, for example, a method of screen printing a conductive paste using a metal mask having an opening at a predetermined position, a method of printing a solder paste that is a low-melting metal, a method of performing a solder plating, or a method of melting a solder paste. It can be formed by a method of immersion in the glass. Pb-Sn solder, Ag-Sn solder, indium solder, or the like can be used as the low melting point metal.

Finally, as shown in step (I), a resin is applied to the entire surface of the insulating layer 36 on the bump 154 side,
After drying, an adhesive layer 56 made of an uncured resin is formed.

The adhesive layer 56 is preferably made of an organic adhesive. As the organic adhesive, epoxy resin,
Polyimide resin, thermosetting polyphenolene ether (P
PE: Polyphenylene ether, a composite resin of an epoxy resin and a thermoplastic resin, a composite resin of an epoxy resin and a silicone resin, and at least one resin selected from BT resins.

As a method of applying the uncured resin as an organic adhesive, a curtain coater, a spin coater, a roll coater, a spray coat, a screen printing, or the like can be used. Further, the formation of the adhesive layer can also be performed by laminating an adhesive sheet. The thickness of the adhesive layer is 5-50μ
m is preferred. The adhesive layer is preferably pre-cured (pre-cured) for easy handling.

As shown in the step (J), the semiconductor chip 3
The semiconductor chip 30 and the substrate 90 are bonded by heating and pressing the substrate 90 and the substrate 90 using a hot press. Here, first, the bumps 154 of the semiconductor chip 30 are pressed with the substrate 90 by pressing.
The uncured adhesive (insulating resin) interposed between the pad 92 and the pad 92 is extruded to the periphery, and the bump 154 contacts the pad 92 to establish a connection between them. Further, the adhesive layer 56 is hardened by being heated at the same time as the pressurization, and strong bonding is performed between the semiconductor chip 30 and the substrate 90. In addition,
As the hot press, it is preferable to use a vacuum hot press. Thus, the attachment of the semiconductor chip 30 to the substrate 90 described above with reference to FIG. 8 is completed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.

FIG. 3 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.

FIG. 4 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.

FIG. 5 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.

FIG. 6 is a sectional view of a semiconductor chip according to a second embodiment of the present invention.

FIG. 7 is a manufacturing process diagram of the semiconductor chip according to the second embodiment.

FIG. 8 is a sectional view of a semiconductor chip according to a third embodiment.

FIG. 9 is a manufacturing process diagram of the semiconductor chip according to the third embodiment.

FIG. 10 is a manufacturing process diagram of the semiconductor chip according to the third embodiment.

FIG. 11 is a manufacturing process diagram of the semiconductor chip according to the third embodiment.

FIG. 12 is a cross-sectional view of a semiconductor chip according to the related art.

[Explanation of symbols]

 Reference Signs List 30 semiconductor chip 32 aluminum electrode pad 34 passivation film 36 insulating layer 36a non-through hole 36A, 36B, 36C insulating film 38 nickel plating layer 40 composite plating layer 42 via 44 redistribution layer 90 substrate 92 pad 236 insulating layer 236A, 236B insulating film

Claims (3)

[Claims] 1. A semiconductor chip comprising: an insulating layer formed on a surface on an electrode pad side; and a via formed on the insulating layer for connecting the electrode pad to an external substrate. A semiconductor chip, wherein the layer is formed of two or more insulating films, the insulating film on the semiconductor chip side has a relatively low coefficient of thermal expansion, and the insulating film on the external substrate has a relatively high coefficient of thermal expansion. 2. The method according to claim 1, wherein a coefficient of thermal expansion of the insulating film on the semiconductor chip side is set to a value closer to a coefficient of thermal expansion of the semiconductor chip than an intermediate value between a coefficient of thermal expansion of the semiconductor chip and a coefficient of thermal expansion of the external substrate. 2. The semiconductor chip according to claim 1, wherein the thermal expansion coefficient of the insulating film on the substrate side is set to a value closer to the thermal expansion coefficient of the external substrate than the intermediate value. 3. A semiconductor chip comprising: an insulating layer formed on a surface on an electrode pad side; and a via formed on the insulating layer for connecting the electrode pad to an external substrate. A semiconductor chip, wherein a coefficient of thermal expansion of a layer is relatively low on a semiconductor chip side and relatively high on an external substrate side.