JP2002044940A - Mos-switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS-switching circuit that realizes prevention of wrong continuity due to adverse effects of output voltage through gate-electrode parasitic capacity, inhibiting the increases in output resistance of a low-side output element having a MOS gate electrode. SOLUTION: A gate potential of the low-side output element 2 is shifted to negative side by an accumulated voltage of a capacitor 811, when the low-side output element 2 is turned off immediately, prior to the turning-on of a high-side output element 1. While the low-side output element 2 is being turned on, the control voltage on the low side is applied to the gate electrode of the low-side output element 2, after recovering attenuation of the control voltage at the side of a low side due to the accumulated voltage of the capacitor 811 by means of a buffer circuit 82. Thereby, deterioration of the output performance of the low-side output element 2 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a switching circuit using a transistor having a MOS gate electrode.

[0002]

2. Description of the Related Art MOS
A conventional technique of an output stage (drive circuit) of a synchronous rectification DC-DC step-down converter circuit constituted by transistors will be described. This output stage includes a high-side MOS transistor (high-side output element) and a low-side MOS transistor (low-side output element), and is connected between a high power supply line (positive power supply line) and a low power supply line (negative power supply line). Are connected in series to each other to form a MOS drive circuit.

[0003] Both MOS transistors are pulse-driven complementarily (so as not to be turned on at the same time), and a high-side MOS transistor is driven.
When the transistor is turned on, the connection point (output terminal) of both MOS transistors is applied to the load through the choke coil.
A voltage obtained by subtracting the voltage drop of the choke coil from the power supply voltage is supplied, and magnetic energy is accumulated in the choke coil. After a certain period of time, the high-side MOS transistor is turned off and the low-side MOS transistor is turned on. The coil releases the stored magnetic energy so as to maintain the current flowing through the choke coil. As a result, a DC voltage lower than the power supply voltage is formed.

As described above, in a drive circuit (output stage) for alternately turning on (complementarily operating) the high-side output element and the low-side output element connected in series to each other, if the low-side element is constituted by a MOS transistor, The rise of the drain potential (output terminal potential) of the low-side MOS transistor due to the turning on of the element raises the gate electrode of the low-side MOS transistor through the gate-drain capacitance Cgd of the low-side MOS transistor, thereby increasing the potential of the low-side MOS transistor. It is known to cause a problem of turning on (hereinafter, also referred to as a simultaneous on problem).

This simultaneous ON problem is caused by the low side MOS.
The higher the rate of increase in the drain voltage of the transistor (the higher the frequency of the voltage applied to the gate-drain capacitance), the more significant the impedance of the gate-drain capacitance Cgd becomes, which becomes more significant.

Further, the simultaneous ON problem is caused when the drive circuit applies a step voltage to a reactive load such as the choke coil 5, the choke coil 5 becomes transiently high impedance with respect to the rise of the input voltage. It gets even more serious.

As a countermeasure for the simultaneous ON problem, an input signal voltage is applied to the gate electrode of the low-side MOS transistor through a negative bias generator in which a Zener diode and a capacitor are connected in parallel, thereby turning off the low-side MOS transistor. Technology to shift the gate potential to the negative side at the time (gate potential negative bias technology)
Has been proposed.

However, in this method, when the low-side MOS transistor is turned on, the gate potential of the low-side MOS transistor is reduced by the voltage drop of the negative bias generator, and the MOS transistor is turned on.
There is a problem that the performance of the drive circuit, particularly the low-side output element, cannot be exhibited.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to prevent an erroneous conduction due to the influence of an output voltage through a gate electrode parasitic capacitance while suppressing an increase in output resistance of a low side output element having a MOS gate electrode. It is an object of the present invention to provide a MOS switching circuit that realizes the above.

[0010]

According to a first aspect of the present invention, there is provided a MOS switching circuit comprising a low side output element having a MOS gate electrode for connecting a negative power supply line and an output terminal, and an input high side input voltage. A high-side output element that is driven and connects the positive power supply line and the output end;
A MOS switching circuit comprising: a low-side output element driving circuit for causing the low-side output element to operate substantially in reverse to the high-side output element; wherein the low-side output element driving circuit includes a capacitor and a constant voltage drop element connected in parallel with each other. A negative bias generation unit having one end to which a low side input voltage having a phase substantially opposite to the high side input voltage is input, and a low side MOS transistor having a gate electrode connected to the other end of the negative bias generation unit. A buffer circuit for applying an output voltage having the same phase as the potential of the other end of the negative bias generator to the MOS gate electrode of the low-side output element; an anode electrode connected to a lower power supply connection end of the buffer circuit; Are connected to the negative power supply line, and the other end of the negative bias generator and the And it connects the lower power supply connection end Ffa circuit is characterized in that it comprises a voltage dropping element for generating a predetermined voltage drop.

The low-side output element is not limited to a MOS field-effect transistor (MOSFET) as long as it is a three-terminal switching element having a MOS gate electrode. For example, a MOSSIT, IGBT, or the like may be used. The high-side output element may be any three-terminal switching element.

In the low-side output element driving circuit, the MOS transistor to which the control voltage is input from the negative bias generator is a normal MOS field-effect transistor (MO) if it is a three-terminal switching element having a MOS gate electrode.
SFET), for example, MOSSIT
Or IGBT. Any other three-terminal switching element of the low-side output element driving circuit may be used. The low-side output element drive circuit typically includes a first-stage inverter circuit having the MOS transistor as a low-side element, and an output-stage inverter circuit for inverting the output voltage of the first-stage inverter circuit.

The constant voltage drop element of the negative bias generating section is typically constituted by a Zener diode whose cathode electrode is connected to the gate electrode of the MOS transistor of the low side output element drive circuit. The output element driving circuit includes a predetermined number of charging diodes whose cathodes are on the MOS transistor side, and preferably one discharging diode connected in anti-parallel to these charging diodes.

The voltage drop element is typically composed of a resistance element, but a resistance element and a diode may be connected in series. The cathode electrode of this diode is connected to the gate electrode of the MOS transistor of the low-side output element driving circuit, so that current can flow into the capacitor from the lower power supply connection end of the low-side output element driving circuit.

A parallel connection circuit of a resistor and a diode may be provided between the output terminal of the buffer circuit and the gate electrode of the low-side output element, and the anode electrode of this diode is connected to the gate electrode side of the low-side output element. .

The gate electrode of the low-side output element and the negative power supply line may be connected by a bias resistor. In this case, the bias resistor is connected to the negative power supply line through a diode for preventing current from flowing from the negative power supply line. Is preferably connected to

The high-side control voltage applied to the high-side output element and the low-side control voltage or M of the low-side output element input to the low-side output element drive circuit
The control voltage input to the OS gate electrode is reversed in phase, but a dead time of a predetermined time (a period during which both control voltages are low) is provided between the high-side control voltage and the low-side control voltage. However, it is suitable for preventing DC current from leaking between the positive and negative power supply lines through the high-side output element and the low-side output element.

According to the present invention, the gate potential of the low-side output element can be shifted to the negative side by the storage voltage of the capacitor when the low-side output element is turned off immediately before the high-side output element is turned on.
At the time of turn-on of the low-side output element, since the attenuation of the low-side control voltage due to the storage voltage of the capacitor is recovered by the buffer circuit and then applied to the gate electrode of the low-side output element, a decrease in the output performance of the low-side output element is suppressed. A MOS switching circuit having low loss, excellent current driving capability, and excellent reliability can be realized.

According to a second aspect of the present invention, in the MOS switching circuit according to the first aspect, a DC-DC step-down converter is further configured with a choke coil provided between the output terminal and an external low-voltage load. Since the DC high-voltage power supply is connected between the positive and negative power supply lines, a DC-DC step-down converter with high performance and excellent reliability can be realized.

According to a third aspect of the present invention, the MOS switching circuit according to the first aspect further comprises a DC-DC boost converter together with a choke coil provided between the output terminal and an external low-voltage DC power supply. Since the DC high-voltage load is connected between the positive and negative power supply lines, a DC-DC boost converter with high performance and excellent reliability can be realized.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the following examples.

[0022]

Embodiment 1 A DC-DC step-down converter to which a complementary synchronous drive circuit of the present invention is applied will be described below with reference to the circuit diagram shown in FIG.

(Circuit configuration) 1 is a high side MOS transistor, 2 is a low side MOS transistor, and a high power supply line (positive power supply line, here 42V) 3 and a low power supply line 4 (negative power supply line, here 0V) ) Are connected in series with each other to form a MOS drive circuit.

Reference numeral 5 denotes a choke coil, and reference numeral 6 denotes a load. An output terminal X of the MOS drive circuit comprising a connection point between the transistors 1 and 2 supplies power to the load 6 through the choke coil 5.

Reference numeral 7 denotes a gate potential regulating circuit of the high-side MOS transistor 1 which is constituted by an NMOS transistor and operates as a source follower, and comprises resistors R1 and R2 and a diode D1. The resistors R1 and R2 are resistance voltage dividing circuits that connect the high-side input terminal Y and the output terminal X.

The chopping input signal voltage Vin1 applied between the high-side input terminal Y and the output terminal X is divided by this resistance voltage dividing circuit, and the gate electrode / source of the high-side MOS transistor 1 is divided. Applied between the electrodes. The diode D1 is used to rapidly lower the gate potential when the high-side MOS transistor 1 is turned off to speed up the turn-off of the high-side MOS transistor 1. This gate potential regulating circuit is used in the present invention. It is not an essential component.

Reference numeral 8 denotes a gate potential negative level shift circuit (low-side output element driving circuit), which constitutes this DC-DC step-down converter together with the MOS drive circuit (output stage), choke coil 5, and gate potential regulating circuit 7. are doing.

The gate potential negative level shift circuit 8 which is a feature of this embodiment will be described in more detail.

This gate potential negative level shift circuit 8
It comprises a low level potential lowering circuit (negative bias generator) 81, a buffer circuit 82, a gate potential regulating circuit 83, diodes 84 and 85, and a resistor 86.

The low-level potential lowering circuit 81 includes a capacitor 811 and a Zener diode 812. The capacitor 811 and the Zener diode 812 are connected in parallel to form a transistor 82 of a buffer circuit 82 described later.
1 between the first gate electrode and the low-side input terminal Z.

The buffer circuit 82 is constituted by a two-stage CMOS inverter circuit, and its high-level power supply connection terminal M
Is supplied from the control power supply line C (12 V), and the lower power supply connection end L described above is connected to the lower power supply line 4 through a diode 84.

The preceding stage of the buffer circuit 82 is formed by connecting a transistor 821 as a low-side element, a transistor 822 as a high-side element, and a resistor 823 interposed between them in series. It is connected to the low side input terminal Z. The output stage of the buffer circuit 82 includes a transistor 824 as a low-side element and a transistor 825 as a high-side element connected in series. The operation and function of the buffer circuit 82 composed of a two-stage CMOS inverter circuit are well known and will not be described. Gate potential regulating circuit 83
The configuration and operation of the high-side output element 1
Since it is the same as that of the gate potential regulating circuit 7, the description is omitted. However, it is important to note that the lower power supply connection end L of the buffer circuit 82 and the lower power supply end M of the gate potential regulating circuit 83 are individually connected to the lower power supply line 4 through the diodes 84 and 85. Potential (0 V).

A resistor (potential drop element) 86 connects the lower end L of the buffer circuit 82 to a gate electrode of a transistor 821 of the buffer circuit 82 described later.

(Description of Operation) The operation of this circuit will be described below. FIG. 2 shows a change in the potential of each part of the circuit of FIG. 1, and FIG. 3 shows a change in the gate potential G1 of the high-side MOS transistor 1 and the gate potential G2 of the low-side MOS transistor 2 when the high-side MOS transistor 1 is turned on. Show.

High-side input terminal Y and high-side MO
Between the source electrode (= output terminal X) of the S transistor 1 and the first clock voltage Vin1 which is a high-side control voltage
Is applied, and a second clock voltage Vin, which is a low-side control voltage, is applied between the low-side input terminal Z and the lower power supply line 4.
2 is applied. Although the first clock voltage Vin1 and the second clock voltage Vin2 are in anti-phase relationship, a dead time of a predetermined time (both voltages are low level) is provided and M
Simultaneous conduction during transition of the OS transistors 1 and 2 is regulated.

When the first clock voltage Vin1 goes to a low level, the source electrode potential of the transistor 1 that operates as a source follower decreases accordingly.

After the dead time, the second clock voltage Vin2
Becomes high level, the transistor 822 is turned off. At the same time, the capacitor 81
1, a current flows through the resistor 86 and the diode 84, a voltage Vgs between the gate electrode and the source electrode equal to the voltage drop of the resistor 86 is formed, and the transistor 821 is turned on. At the same time, the capacitor 811 is charged in the breakdown voltage range of the Zener diode 812. Is done.

Then, the output stage of the buffer circuit 82 including the transistors 824 and 825 outputs a high level,
The transistor 2 is turned on to set the output terminal X to low level.

Next, after a predetermined time, the second clock voltage Vin
When 2 goes low, the transistor 822 turns on. At the same time, the potential of the low-side input terminal Z becomes low level, so that the gate electrode potential of the transistor 821 further decreases by the amount of the storage voltage of the capacitor 811 and becomes negative potential. At this time, the lower potential terminal L of the buffer circuit 82
Also, the potential becomes a negative potential through the resistor 86 in conjunction with the decrease in the gate electrode potential of the transistor 821. The diode 84 prevents power supply from the lower power supply line 4 to the lower potential terminal L. Of course, since the transistor 821 is turned off, the output stage of the buffer circuit 82 including the transistors 824 and 825 is
The negative potential at the lower potential terminal L is output to the gate electrode of the MOS transistor 2, the gate electrode of the MOS transistor 2 becomes negative potential, and the MOS transistor 2 is turned off. The diode 85 prevents power supply from the lower power supply line 4 to the gate electrode of the MOS transistor 2.

After the dead time, the first clock voltage Vin
When 1 goes high, the source electrode potential of the transistor 1 rises following the gate potential, and the potential of the output terminal X goes high. At this time, the gate electrode potential of the MOS transistor 2 is electrostatically pulled up through the gate-drain capacitance Cgd of the MOS transistor 2 due to the rapid rise of the drain electrode potential of the MOS transistor 2. Since it is pulled down, it is possible to prevent the MOS transistor 2 from being turned on.

That is, the gate potential negative level shift circuit 8 pulls down the gate potential (low level) when the transistor 2 is turned off to the negative side without lowering the gate potential (high level) when the transistor 2 is turned on. Without affecting the output characteristics (especially the discharge characteristics) of the MOS drive circuit.
The output potential tracking turn-on of the transistor can be prevented.

(Modification) The buffer circuit 82 can recover (increase) the high-level potential output to the transistor 2 even if the high-level potential input to the gate electrode of the transistor 821 decreases due to the storage voltage of the capacitor 821. Any amplifier circuit may be used.

The buffer circuit 82 and the diode 84
Is provided, the second clock voltage Vin2 input to the low-side input terminal Z is applied to the gate electrode of the low-side MOS transistor 2 through the low-level potential lowering circuit 81 directly. The current driving capability can be greatly improved.

The gate potential regulating circuit 83 including the resistors R1 and R2 and the diode D1 can be omitted.
Only may be omitted. In these cases, diode 85
Can also be omitted. The resistor 823 can also be omitted.

Each transistor other than the transistor 2 can employ various three-terminal switching elements. However, the transistor 821 is preferably a transistor having a MOS gate electrode.
It should be a transistor with an OS gate electrode.

[0046]

Embodiment 2 In FIG. 1, a DC power supply is used in which the load 6 is changed to a power supply and a load is connected between the higher power supply line 3 and the lower power supply line 4.
Also in the -DC boost converter, the gate potential negative level shift circuit 8 can provide the same effect as described above.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a switching circuit having a MOS gate electrode according to the present invention.

FIG. 2 is a timing chart showing a potential change of each part of the circuit of FIG.

FIG. 3 is a gate potential waveform diagram showing a change in gate potential of the MOS drive circuit in FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 High side output element 2 Low side output element 5 Choke coil 6 Load 8 Gate potential negative level shift circuit (Low side output element drive circuit) 81 Low level potential lowering circuit (Negative bias generation part) 82 Buffer circuit 84 Diode 86 Resistance (voltage drop) element)

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiroshi Matsumae 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Inside Denso Corporation (72) Inventor Toshihiko Sugiura 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Denso Corporation (72) Inventor Shigeo Hirashima 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Inside Denso Corporation (72) Inventor Hironori Sato 14, Iwatani, Shimoba-Kakucho, Nishio-shi, Aichi Prefecture F-term in Japan Automotive Parts Research Institute, Inc. (Reference) 5H730 AA17 BB13 BB57 DD04 EE14 5J055 AX02 AX07 AX13 AX27 AX37 AX55 AX56 BX16 CX19 DX09 DX13 DX22 DX56 EY01 EY05 EY10 EY12 EY13 EY21 EZ20 GX01 GX04

Claims (3)

[Claims] A low-side output element having a MOS gate electrode for connecting a negative power supply line to an output terminal; a low-side output element driven by an input high-side input voltage and connecting a positive power supply line to the output terminal; And a low-side output element drive circuit that causes the low-side output element to operate substantially in reverse with respect to the high-side output element, wherein the low-side output element drive circuits are connected in parallel with each other. A negative bias generating section having a capacitor and a constant voltage drop element, and having a low-side input voltage substantially opposite in phase to the high-side input voltage at one end, and a gate electrode at the other end of the negative bias generating section. A low-side MOS transistor connected to the output terminal, the output voltage having the same phase as the potential of the other end of the negative bias generation section being connected to the low-side MOS transistor; A buffer circuit for applying to the MOS gate electrode of the id output element, the anode electrode lower power supply connection terminal of the buffer circuit,
A diode having a cathode electrode connected to the negative power supply line, a voltage drop element that connects the other end of the negative bias generator and the lower power supply connection end of the buffer circuit to generate a predetermined voltage drop, A MOS switching circuit comprising: 2. The MOS switching circuit according to claim 1, wherein a DC-DC step-down converter is configured together with a choke coil provided between the output terminal and an external low-voltage load.
A MOS switching circuit, wherein a DC high-voltage power supply is connected between the positive and negative power supply lines. 3. The MOS switching circuit according to claim 1, wherein a DC-DC step-up converter is configured together with a choke coil provided between the output terminal and an external DC low-voltage power supply, and the DC high-voltage load is a positive-negative load. A MOS switching circuit, which is connected between power supply lines.