JP2001319828A - Capacitor array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of easily manufacturing a capacitor array which is small in size but has large capacitance at a low cost without changing a usual mounting method. SOLUTION: A first capacitor unit Na1 and a second capacitor unit Na2 are each formed through a manner in which two inner electrodes 2 to 5 confronting each other through the intermediary of a dielectric layer l are disposed in a laminate 11 composed of the laminated dielectric layers l, and the capacitor units Na1 and capacitor units Na2 are alternately disposed in line in the laminating direction of the dielectric layers 1 for the formation of a capacitor array. The inner electrodes 2 and 3 of the first capacitor unit Na1 are extended from different positions to the different edge faces of the laminate 11, their extensions are connected to first outer electrodes 6 and 7, and on the other hand the inner electrodes 4 and 5 of the second capacitor unit Na2 are extended from the different positions to the main surface of the laminate 11, and their extensions are connected to second outer electrodes 8 and 9 formed on the main surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor array in which a plurality of capacitor units are stacked in a direction in which dielectric layers are stacked.

[0002]

2. Description of the Related Art With the spread of various electronic devices, the size and weight of these devices have been rapidly reduced. Especially in recent years,
There is an increasing demand for smaller and lighter electronic devices for portable use, such as a camera-integrated VTR, a mobile phone, a notebook personal computer, and a palmtop computer.

[0003] If the size and weight of such electronic devices are reduced, the circuit boards used for the electronic devices must be reduced in size and weight. From the mounting type, in which the pins of the electronic components are inserted into the through holes formed in the printed circuit board and soldered, the electronic components are placed and soldered on the conductive pattern lands provided on the printed circuit board to reduce the size and weight To surface mount technology (SMT).

The electronic components used in the SMT are collectively referred to as surface mount components (SMD). For example, in the field of capacitors, chip-type multilayer ceramic capacitors and capacitor arrays in which a plurality of capacitors are incorporated in an element are listed. Can be

FIG. 7 is an external perspective view of a conventional capacitor array 40, and FIG.
0 is a cross-sectional view, in which (a) is a partial cross-sectional view taken along line AA, and (b) is a partial cross-sectional view taken along line BB.

As shown in the figure, a capacitor array 40 has, for example, a plurality of internal electrodes 42a and 43a opposed to each other between layers of a laminated body 51 in which a plurality of dielectric layers 41 are laterally laminated. Each of the internal electrodes 42a and 43a is extended to a position on a different end face of the laminated body 51, and the external electrodes 46a and 4a are arranged on the end face of the laminated body 51.
7a. The dielectric layer 41 and the internal electrode 4
A capacitor unit N is formed by 2a, 43a and external electrodes 46a, 47a. This capacitor unit N
Are formed in the stacking direction of the dielectric layers 41 as needed to form the capacitor array 40. In the figure, adjacent capacitor units Na (42a, 43
a, 46a, 47a), Nb (42b, 43b, 46)
b, 47b),... are shown. Here, the colored part
3 shows a connection portion with an external electrode.

[0007] By using such a capacitor array 40, a single capacitor can be grouped as compared with the conventional one, variations in the size and shape of each capacitor can be suppressed, and the mounting work on the circuit board can be reduced. It can be simplified.

Conventionally, when a multilayer ceramic capacitor is mounted on a printed circuit board or the like, it is necessary to disperse lands that are slightly larger than each capacitor element on the circuit board, so that high-density mounting is required. Although it was difficult, the use of the capacitor array 40 enables high-density mounting by reducing the distance between lands. Further, the number of mountings can be reduced, and the mounting cost can be reduced.

[0009]

However, according to the capacitor array 40, the external electrodes 46a and 46b or the external electrodes 47a and 47b of the adjacent capacitor units Na-Nb are connected to the substrate mounting surface on the end face of the laminated body 51. It is necessary to provide a distance so as to prevent conduction by the solder. Generally, the distance y between external electrodes is designed to be larger than the width x of the external electrodes. For example, in a 2012-type capacitor array according to the EIA standard, when the width x of the external electrodes is 0.2 mm, the distance y between the external electrodes is 0.3 mm. Therefore, it is necessary to intervene a large number of dielectric layers that do not interpose an internal electrode between adjacent internal electrodes, and since this portion does not generate a capacitance, it is merely an insulating layer, and it is necessary to meet a product demand for a small and large capacity. However, there is a problem that it may cause an increase in size.

The present invention has been achieved in view of the above problems, and an object of the present invention is to provide a capacitor array capable of realizing a small and large capacity.

[0011]

In order to solve the above-mentioned problems, a capacitor array according to the present invention has a structure in which a plurality of dielectric layers are laminated in a rectangular laminate at least facing each other with the dielectric layers interposed therebetween. The first, in which two internal electrodes are arranged,
A capacitor array in which a plurality of second capacitor units are alternately arranged in the stacking direction of the dielectric layers, wherein the first capacitor unit has different end faces of the stacked body from positions where internal electrodes are different from each other. And the extension portion is connected to at least two first external electrodes formed on each end face of the laminate, and the second capacitor unit is configured such that each internal electrode is formed from a position different from each other. The present invention is characterized in that it extends to the main surface of the laminate and that the extension is connected to at least two second external electrodes formed on the main surface of the laminate.

According to the structure of the present invention, in addition to the capacitance generated between the internal electrodes in the first capacitor unit, the capacitance is generated in the second capacitor unit. An invalid area that does not occur is suppressed as much as possible. That is, since the second capacitor unit can be formed in an invalid region where no capacitance is originally generated in the capacitance generated between the internal electrodes in the first capacitor unit, the second capacitor unit is added to the capacitance of the original capacitor array. The capacitance generated between the internal electrodes in the capacitor unit is added, thereby realizing a small size and a large capacitance.

Further, the second external electrode formed on the main surface side of the second capacitor unit is provided on a surface different from the first external electrode formed on the end surface side of the first capacitor unit originally formed on the end surface. Accordingly, the first external electrodes formed on the same surface of the multilayer body can be sufficiently separated from each other, and the first external electrodes and the second external electrodes can be prevented from conducting with the solder at the time of mounting without short-circuiting. Can be.

Therefore, a part of the internal electrode of the first capacitor unit is extended to the main surface of the laminate, and
The extension may be connected to one of the second external electrodes, or may be configured so that one of the first external electrodes and one of the second external electrodes are directly connected.

With such a configuration, when connected to either the first or second external electrode, the capacitances of the first and second capacitor units can be obtained at the same time, so that the mounting on the circuit board is simplified. Can be done. Further, since the first external electrode has exactly the same shape as the conventional capacitor array, the conventional mounting method of the capacitor array can be used as it is. Furthermore, there is no significant change in the manufacturing of the internal electrodes only by changing the number of the internal electrodes, and the manufacturing method of applying the first external electrode to the laminated body also uses the same direction as before. Therefore, even if the capacity is increased, it is possible to manufacture without changing the mounting method.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an external perspective view of a capacitor array according to the present invention. 2 is a cross-sectional view of the capacitor array of FIG. 1, (a) is a partial cross-sectional view taken along line AA, and (b) is a partial cross-sectional view taken along line BB. It is. FIG. 3 is an exploded perspective view of a main part of the capacitor array of FIG.

Referring to FIG. 1, a capacitor array 1 according to the present invention is shown.
Reference numeral 0 denotes, for example, a rectangular laminated body 11 formed by laminating a plurality of dielectric layers 1, and a plurality of capacitor units N formed in the laminated body 11 in the laminating direction of the dielectric layers 1. . The capacitor unit N includes capacitor units Na ₁ , Nb ₁ as a first capacitor unit and capacitor units Na ₂ , N as a _second capacitor unit.
consists b ₂ Prefecture, first, second capacitor units are formed alternately with each other.

The dielectric layer 1 is made of a strip-shaped green sheet, and is made of a dielectric material such as barium titanate or strontium titanate.

The capacitor unit Na ₁ has at least two internal electrodes 2 a and 3 a facing each other with the dielectric layer ₁ of the multilayer body 11 interposed therebetween, and the internal electrodes 2 a and 3 a are located at different positions from each other. It extends to different end faces. That is, for example, the internal electrode 2a extends to one end surface of the laminate 11 and the extension portion is
Is connected to an external electrode 6a formed on one end face of
The internal electrode 3 a extends to the other end surface of the multilayer body 11, and the extending portion is connected to the external electrode 7 a formed on the other end surface of the multilayer body 11. The capacitor unit Nb ₁ similarly plurality of internal electrodes 2b, 3b, and is formed with external electrodes 6b, 7b.

The capacitor unit Na ₂ has at least two internal electrodes 4a and 5a facing each other, and the internal electrodes 4a and 5a extend from different positions to different main surfaces of the laminated body 11. That is, for example, the internal electrode 4a extends to the upper main surface of the multilayer body 11, and the extending portion is connected to a pair of external electrodes 8a formed on the upper main surface of the multilayer body 11. The electrode 5a extends to the lower main surface of the multilayer body 11, and the extending portion is connected to the external electrode 9a formed on the lower main surface of the multilayer body 11. The capacitor unit Nb ₂ likewise plurality of internal electrodes 4b, 5b, and is formed with external electrodes 8b, 9b.

The internal electrodes 2a-
3a, 2b-3b and internal electrodes 4a-5a, 4b
The capacitance component can be formed by facing between −5b. The internal electrodes 2 to 5 of the capacitor unit N
As the material of (2a to 5b), a noble metal material such as Pd, Ag-Pd alloy, or a base metal such as Ni or Cu is used.

Here, in FIG. 2, the colored portions indicate the connection portions between the internal electrodes 3 to 5 and the external electrodes 6 to 9. Also,
In FIG. 2A, a dotted line and an alternate long and short dash line are used to distinguish the external electrode 8 and the external electrode 9 printed on the upper main surface and the lower main surface, respectively. Further, in FIG. 2B, a dotted line and an alternate long and short dash line are used to distinguish the external electrodes 6 and 7 printed on one end face and the other end face, respectively.

The layout of the external electrodes 6a, 6b, 7a, 7b is different from that of the
Are formed in a pair on the two end faces. On the other hand, the arrangement of the external electrodes 8a, 8b, 9a, 9b is as follows.
It is formed on both main surfaces of the laminated body 11 different from each other.

However, as shown in FIGS. 1 and 3, external electrodes 8a and 8b or external electrodes 9a and 9b (not shown in FIG. 1; the same applies hereinafter) formed on the main surface side of the laminated body 11 interfere with each other. The external electrodes 8a and 9a are formed at positions close to the external electrode 6a on the end face side, and the external electrodes 8b and 9b are formed at positions close to the external electrode 7b on the end face side. 9a are not formed on the same surface. Thus, for example, the external electrodes 8a and 8b on the same surface are arranged in a staggered manner, and the external electrodes 8a and 8b and the external electrodes 9a and 9
b are shifted in position so as not to face each other.

The external electrodes 6 (6a, 6b), 7 (7
a, 7b), 8 (8a, 8b), 9 (9a, 9b) contain noble metals such as silver and palladium, or base metals such as nickel and copper, or alloys thereof, and have low melting materials such as glass. To improve the adhesion strength of the electronic component 20 to the ceramic. In particular, the external electrodes 6 and 7 formed on the end surfaces of the laminate 11 are formed by a conventional dip method or the like.
The external electrodes 8 and 9 formed on the main surface side are formed by applying and baking a conductive paste by a method such as screen printing or by a conductive film forming method such as an electroless plating method or a sputtering method.

Also, as a characteristic part of the present invention, the capacitor unit Na ₁ as the _first capacitor unit and the second
Capacitor unit Na ₂
DOO, but also, the capacitor unit Nb ₁ and by a capacitor unit Nb ₂ a second capacitor unit is electrically connected to the first by only one of the connection of the external electrodes is a first capacitor unit, The capacity of both the second capacitor units is obtained.

That is, for example, a part of the internal electrode 3a is extended to the main surface on the upper surface side, and the extended part is connected to the external electrode 8a.
In addition, a part of the internal electrode 4a extends to the main surface on the lower surface side, and the extending portion is connected to the external electrode 9a to form a capacitor unit group Na. A capacitor unit Nb is formed by a similar configuration.

The capacitor unit N (Na ₁ , N
a ₂ , Nb ₁ , Nb ₂ ), at least two internal electrodes may be continuously formed, and the number of continuously formed internal electrodes is not limited.

Next, another embodiment of the present invention will be described with reference to FIGS. Note that the same reference numerals are given to the same portions as those in the above-described embodiment. 4 is a perspective view of a capacitor array according to another embodiment, FIG. 5 is a cross-sectional view of the capacitor array of FIG. 4, (a) is a partial cross-sectional view taken along line AA, (B) is a partial cross-sectional view taken along line BB. FIG. 6 is an exploded perspective view of a main part of the capacitor array of FIG.

As shown, the capacitor array 1 of the present invention
0, the internal electrodes 2a, external electrodes 6a and extending portions extending from 3a was formed on the respective different end faces, the first capacitor unit Na ₁ is connected to 7a are formed. Further, the internal electrodes 4a and 5a are at different positions from each other, and
Are extended to the same upper surface side main surface, the external electrodes 8a are formed therein, the capacitor unit Na ₂ of the connected second is formed in 9a. Then, the external electrodes 6a,
7a and the external electrodes 8a, 9a are connected to each other by the connecting portion S to form the laminate 1
They are electrically connected via one ridge line (corner).

In this case, the first capacitor unit Na
₁ of the internal electrodes 2a, 2a, 3a, of 3a, provided as a second capacitor unit Na ₂ near the internal electrodes 2a, the connection portion S faces the laminate 11 main surface located directly above substantially the 3a comes ing. This is because the first capacitor unit Na
_Since the arrangement of the _first and second capacitor units Na ₂ is too close to each other, for example, a gap is formed between the external electrode 8a and the external electrode 8b so as not to interfere with each other at the connection S between the two. It is in. Therefore, the internal electrodes 2a,
3a may be formed to face the first plurality of internal electrodes 2a, 3a of the capacitor unit Na ₁ close to the second capacitor unit Na ₂ in the case of multiple forms.

Therefore, a part of the internal electrodes 2 (2a, 2b) 3 (3a, 3b) as shown in the first embodiment extends to the main surface side and the external electrodes 8 (8a, 8b), 9 (9a,
9b), the area for forming the external electrodes 8, 9 can be reduced, the external electrodes 8, 9 can be formed on the same surface, and the adjacent external electrodes 8, 9 can be formed.
9 does not need to be shifted perpendicularly to the stacking direction.

Next, a method for manufacturing the capacitor array 10 of the present invention will be described. Hereinafter, the distinction between a, b and 1, 2 in the figure of the capacitor unit will be omitted for the parts common to both. From a slip in which a solvent, a dispersant, a binder, and the like are mixed with a dielectric powder and a sintering aid, a ceramic green sheet to be the dielectric layer 1 is formed by a doctor blade method. The molding method includes other methods, pulling method,
A die coater, a gravure roll coater or the like may be used.

A metal ink for forming the internal electrodes 2 to 5 is printed on the dielectric layer 1 by a screen printing method. After that, the dielectric layers 1 on which the internal electrodes 2 to 5 are printed are laminated in the order shown in FIG. 3, and then, are thermocompression-bonded to obtain the block-shaped laminated body 11.

Next, the laminated body 11 is cut into a capacitor block including the capacitor unit N by a pressing blade.
When the laminate 11 is thick, it is desirable to cut it by a dicing method. At this time, the lead portion of the internal electrode in each capacitor unit N is exposed.

Next, the block-shaped laminate 11 is heated at 250 ° C.
After preliminarily firing in a furnace at ~ 400 ° C to remove the binder components, put in a main firing furnace and simultaneously sinter the dielectric ceramics 1 and the internal electrodes 2-5 at 1250-1300 ° C at an appropriate temperature of the ceramic material. .

Thereafter, in order to electrically connect the respective capacitor units N to the outside, the external electrodes 6, 7 are suitably placed on the end faces of the sintered body, and the external electrodes 8, 9 are placed on the upper and lower surfaces of the sintered body, respectively. It is formed by an electrode forming method. Thus, FIG.
Is obtained.

Thus, according to the capacitor array 10 of the present invention, a rectangular laminated body 11 in which a plurality of dielectric layers 1 are laminated.
Inside, at least two opposing each other with the dielectric layer 1 interposed therebetween.
A capacitor array 10 in which a plurality of first and _second capacitor units Na ₁ and Nb ₂ having two internal electrodes arranged alternately and arranged in the direction in which the dielectric layers 1 are stacked;
Of the capacitor unit Na _1, the internal electrodes 2, 3 extend from different positions to different end faces of the multilayer body 11, and the first external electrodes 6, 7 whose extension portions are formed on the respective end faces of the multilayer body 11. In the second capacitor unit Nb, the internal electrodes 4 and 5 extend from different positions to the main surface of the multilayer body 11, and the extending portions extend to the main surface of the multilayer body 11. Second external electrodes 8, 9 formed
Connected to the internal electrodes 2 and 3, in addition to the capacitance generated between the internal electrodes 2 and 3, a capacitance is also generated between the internal electrodes 4 and 5; Can be realized.

Since the external electrodes 8 and 9 are provided on a surface different from the external electrodes 6 and 7, the external electrodes 6 and 7 are provided.
The spacing between the capacitor units N can be made sufficient, and the external electrodes 8 and 9 can be prevented from being short-circuited by the solder on the board mounting surface. Therefore, the conventional mounting method of the capacitor array can be used as it is. Further, since a conventional method for manufacturing a multilayer ceramic capacitor element can be used, a simple and inexpensive manufacturing method can be achieved. Here, the amount of solder at the time of mounting is desirably minimized so that the solder does not enter under the element at the time of mounting and a short circuit accident does not occur.

After sintering, the surfaces of the external electrodes 8 and 9 are
The coating may be performed with an insulating resin or the like. If a coating layer is provided on the surfaces of the external electrodes 8 and 9, the above-described short circuit accident can be more reliably prevented, and any mounting method can be used. Alternatively, it is also possible to prevent the above-mentioned short circuit accident by providing all the external electrodes 8 and 9 on the same surface and making the surface facing this surface the mounting surface during mounting.

It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the scope of the present invention.

[0042]

As described above, according to the structure of the present invention,
The first capacitor units and the second capacitor units formed in the stacking direction of the dielectric layers are alternately arranged, and the leading directions of the external electrodes of the first and second capacitor units are different from each other. Since at least two first external electrodes are formed on the end surface side and at least two second external electrodes are formed on the main surface side, the second capacitor is connected to the second capacitor in addition to the capacitance generated between the internal electrodes of the first capacitor unit. Since a capacitance is also generated between the internal electrodes of the capacitor unit, an ineffective area where no capacitance is generated is reduced, and a capacitor array that is reduced in size and increased in capacitance can be provided.

Further, the first external electrode formed on the main surface side of the second capacitor unit has the first external electrode formed on the end surface.
By providing the capacitor unit on the surface different from the first external electrode, the first external electrodes formed on the same surface of the multilayer body can be sufficiently separated from each other. Can be prevented from conducting with the solder during mounting without short-circuiting.

Further, a part of the internal electrode of the first capacitor unit is extended to the main surface of the laminate, and the extended part is connected to the second external electrode, or With the configuration in which the first external electrode and the second external electrode are directly connected to each other, the capacitance of the first and second capacitor units can be obtained at the same time when connected to either the first or second external electrode. Thus, it is possible to provide a capacitor array that can be easily mounted on a circuit board.

Since the first external electrode has exactly the same shape as the conventional capacitor array, the conventional mounting method of the capacitor array can be used as it is.
Unlike the conventional method, there is no significant change in the manufacturing of the internal electrode only by changing the number of the internal electrodes, and the manufacturing method of applying the first external electrode to the laminate can be used as it is. Therefore, even if the capacity is increased, it is possible to manufacture without changing the mounting method.

[Brief description of the drawings]

FIG. 1 is an external perspective view of a capacitor array according to the present invention.

FIG. 2 is a cross-sectional view of the capacitor array of FIG.
(A) is a partial cross-sectional view taken along line AA, and (b) is a partial cross-sectional view taken along line BB.

FIG. 3 is an exploded perspective view of a main part of the capacitor array of FIG. 1;

FIG. 4 is an external perspective view showing a capacitor array according to another embodiment of the present invention.

FIG. 5 is a sectional view of the capacitor array of FIG. 4,
(A) is a partial cross-sectional view taken along line AA, and (b) is a partial cross-sectional view taken along line BB.

FIG. 6 is an exploded perspective view of a main part of the capacitor array of FIG. 4;

FIG. 7 is an external perspective view of a conventional capacitor array.

8 is a cross-sectional view of the capacitor array of FIG.
(A) is a partial cross-sectional view taken along line AA, and (b) is a partial cross-sectional view taken along line BB.

[Explanation of symbols]

10 Capacitor array 11 Laminated body 1 Electric layer 2 (a, b), 3 (a, b)... Internal electrode 4 (a, b), 5 (a, b)... Internal electrode 6 (a, b), 7 (a, b). 1 external electrode 8 (a, b), 9 (a, b) ... second external electrode N (a, b) ... first and second capacitor units x ...・ ・ ・ ・ ・ ・ ・ ・ ・ Width of external electrode y ・ ・ ・ ・ ・ ・ Distance between external electrodes

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (3)

[Claims] A first and a second capacitor unit in which at least two internal electrodes facing each other with the dielectric layer interposed therebetween are alternately arranged in a rectangular laminate in which a plurality of dielectric layers are laminated. A capacitor array in which a plurality of the dielectric layers are aligned in a stacking direction of the dielectric layer, wherein the first capacitor unit has internal electrodes extending from different positions to different end faces of the multilayer body, and A portion is connected to at least two first external electrodes formed on each end surface of the laminate, and in the second capacitor unit, the internal electrodes extend from different positions to the main surface of the laminate. A capacitor array, wherein the extension is connected to at least two second external electrodes formed on the main surface of the laminate. 2. A method according to claim 1, wherein a part of the internal electrode of the first capacitor unit extends to a main surface of the multilayer body, and the extending part is connected to one of the second external electrodes. The capacitor array according to claim 1, wherein 3. The device according to claim 1, wherein one of said first external electrodes is directly connected to one of said second external electrodes.
The described capacitor array.