JP2001308109A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a relatively deep (50 μm or longer) via hole. SOLUTION: The source, drain, and gate of an FET are formed on the main surface of a semiconductor substrate, and the main surface of the semiconductor substrate is coated with high-viscosity resist by 14 μm or longer. After that, the semiconductor substrate is maintained at normal temperature or less, Cl2 is selected to be at least equal to BCl3, and the semiconductor substrate region at the lower part of an opening hole window is etched.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a via hole penetrating from the front side to the back side of a semiconductor substrate, and a method of manufacturing the same.
The present invention relates to a device suitable for an MMIC (microwave monolithic integrated circuit).

[0002]

2. Description of the Related Art A semiconductor device having a via hole for electrically connecting a front surface and a back surface of a semiconductor substrate and a method of manufacturing the same are described in, for example, Japanese Patent Application Laid-Open No. 4-7845 (hereinafter referred to as "prior art 1"). JP-A-2-54937 (hereinafter referred to as Prior Art 2), JP-A-8-78437 (hereinafter referred to as Prior Art 3), and JP-A-10-3031.
No. 98 (hereinafter referred to as prior art 4).

GaAsFE having via-hole structure
T, MMIC (microwave monolithic integrated circuit)
It is said that it is suitable for a microwave band or the like because the ground inductance is smaller than when the source electrode is grounded by a bonding wire.

FIG. 7 shows a semiconductor device of this type shown in Prior Art 1. On the surface of the GaAs substrate 1, a source electrode 2a, a drain electrode 2b, and a gate electrode 3 are provided. Then, a metallized pattern 7a of Au or the like connected to the source electrode 2a and a wiring pattern 7b connected to the drain electrode 2b are formed. Also, back metallization 8
To electrically connect the source electrode 2a to the source electrode 2a.

The opening of the via hole 9 is formed by processing the GaAs substrate 1 to a thickness of 30 μm thinner than the back surface of the substrate.

On the second page, the lower left column, lines 14 to 20 states, “The method of forming a via hole from the surface of a semiconductor substrate includes a step of thinning the semiconductor substrate in the manufacturing process. When the bottom of the via hole is exposed, a projection is generated at the bottom of the via hole due to the variation in the thickness of the semiconductor substrate, as shown in FIG. 2 (c). "

Further, Prior Art 2 also discloses a method of forming a via hole in a GaAs FET, MMIC, or the like used for an MMIC or the like. For example, the sixth prior art 2
In line 17 in the lower right column of the page to line 1 in the upper right column of the same page 7, first, "This time, the V / V
As the H formation method, the replacement time (r
It has been found that the reduction of the elongation time has a high aspect ratio and is effective as a high-speed etching method, which enables the via-hole electrode structure of the present invention. In addition, "under the above pressure conditions using, for example, a Cl ₂ + Ar-based gas as a supply gas,..., Etching depth to 300 μm / 100 min, aspect ratio 10
The above values are obtained, and this etching rate shows an increasing tendency due to an increase in the power density and a decrease in the replacement time. ".

[0008] Further, on page 8, upper left column, lines 12 to 16, "When only a resist is used as a mask as a reaction product in a V / H hole, a resist material is mainly used on the side wall. A residue is easily generated, resulting in a decrease in reproducibility of the V / H hole shape. ", Which points out that a residue is generated in a via hole (V / H).

The size (depth) of the via hole itself imposes restrictions on the thickness of the GaAsFET or MMIC substrate itself. That is, if the depth of the via hole that can be formed is, for example, 30 μm, the thickness of the entire substrate must necessarily be reduced to about 30 μm in order to penetrate the front and back surfaces of the substrate. However, making the substrate thinner is unfavorable because it lowers the mechanical strength.

Further, with reference to Prior Art 3, a semiconductor device using a via hole electrode and a method of manufacturing the same are shown in great detail. The via hole shown here has an opening diameter of 8 to 10 μm and a depth of about 30 μm as described in the paragraph [0162]. With this size, the [000] of the prior art 3
2] As described in the paragraph, there is no particular problem in the processing shape and the arrangement position of the via hole.

Further, referring to the prior art 4, the [00]
65] In the paragraph, GaAs of a type forming a via hole
s Substrate thicknesses of 150 μm, 100 μm, and 30 μm are mentioned. Further, the technology of the first embodiment of the prior art 4 can be applied only to GaAs having a film thickness of 100 μm and 30 μm.
It is described that only the s substrate is used.

As is apparent from the above prior art, the depth of a via hole is limited to at most about 100 μm.

The present inventor has conducted various experiments before reaching the present invention. In particular, it has been found that when a via hole having a via hole depth of 100 μm or more is formed, the processed shape of the via hole is greatly affected.

FIG. 6 shows one experiment which the inventor tried before reaching the present invention. In FIG. 6, a high-viscosity resist (product name: PMER-N-Ca1000) is formed on the main surface of the GaAs substrate 20.
PM, manufactured by Tokyo Ohka Co., Ltd.) 21. Thereafter, a GaAs substrate was placed on an electrode of an etching apparatus (not shown) and maintained at a temperature of about 40 ° C. Thereafter, Cl ₂ : B is supplied to the etching apparatus.
An etching gas having a flow ratio of Cl ₃ : Ar gas of 6: 6: 1 was introduced. As a result, the width W1 of the substrate 20 is about 40
A groove 24 having a thickness of about 100 μm and a depth H1 of about 100 μm was formed.
However, via holes are not etched vertically,
Undercuts 22 were formed, and needle-like residues 23 were formed at the bottoms of the via holes (grooves). The needle-like residue is fine thread-like GaAs, such as needles, remaining without being etched, and has a size of 5 to 20 μm in width and 5 to 5 μm in height.
It was 0 μm.

[0015]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a semiconductor device in which undercuts and needle-like residues do not occur despite the relatively deep via holes having a depth of 50 μm or more. And a method for producing the same.

[0016]

According to a first aspect of the present invention, there is provided an FET formed on a main surface of a semiconductor substrate, and a high-viscosity resist selectively formed on the main surface of the semiconductor substrate. A via hole provided from the opening of the pattern toward the back side of the semiconductor substrate; a gold plating layer formed in the groove; and a conductor connected to one electrode of the FET and the gold plating layer of the via hole. And a wiring electrically connected to the gold plating layer and formed on the back side of the semiconductor substrate.

According to this configuration, when a semiconductor substrate is mounted, the FET source portion can be mounted without gold wire wiring, so that the semiconductor device can be downsized.

The second aspect of the present invention is the first aspect of the present invention.
A via hole having a depth of 50 μm or more formed from an opening of a high-viscosity resist pattern having a viscosity of 500 CP or more selectively formed on the main surface of the semiconductor substrate toward the back surface of the semiconductor substrate. A gold plated layer formed in the groove, a conductor connected to one electrode of the FET and the gold plated layer of the via hole, and a conductive layer electrically connected to the gold plated layer and formed on the back side of the semiconductor substrate. And a semiconductor device provided with the wiring.

According to this configuration, when a semiconductor substrate is mounted, the FET source portion can be mounted without gold wire wiring, so that the semiconductor device can be downsized.

According to the invention of claim 3 of the present invention, titanium is formed in the via hole, a gold plating layer is formed on the titanium, and polyimide is filled in the via hole. Semiconductor device.

With this configuration, gold plating is stably formed on the GaAs substrate, and the via holes are filled with the polyimide resin, so that the reliability with respect to mechanical strength is enhanced.

According to a fourth aspect of the present invention, there is provided a method of forming a source, a drain and a gate on a main surface of a semiconductor substrate, and covering the main surface of the semiconductor substrate with a high-viscosity resist.
Forming an opening window in a predetermined position on the high viscosity resist, to hold the semiconductor substrate to room temperature or less, Cl _2,
A method of manufacturing a semiconductor device, comprising: a step of etching a semiconductor substrate region below an aperture window with an etching gas containing a BCl ₃ gas.

According to this structure, a relatively deep via hole having a depth of 50 μm or more and undercut can be formed in the semiconductor substrate.

According to a fifth aspect of the present invention, there is provided a method for forming an FET on a main surface of a semiconductor substrate and covering the main surface of the semiconductor substrate with a high-viscosity resist, Forming an aperture window, maintaining the semiconductor substrate at room temperature or lower, and etching the semiconductor substrate region below the aperture window using an etching gas containing Cl ₂ and BCl ₃ to form a via hole. Performing a step of forming gold plating in the via hole, filling the via hole with polyimide, and exposing or polishing the back surface side of the semiconductor substrate to expose the gold plating layer formed in the via hole. And a step of forming a wiring layer on the back side of the semiconductor substrate.

With this configuration, even if a relatively deep via hole having a depth of 50 μm or more is formed in the semiconductor substrate, deterioration of the mechanical strength and the quality reliability of the semiconductor device can be suppressed.

The invention according to claim 6 of the present invention is the method of manufacturing a semiconductor device according to claim 4 or 5, wherein Ar gas is added to the etching gas.

With this structure, the via hole etching effect is enhanced.

The invention according to claim 7 of the present invention is the invention according to claim 4 or 5, wherein the semiconductor substrate is kept at 15 ° C. or lower.

With this configuration, a via hole in which undercut is suppressed can be formed.

The invention according to claim 8 of the present invention is the method for manufacturing a semiconductor device according to claim 4 or 5, wherein the thickness of the high-viscosity resist covering the semiconductor substrate is 14 μm or more.

According to this structure, a relatively deep via hole having a depth of 100 μm or more can be formed from the main surface side to the back surface side of the semiconductor substrate.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fourth or fifth aspect, wherein the flow ratio of Cl ₂ : BCl ₃ of the etching gas is 1: 1 to 5: 1.

With this configuration, the flow rate of Cl ₂ as an etchant gas is made larger than that of BCl ₃ , so that the function of etching the substrate can be promoted.

According to a tenth aspect of the present invention, in the fourth or fifth aspect, when the substrate and the high-viscosity resist thereon are simultaneously etched by the etching gas, the etching of the substrate with respect to the etching rate of the high-viscosity resist is performed. Cl ₂ and BC so that the speed of
The ratio of l ₃ and Ar gas is selected.
It is a manufacturing method of the semiconductor device described.

With this configuration, a high-viscosity resist can be used for 14 times.
By applying about μm or more, via holes of 50 μm or more can be formed in the substrate by one etching.

The eleventh aspect of the present invention is the invention according to the fourth or fifth aspect, wherein the inductively coupled plasma (ICP) is used.
This is a method for manufacturing a semiconductor device in which Cl ₂ and BCl ₃ gases are introduced into the device and the semiconductor substrate region is etched.

According to this structure, the semiconductor substrate is etched by the high-density plasma, so that the uniformity of the etching is improved.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG.
The drain electrode 3 is formed on the main surface of the aAs substrate 30 by a predetermined method.
1 shows a state in which a gate electrode 32 and a source electrode 33 are formed. Although not shown in the subsequent steps, a high-viscosity resist 34 was applied to the entire main surface of the substrate 30 to selectively form a resist pattern.

FIG. 1B shows a high-viscosity resist having a viscosity of 500 to 1000 CP (for example, product name: PMER-N-Ca500PM or PMER-N) on the main surface of the substrate 30.
This shows a state in which an aperture window 35 is formed in the vicinity of the source electrode 33 after applying (−Ca1000PM; all manufactured by Tokyo Ohka Co., Ltd.) 34. The aperture window 35 was formed on the same main surface of the substrate 30 as the surface on which the source electrode of the FET was formed. Thereby, problems such as misalignment in mask alignment are solved. The width W of the aperture window may be set as appropriate, but is set here to about 50 to 70 μm. The thickness t of the resist is 23 to 25 μm. Here, the reason why the high-viscosity resist is adopted is that the resist is formed to be relatively thick on the semiconductor substrate. If this is a low-viscosity resist, the resist flows and the resist cannot be formed thick on the substrate 30. Become. That is, the thickness t of the resist is set to 23
The reason why the coating was able to be applied relatively thickly to ２５25 μm is due to the use of a high-viscosity resist.

Thereafter, the GaAs substrate 30 was subjected to anisotropic etching to form a via hole 35 having a width W of 70 μm and a depth H of 150 μm as shown in FIG.

Thereafter, as shown in FIG. 2D, the high-viscosity resist 34 is removed with, for example, an oxygen asher, and then washed with isopropyl alcohol (IPa), acetone, or the like, dried, and then at least one layer of titanium or gold is formed. First
The metal layer 36 was formed by vapor deposition on the entire surface of the substrate 30. First
The metal layer 36 is deposited on the main surface of the substrate 30 and inside the via hole 35. At this time, the width W of the via hole 35
However, when the width is about 70 μm as in the present invention, it was not possible to fill the entire via hole. In order to fill the entire via hole, it is necessary to perform processing by a method with a higher film forming rate.

The anisotropic etching used in the present invention is performed by using an inductively coupled plasma (ICP) apparatus. The details including the etching conditions will be described later.

As shown in FIG. 2E, after forming the metal layer 36 on the main surface of the substrate 30 as shown in FIG. 2D, a resist 37 is applied to the entire substrate 30 and selectively patterned. After that, a state is shown in which a second metal layer 38 made of gold plating is formed using the resist 37 as a mask, and a third metal layer 42 made of a titanium layer is further applied. As the resist 37, the high-viscosity resist used when forming the via hole 35 described above was used. However, the viscosity of the resist used in this step may be lower than that used in forming the via hole 35. This is because the resist used at this time is formed thinner than the high-viscosity resist used when forming the via hole.

As a result, the titanium layer 42 is peeled away from the portion where the resist 37 remains by the lift-off method, and the titanium layer 36 near the gate electrode 32 is etched. The source electrode 33 and the first metal layer 36 and the second metal layer 38 formed in the via hole 35 are formed so as to be electrically connected to each other and to be drawn out to the back surface side of the substrate 30.

Thereafter, as shown in FIG. 2F, a nitride film 43 is formed on the entire main surface of the substrate 30, and contact windows 44 and 45 are formed. Further, a polyimide resin 39 is selectively coated in the via hole 35 on the main surface of the substrate 30. This coating is not a requirement, but it increases the mechanical strength of the entire substrate 30.

Although not shown in FIG. 3 (g), the first metal layer 36 or the second metal layer 38 formed at the bottom of the via hole is exposed by polishing, for example, from the back side of the substrate 30. Then, the entire substrate 30 is subjected to a thinning process. This thinning process reduces the thickness of the substrate to about 100 μm. After that, when the wiring layer 40 is formed on the back side,
The source electrode 33 is connected to the first metal layer 36 and the second metal layer 38 and further connected to the wiring layer 40 and is led out from the back side of the substrate 30.

1 (a) to 1 (c), 2 (d) to
(F) and FIG. 3 (g) show only one field effect transistor (FET) for drawing. However, actually, a plurality of FETs are mounted on the GaAs FET and the MMIC, and wiring is provided between the plurality of FETs or between the plurality of electric elements via the wiring layer 40 on the back surface side of the substrate 30. Will be.

FIGS. 4A and 4B show an ICP apparatus used in the present invention. (A) shows the outline of the ICP device,
(B) is an enlarged view of the lower electrode portion. The ICP device used in the present invention is used when forming the via hole 35 in the process of moving from FIG. 1B to FIG.

The ICP device 50 shown in FIG.
A P coil 51, a lower electrode 52, and a gas nozzle 53 are provided. Furthermore, an exhaust system 55 for controlling the pressure in the chamber 54 and a vacuum gauge 5 for detecting the pressure are provided.
6 is provided.

The etching gas is supplied from a gas nozzle 53. The etching gas is a mixture of Cl ₂ / BCl ₃ / Ar gas, each of which is 105/35/10 SCC.
It was set to M and introduced into the chamber 54 from the gas nozzle 53. Although the addition of Ar gas is not necessarily indispensable in the present invention, by employing this, the effect of etching can be enhanced.

In the present invention, the flow rate of Cl ₂ acting as an etching gas is set to be about three times that of BCl ₃ . Thereby, the etching speed is accelerated.

The pressure in the chamber 54 is 1.0 to 1.0.
4.0 Pascal, power of ICP coil 51 is 100 ~
It was set to 1000W.

Further, the lower electrode 52 is supplied with RF bias power. In the present invention, a power of 10 to 500 W was supplied. By supplying the bias power, the etching speed is improved by the ion assist and the effects of anisotropic etching are obtained. Further, the lower electrode 52 is provided with a water cooling means 57 for cooling the entire lower electrode.

In the present invention, Cl ₂ and BC
The flow ratio of l ₃ is not limited to the above 3: 1 ratio.
Practically, there was no problem even at about 1: 1.

However, when the ratio was 0.8: 1.0, needle-like residues were generated in the via holes.

When the ratio of Cl ₂ to BCl ₃ is set to 6: 1, the degree of etching of the high-viscosity resist increases, and unless a thicker resist is applied, a via hole having a desired depth is formed. And the frequency of occurrence of undercut has also increased. From this, the preferred ratio of Cl ₂ to BCl ₃ is 1: 1 to 5: 1.
It is.

FIG. 4B is an enlarged view of the lower electrode 52. The lower electrode 52 is provided with cooling means 58 for keeping the substrate 30 at a normal temperature or lower. Usually, cooling means 5
Helium gas is supplied to 8, and the substrate 30 is kept at 15 ° C. or lower, preferably 10 ° C. or lower at room temperature or lower. Substrate 30
Is maintained at room temperature or lower, the undercut generated in the via hole 35 can be suppressed even if the etching effect is promoted by increasing the flow ratio of Cl _{2 to} BCl ₃ .

FIG. 5 shows a completed state when a via hole 35 is formed in the substrate 30 using the ICP apparatus shown in FIG. The width W of the via hole 35 is about 70 μm,
The depth H was about 150 μm. According to such a method, the size of the undercut was expected to be about several μm, but it was hardly observed in practice. Moreover, no needle residue was generated.

In the present invention, a relatively deep via hole is used.
Formed without undercut or needle-like residue
What can be done mainly has the action of etching
Cl _TwoGas to BCl_ThreeAbout 1 to 5 times the gas
Therefore, the etching action is accelerated and the etching rate is increased.
And keeping the semiconductor substrate below room temperature.
Acting as a deposition gas_ThreeLower the flow ratio of
Suppresses undercuts on the sidewalls of via holes
Probably due to the formation of a sufficient sedimentary layer
You.

The high-viscosity resist 34 applied to the portions other than the via holes was also etched by about 20 μm by the etching action when forming the via holes, and the thickness thereof was reduced to 3 to 5 μm. That is, since the depth of the via hole was 150 μm, the result was that the etching rate ratio of the substrate 30 to the etching rate of the high-viscosity resist 34 was 150/20 = 7.5 times. It can be said from this result that the high-viscosity resist is 1
Assuming that 4 μm is applied, the via hole has 7.5
It can be formed twice, that is, at a depth of 105 μm, which is sufficient to form a via hole of 100 μm or more.

When a relatively thick layer is formed by applying the high-viscosity resist 34 of 14 μm or more, a high-viscosity resist having a resist viscosity of 500 CP or more, preferably about 1000 CP is convenient.

As described above, the main feature of the configuration of the semiconductor device of the present invention is that a high-viscosity resist pattern is formed on the same side as the main surface of the semiconductor substrate on which the FET is formed.
A via hole formed using the resist pattern as a mask is provided. The via holes are formed by a resist pattern having a resist viscosity of 500 CP or more and a thickness of 14 μm or more.

The main feature of the method of manufacturing a semiconductor device according to the present invention is that a high-viscosity resist pattern is formed and a substrate on which the semiconductor device is to be formed is kept at a room temperature or lower when etching is performed using the resist pattern as a mask. while doing,
Anisotropic etching is performed by introducing Cl ₂ and BCl ₃ gas.

The thickness of the high-viscosity resist is selected to be 14 μm or more. Thereby, the depth can be formed to 100 μm or more.

Further, a feature of the present invention is that the flow ratio of Cl ₂ to BCl ₃ is selected from 1: 1 to 5: 1. Thereby, it is possible to form a via hole in which an undercut and a needle-like residue are not generated.

Although the present invention has been described using a GaAs substrate, the present invention is not limited to the case where a via hole is formed in another semiconductor substrate such as a silicon substrate, or when a memory capacity is formed instead of a via hole. It can also be applied to the case of forming a trench.

[0067]

As described above, according to the semiconductor device of the present invention, a high-viscosity resist pattern is formed on the main surface side of a semiconductor substrate on which an FET is formed, and a resist for forming a via hole is formed. Set the aperture window mask to F
Since the ET is formed from the same main surface side, via holes with high alignment can be formed, and Cl ₂ and BCl ₃ are formed.
By setting the flow rate ratio to a predetermined ratio and performing anisotropic etching when forming via holes at room temperature or less, it is possible to eliminate undercuts and to form deep via holes of 50 μm or more. .

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view of the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a sectional view of a semiconductor device according to an embodiment of the present invention;

FIG. 4 is a diagram showing an outline of an inductively coupled plasma (ICP) device used in an embodiment of the present invention.

FIG. 5 is a sectional view of a via hole obtained by the present invention.

FIG. 6 is a view showing an undercut and a needle-like residue generated in a conventional via hole.

FIG. 7 is a diagram showing a conventional semiconductor device having via holes;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 GaAs substrate 2a Source electrode 2b Drain electrode 3 Gate electrode 7a Metallized pattern 7b Wiring pattern 8 Backside metallized 9 Via hole 22 Undercut 23 Needle residue 30 GaAs substrate 31 Drain electrode 32 Gate electrode 33 Source electrode 34 High viscosity resist 35 Via hole 36 first metal layer 37 resist 38 second metal layer 39 polyimide resin 40 wiring layer 42 third metal layer 43 nitride film 44 contact window 45 contact window 51 ICP coil 52 lower electrode 53 nozzle 54 chamber 55 exhaust system 56 vacuum gauge 57 water cooling Means 58 Cooling means

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yukio Nakamura 1-1, Komachi, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. F-term (reference) 5F033 GG02 HH13 HH18 JJ13 JJ18 MM30 NN05 PP19 PP27 QQ07 QQ13 QQ15 QQ37 QQ41 QQ46 RR06 RR22 WW02 WW03 WW06 5F102 GB02 GC01 GD01 GJ05 HC16

Claims (11)

[Claims] 1. An FET formed on a main surface of a semiconductor substrate.
And a via hole provided from the opening of the high-viscosity resist pattern selectively formed on the main surface side of the semiconductor substrate toward the back surface side of the semiconductor substrate, and a gold plating layer formed on the via hole A conductor connected to one electrode of the FET and a gold plating layer of the via hole;
And a wiring electrically connected to the gold plating layer and formed on a back side of the semiconductor substrate. 2. An FET formed on a main surface of a semiconductor substrate.
And a via hole with a depth of 50 μm or more formed from the opening of the high-viscosity resist pattern having a viscosity of 500 CP or more selectively formed on the main surface of the semiconductor substrate toward the back surface of the semiconductor substrate. A gold plated layer formed in the via hole, a conductor connected to one electrode of the FET and the gold plated layer of the via hole, and a conductive layer electrically connected to the gold plated layer and formed on the back side of the semiconductor substrate. Semiconductor device comprising: 3. The semiconductor device according to claim 1, wherein titanium is formed in the via hole, gold plating is formed thereon, and the via hole is filled with polyimide. 4. A step of forming a source, a drain, and a gate on a main surface of a semiconductor substrate and coating the main surface of the semiconductor substrate with a high-viscosity resist, and forming an aperture window at a predetermined position on the high-viscosity resist. And a step of holding the semiconductor substrate at room temperature or lower and etching the semiconductor substrate region below the aperture window with an etching gas containing Cl ₂ and BCl ₃ gases. 5. A step of forming an FET on a main surface of a semiconductor substrate and coating the main surface of the semiconductor substrate with a high-viscosity resist;
Forming an opening window in a predetermined position on the high viscosity resist, to hold the semiconductor substrate to room temperature or less, Cl _2,
A step of etching a semiconductor substrate region below the opening window to form a via hole using an etching gas containing BCl ₃ , a step of forming gold plating in the via hole, and a step of filling the via hole with polyimide. A semiconductor device comprising: a step of exposing a gold plating layer formed in the via hole by etching or polishing from the back side of the semiconductor substrate; and a step of forming a wiring layer on the back side of the semiconductor substrate. Manufacturing method. 6. The method according to claim 4, wherein an Ar gas is added to the etching gas. 7. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor substrate is kept at 15 ° C. or lower in the step of etching. 8. The method of manufacturing a semiconductor device according to claim 4, wherein the high-viscosity resist covering the semiconductor substrate has a thickness of 14 μm or more. 9. A flow rate ratio of Cl ₂ : BCl ₃ is from 1: 1 to 5:
6. The method for manufacturing a semiconductor device according to claim 4, wherein 10. When a substrate and a high-viscosity resist are simultaneously etched by an etching gas, Cl ₂ , BCl ₃ , and the like are used such that the etching rate of the substrate is 5 to 10 times that of the high-viscosity resist. A
7. The method for manufacturing a semiconductor device according to claim 6, wherein a ratio of r gas is selected. 11. The method of manufacturing a semiconductor device according to claim 4, wherein Cl ₂ or BCl ₃ gas is introduced into an inductively coupled plasma (ICP) device to etch the semiconductor substrate region.