JP2001229037A - System for measuring virtual computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that it is necessary to operate processing (host (virtual computer control program) CKC and CPT interruption simulation) for comparing host CPT and CKC, and for setting the previous interruption as an SCPT in the case of the transition of processing between the host and a guest (virtual computer) in a conventional technique, and that overhead on guest instruction processing is generated. SOLUTION: Each host and guest is provided with a timer mechanism in this virtual computer system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clocking method of a computer, and more particularly to a clocking method of a virtual computer system suitable for realizing a plurality of timer mechanisms for a host or a guest as hardware. .

[0002]

2. Description of the Related Art Conventionally, as a timer mechanism of a virtual machine system, Japanese Patent Application Laid-Open No. 08-339307 discloses a method of realizing a timer mechanism for each guest using a set of ToD, CKC, CPT and a simulation-dedicated SCPT. Proposed.

[0003] This is because the CKC or CPT held by the host and the CKC or CPT held by the guest are
Is simulated by setting the smaller one of the correction values to the SCPT, thereby efficiently sharing the timer mechanism with a small number of gates.

FIG. 2 shows a configuration diagram of this prior art. FIG.
, 201 is an actual computer (hereinafter referred to as CU),
It is connected to the components shown in the figure via signal lines 230 and 240, and controls the components.

Although omitted in FIG. 2 for the sake of simplicity, the status description table in the main memory of the CU 201 includes clock comparator values (CKC) of the host and guest, CPU
The timer value (CPT) is held. Also, this CU20
In one main memory, a host and guest program status word (PSW) is also held.

Reference numeral 202 denotes a register for holding a host ToD value (hereinafter, referred to as HToD value) used by the VMCP (host), and 203 is connected to a plus one adder (hereinafter, referred to as ADD). The ADD 203 is a circuit that adds 1 to the data input from the ToD 202 and returns the data to the ToD 202. The host TOD value is set in the ToD 202 by the CU 201 via the signal line 230, and is thereafter updated by the ADD 203 for a fixed time. That is, TO
D202 and ADD203 constitute a clock mechanism for measuring the current time.

Reference numeral 204 denotes a CKC register (hereinafter, simply referred to as CKC) for holding the value of the CKC of the power source.
This is a register that holds the clock comparator value (CKC) of the host or guest that is currently being executed (current), which is given via the signal line 230 by 1.

Reference numeral 205 denotes a comparison circuit (hereinafter referred to as CoMP) for comparing the values of the ToD 202 and the CKC 204.
Along with 202, it is connected to a comparison circuit CoMP205. This CoMP 205 has a ToD value of ToD 202 and C
This is a circuit for comparing the CKC value of the KC 204 with the CKC value.

When the ToD value of the ToD 202 becomes larger than the CKC value, the CoMP 205 sends a CKC interrupt request signal to the CU 201 via the signal line 240. That is, the CKC 204 and the CoMP 205 constitute a timed timer mechanism.

Reference numeral 206 denotes a CPT register (hereinafter simply referred to as CPT) for holding the current CPT value.
1 is a register for holding the CPU timer value (CPT) of the currently executing host or guest provided through the signal line 230 by a 1 and a subtraction circuit (hereinafter referred to as SUB) 2
07. The SUB 207 is a circuit that returns the data input from the CPT 206 at regular intervals by minus one to the CPT 206. When the value becomes negative, the CPT 206 sends a CPT interrupt request signal to the CU 201 via the signal line 240. That is, CPT 206 and SU
B207 constitutes a subtraction timer mechanism.

Reference numeral 208 denotes a host CK which has been corrected as described below.
Simulation CPT holding C (hereinafter referred to as HCKC) value or host CPT (hereinafter referred to as HCPT) value
A register (hereinafter referred to as an SCPT), and a SUB209
It is connected to the.

The SUB 209 is provided at regular intervals with the SCPT 20
SCPT208 by subtracting -1 from the data input from 8
Circuit.

When the value becomes negative, the SCPT 208 sends an HCPT or HCKC interrupt request signal to the CU 201 via the signal line 240. That is, SCPT208,
The SUB 209 is a host timer simulation mechanism that simulates CKC or CPT of a host in a power-rented guest under a VM.

Reference numeral 210 denotes a work register (hereinafter referred to as TEMPCKC) for holding the value of the host CKC. Similarly, reference numeral 211 denotes a work register (hereinafter, referred to as TEMPCPT) for holding the value of the host CPT.

Next, an initialization operation and an interruption operation with the conventional timer mechanism will be described with reference to FIGS.

FIG. 3 is a processing flowchart for initializing the guest timer mechanism when switching from the host to the guest.

ToD, CKC, and CPT have H
ToD, HCKC and HCPT are set.

First, in step 301, the CU 201
Are the values of CKC 204 and CPT 206, HCKC and H
The CPT is fetched and stored in hardware such as a register and a memory. Next, in step 302, the host CKC
It is determined whether interruption acceptance is permitted. Specifically, when the external mask of the program state word (PSW) of the host is “1” and the CKC interrupt subclass mask of the control register of the host is “1”, acceptance of the host CKC interrupt is permitted.

If the host CKC interrupt is permitted, the process proceeds to step 303; otherwise, the process proceeds to step 304.

In step 303, the CU 201 executes HCK
Performs a correction operation called C-ToD and returns the result to TEMPCK.
C210, which is SCPT208, SUB
This is because the HCKC can be simulated using the H.209. That is, the value of HCKC-ToD is set to SC
PT208, subtract it using SUB209, and when it becomes negative, the ToD value of ToD202 (HTo
D) is regarded as HCKC.

Next, in step 304, the CU 201 determines whether the host is allowed to accept the CPT interrupt. Specifically, the external mask of the host PSW is "
When the CPT interrupt subclass mask of the control register of the host is "1", acceptance of the host CPT interrupt is permitted.

If the host CPT interrupt is permitted, the process proceeds to step 305. If the host CPT interrupt is not permitted, the process proceeds to step 305.
Proceed to 6.

In step 305, the HCPT captured in step 301 is stored in TEMPHCPT211.

In step 306, the CU 201 reads the guest clock comparator value (hereinafter referred to as GCCKC), the guest CPU timer value (hereinafter referred to as GCPT), and the correction amount (epoch difference) ED in the state description table in the main memory. .

In step 307, the CU 201 first sets G
An operation GCKC-ED is performed using CKC. This is to set the time of the guest freely, regardless of the current time, and is a correction operation for matching between the HToD of the ToD 202 and the GCKC. The value of GCKC-ED is set in CKC204. Next, CU201 is GC
Set PT in CPT 206.

In step 308, the CU 201 executes the TEMP obtained in step 303 and step 305.
The contents of HCKC 210 and TEMPHCPT 211 are compared, and the process proceeds to either step 310 or 309 depending on the magnitude relation. The case of step 309 is T
The case where the value of EMPHCC 210 is smaller than the value of TEMPHCPT 211, that is, HCKC is
This is a case where an interrupt is considered to occur before T. In this case, the CU 201 sends the TEMP
The value of the HCKC 210 is set, and the HCKC valid flag (HCKCVLD) in the CU 201 main memory is set to “1”. That is, HCKCVLD = "1" indicates that HCK
C indicates that the SCPT 208 has been set.

The case of step 310 is TEMPHC
This is the case where the value of the KC 210 is equal to or greater than the value of the TEMPHCPT 211, that is, the case where it is considered that an interrupt occurs in the HCPT before the HCKC. This Yang C
U201 has TEMPHCPT211 added to SCPT208.
Is set, and the HCKC valid flag (HCKCVLD) in the CU 201 main memory is set to “0”. That is, HCKCVLD = 0 indicates that HCPT is set in SCPT 208.

Thus, the initialization operation of the timer mechanism is completed. Thereafter, the ToD value of the ToD 202 becomes CKC 204
When the GCKC value is larger than the GCKC value, a CKC interrupt is reported from the CoMP 205 to the CU 201 via the signal line 240. The GCPT value of CPT 204 is SUB20
7, the signal is subtracted at regular intervals.
A CPT interrupt is reported to the CU 201 via the.

Thus, the SCPT 208 under the guest
The SUB 209 simulates the CKC or CPT operation of the host, and when the value of the SCPT 208 becomes negative, reports an HCKC or HCPT interrupt to the CU 201 via the signal line 240.

FIG. 4 is a processing flowchart showing an example of an interrupt process in the conventional timer mechanism.

When a timer interrupt occurs in the timer mechanism, the CU 201 first determines in step 401 whether the interrupt is an interrupt report from the SCPT 208.

If the interrupt is from the SCPT 208, an interrupt from the host, ie, HCKC or HCP
This is an interrupt due to T, and the process proceeds to step 402. In step 402, the CU 201 sets the HCKCVLD flag to "
It is determined whether it is 1 "or" 0 ".

If HCKCVLD = 1, SCPT20
Since the value set to 8 is the value of TEMPHCKC 210, that is, HCKC, the CU 201 reports an external interrupt by the clock comparator to the host.

If HCKCVLD = 0, SCPT20
Since the value set to 8 is the value of TEMPHCPT 211, that is, HCPT, the CU 201 reports an external interrupt by the CPU timer to the host.

If it is not an interrupt from the SCPT 208, the process proceeds to step 403. In step 403, the CU
If the interrupt 201 is an interrupt report from the CKC 204, since the GCKC is set in the CKC 204, the external mask of the guest PSW is “1” and the CKC interrupt subclass mask of the guest control register is “1”.
When 1 ", an external interrupt by the clock comparator is reported to the guest.

If it is not an interrupt from the CKC 204, the process proceeds to step 404. The CU 201 interrupts the CP
In the case of an interrupt report from the T206, since the GCPT is set in the CPT 206, when the external mask of the guest PSW is "1" and the CPT interrupt subclass mask of the guest control register is "1", C
Reports an external interrupt by the PU timer.

The embodiment of the conventional timer mechanism has been described above.

[0038]

According to the above prior art, when processing is transferred between a host and a guest, the host CPT, C
It is necessary to perform a process of comparing the KC and setting the one that interrupts first in the SCPT (simulation of the host CKC and the CPT interrupt), which causes a problem of an overhead in processing the guest instruction.

[0039]

In order to achieve the above object, the present invention provides a virtual machine system with a timer mechanism dedicated to each host and guest.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. Here, a virtual computer control program operating on a real computer is called RealHost mode (hereinafter referred to as RH), a virtual computer (hereinafter referred to as guest) operated under control of a host is referred to as Real Guest mode (hereinafter referred to as RG), and Guest operating under the control of the operating virtual machine control program is Inter
It is defined as a passive Guest mode (hereinafter referred to as IG).

FIG. 1 is a block diagram of one embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a real computer (hereinafter referred to as a CU).
The CU 101 is connected to the illustrated units via signal lines 130 and 140, and controls the respective units.

Although omitted in FIG. 1 for simplicity, in general, the host and guest clock comparator values (CKC) are stored in the state description table in the main memory of the CU 101.
The CPU timer value (CPT) is held.

The main storage of the CU 101 holds a host and guest program status word (PSW).

Reference numeral 102 denotes a ToD value (R
This register holds an HToD value, and is connected to an adder circuit (hereinafter referred to as ADD).

The ADD 103 is a circuit that adds 1 to the data input from the RHToD 102 and returns the data to the RHToD 102. The RHToD value is set to the signal line 1 by the CU 101.
Set in the RHToD 102 via 30, 30;
Thereafter, it is updated by the ADD 103 at regular intervals. That is, the RHToD 102 and the ADD 103 constitute a clock mechanism for measuring the current time.

Each of 104, 106 and 108 is R
A CKC register (hereinafter simply referred to as RHCKC, RGCKC, ICK) that holds the value of CKC corresponding to the H, RG, and IG modes.
GCKC), which is a register that holds a clock comparator value (CKC) provided by the CU 101 via the signal line 130 and corresponding to the currently executing (current) mode.

Reference numeral 105 denotes RHToD102 and RHCKC
Comparison circuit for comparing the value of 104 (hereinafter referred to as CoMP)
And is connected to the comparison circuit CoMP105 together with the RHToD102. The CoMP 105 is a circuit that compares the RHToD value of the ToD 102 with the CKC value of the RHCKC 104.

CoMP 105 is the To of RHToD102.
When the D value becomes larger than the CKC value, an RHCKC interrupt request signal is sent to the CU 101 via the signal line 140. That is, the RHCKC 104 and the CoMP 105 constitute a timed timer mechanism.

RGCKC106 and IGCKC108 are also R
A timed timer mechanism that performs the same operation as the HCKC 104 is configured.

110, 112 and 114 are RH,
CP holding the value of CPT corresponding to RG, IG mode
T register (hereinafter simply RHCPT, RGCPT, IGC
PT), which is a register for holding a clock comparator value (CKC) provided by the CU 101 via the signal line 130 and corresponding to the currently executing (current) mode, and is provided to a subtraction circuit (hereinafter referred to as SUB) 111. It is connected.

The SUB 111 performs RHCP at regular intervals.
RHC by subtracting data input from T110 by 1
This is a circuit for returning to the PT 112.

When the value of the RHCPT 112 becomes negative, the RHCPT 112 sends an RHCPT interrupt request signal to the CU 101 via the signal line 140. That is, RHCPT110 and SUB11
1 constitutes a subtraction timer mechanism.

Similarly, RGCPT112, IGCPT1
14 also constitutes a subtraction timer mechanism that performs the same operation as the RHCPT 110.

FIG. 5 is a processing flowchart for the case where the guest timer mechanism is initialized when switching from the host to the guest according to the present invention. Here, the branch for mode discrimination is shown in the figure for the sake of simplicity, but since the mode discrimination is actually performed by hardware,
No processing by the program occurs.

Although omitted in FIG. 1 for simplicity, the CU
101 is for separating RH, RG, IG mode,
It has two mode flags of IE MoDE and ISIE MoDE. When IE MoDE = 0, it indicates the RH mode, IE MoDE = 1 and ISIE MoDE = 0
Represents the RG mode when ISIE MoDE = 1 represents the IG mode.

When setting the value of CKC, step 50
At 1, the RH mode is determined. If IEMoDE = 0, the RHC mode is set and the CKC value is set in the RHCKC register.

Next, in step 502, the RG mode is determined. If ISIE MoDE = 0, it is the RG mode, so the CKC value is set in the RGCKC register.

At this time, if ISIE Mode = 1, the operation is in the IG mode, and the CKC value is set in the IGCKC register. Set the CPT as in Step 5
03 and 504 at IE MoDE and ISIE MoDE
Is determined, and the CP of the RH, RG, and IG mode registers is
Set the T value.

FIG. 6 is a processing flowchart showing an example of an interrupt processing process according to the present invention. Here, the branch for mode discrimination is shown in the figure to make the process easy to understand, but since the mode discrimination is actually performed by hardware, processing by a program does not occur.

First, when a CKC interrupt is detected, the RH mode is determined in step 601. IE MoDE
If = 0, since it is the RH mode, it is determined to be an RHCKC interrupt. Next, in step 602, the RG mode is determined.

If ISIE MoDE = 0, the mode is the RG mode, so it is determined that the interrupt is an RGCKC interrupt. At this time,
If ISIE Mode = 1, it is IG mode, so I
GCKC is determined.

Similarly, when a CPT interrupt is detected, in steps 603 and 604, the IE MoDE and ISI
E MoDE is determined, and a CPT interrupt from each of the RH, RG, and IG modes is determined.

As described above, the provision of the CKC and CPT registers respectively corresponding to the RH, RG, and IG modes eliminates the need for the initialization processing of the timer mechanism and the mode separation processing of the timer interrupt in the prior art.

[0064]

According to the present invention, To under the guest
By occupying D, CKC, and CPT for each of the RH, RG, and IG modes, a simulation process as in the related art is not required, and the timer interrupt performance of the guest VM can be improved. Specifically, all the processing by the program shown in FIGS. 3 and 4 becomes unnecessary.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a timer mechanism according to the present invention.

FIG. 2 is a configuration diagram of a conventional timer mechanism.

FIG. 3 is a flowchart of a conventional initialization process of a timer mechanism.

FIG. 4 is a flowchart of a timer interrupt process of a conventional timer mechanism.

FIG. 5 is a processing flowchart in a case where a guest timer mechanism is initialized when switching from a host to a guest according to the present invention.

FIG. 6 is a flowchart illustrating an example of an interrupt process according to the present invention;

[Explanation of symbols]

101: real computer (CU), 102: time of day clock (ToD), 103: adder (ADD), 1
04 · 106 · 108: Clock comparator (CK
C), 105, 107, 109 ... comparator (CoMP),
110, 112, 114 ... CPU timer (CPT), 1
11.113.115... Subtractor (SUB).

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Katsumi Hayashida 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside Nichi Information Technology Co., Ltd. F-term (reference) 5B098 BA04 FF04 HH01

Claims (4)

[Claims] 1. A timekeeping method in a virtual machine system in which a plurality of virtual machines (hereinafter, referred to as guests) operate on a real machine under control of a virtual machine control program (hereinafter, referred to as a host). A clock mechanism, a timed timer mechanism for detecting that a specific time of the host or guest has come by comparing the value of the clock mechanism, and a subtraction timer mechanism for measuring the elapsed time of the host or guest,
A timekeeping method for a virtual computer system, which is provided exclusively for each mode of a host and a guest. 2. A timekeeping method in a virtual machine system in which a plurality of virtual machines (hereinafter called guests) operate on a real machine under the control of a virtual machine control program (hereinafter called host), wherein the processing is performed by a host, A timekeeping method that does not require saving and restoring timer values when switching between guest modes. 3. A timekeeping method in a virtual machine system in which a plurality of virtual machines (hereinafter called guests) operate on real machines under the control of a virtual machine control program (hereinafter called host), wherein the processing is performed by a host, A timekeeping method that does not require simulation of the host timer in guest mode when switching between guest modes. 4. A timekeeping method in a virtual machine system in which a plurality of virtual machines (hereinafter called guests) operate on a real machine under the control of a virtual machine control program (hereinafter called host). A timekeeping method that allocates one clock mechanism corresponding to each mode when occupying the timer mechanism.