JP2001223608A - Digital correlation circuit and spread spectrum signal receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in the conventional digital correlation circuit where the required number of multipliers by code lengths, resulting in the increase of a scale of a gate. SOLUTION: The digital correlation circuit consists of a reference pattern storage means that stores reference patterns, whose code length is N (e.g. '64') and whose chip value is given as +1 or -1, a multiplier (one multiplier, regardless of the code length N) that multiplies -1 with each value of a digital input from an input terminal, N-sets of selectors selects the digital input itself received from the input terminal (equivalent to the digital input multiplied with +1) or the digital input multiplied with -1 by the multiplier and outputs the selected input, and N-sets of addition register means that respectively correspond to N-sets of the selectors, in the 1st stage of which the corresponding output of the multiplier can be stored temporarily and in the 2nd and succeeding stages, of which the output of the corresponding selector and the output of the pre-stage are summed, and the sum is stored.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum signal receiving apparatus suitable for receiving a spread spectrum signal. The present invention also relates to a digital correlation circuit suitable for use in synchronization processing (synchronization acquisition (establishment) and synchronization tracking) of a spread spectrum system.

[0002]

2. Description of the Related Art Here, a spread spectrum communication system which is a typical example of a spread spectrum system will be described. In a spread spectrum communication system, in order to reproduce original data from a chip value spread using a spreading code, a process of obtaining a correlation between the spreading code and the spread chip value is performed on the receiving device side.

Conventionally, there is a digital correlation circuit having the configuration shown in FIG. 2 used for such correlation processing. FIG.
The digital correlation circuit shown in FIG. 7 shows an example in which the spreading code length is "64". In FIG. 2, reference numeral 100 denotes an input terminal of a digital input D, 200 denotes a spread code memory storing 64 chip values, 301 to 364 denote multipliers,
Reference numerals 401 to 464 denote registers, and reference numerals 502 to 564 denote adders.

[0004] The digital correlation circuit having this configuration operates as follows. First, in each of the multipliers 301 to 364, the product of the chip value input from the input terminal 100 and all chip values of the spreading code held in the spreading code memory 200 is obtained. Next, each of the product outputs and the registers 401 to
The sum with the output of the register 463 is obtained, and the sum is stored in the registers 402 to 464 located at the next stages.

However, the product of the chip value P0 corresponding to the head (first stage) of the spread code and the input chip value is stored in the first (first stage) register 401 as it is. Further, the value stored in the register 464 at the last stage is output as the calculated correlation value S0.

As described above, in the digital correlation circuit shown in FIG. 2, the processing for adding the result of the product operation of all the chip values of the spreading code and the input is executed in parallel, so that the chip sequence for which the correlation characteristic is to be obtained is obtained. Since the last chip is input, a correlation value can be obtained only by calculating one product and one sum.

[0007]

However, in the digital correlation circuit having such a configuration, a multiplier having a spreading code length minus one is required (that is, as shown in FIG. 2, the spreading code length is "64"). In the digital correlation circuit
63 multipliers are required), and the gate size must be large. This characteristic can lead to an increase in the number of terminals that can be accommodated in the communication area and to adopt a spread code with a longer code length, which leads to an increase in the size of the terminal device and an increase in power consumption. The development of a correlation circuit is desired.

The present invention has been made in view of the above-mentioned problems, and proposes a digital correlation circuit that requires a smaller gate size and a shorter processing time than conventional ones, and a spectrum spreader including the digital correlation circuit. A signal receiving device is proposed.

[0009]

(A) In order to solve this problem, in the first invention (claim 1), a digital correlation circuit is provided, and (1) a code length whose chip value is given by +1 or -1. And (2) a multiplier (code length N) for multiplying each chip value of a digital input received from an input terminal by -1. And (3) each use the chip value corresponding to the reference pattern as the control signal, and the digital input itself (corresponding to a value obtained by multiplying by +1) input from the input terminal or multiplication. N selectors for selectively outputting either one of the digital inputs multiplied by -1 by the multiplier, and (4) a corresponding multiplier provided at each of the N selectors in the first stage. Temporarily store the output of After the stage, the output of the corresponding selector and the output of the preceding stage are added and accumulated by N addition register means.

In the digital correlation circuit having this configuration, when the chip value corresponding to the reference pattern is -1, the multiplier multiplied by -1 is selected as the output of the selector, and the chip value corresponding to the reference pattern is selected. Is +1, the digital input itself received from the input terminal (+1
Multiplied by. ) Is selected as the output of the selector.

The output of each of these selectors matches the value obtained by multiplying each chip value of the digital input by each chip value of the reference pattern. Thus, in the digital correlation circuit according to the first invention, the same multiplication result as in the case of preparing N multipliers can be obtained only by preparing one multiplier regardless of the code length N. As a result, a desired correlation value can be obtained from the last stage of the addition register means after calculating one product and one sum after the last chip value of the chip sequence for which correlation is to be obtained is input. .

In a second invention (claim 2), the digital correlation circuit according to the first invention (claim 1) is used in a spread spectrum signal receiving apparatus for receiving a spread spectrum signal obtained by spread spectrum. Be prepared.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a digital correlation circuit and a spread spectrum signal receiver according to the present invention will be described.

(A) Digital Correlation Circuit (A-1) Circuit Configuration FIG. 1 shows an example of a block configuration of a digital correlation circuit according to the present embodiment. FIG. 1 shows a case where the spreading code length is “64”. This digital correlation circuit uses a 64-chip spreading code having a value of either "+1" or "-1" as a reference pattern to obtain a 64-chip time-length correlation of digital input for each chip cycle. It is.

As shown in FIG. 1, the digital correlation circuit comprises an input terminal 100, a spread code memory 200,
, One multiplier 300 and 64 registers 401 to 401
464, 63 adders 502 to 564, and 64 selectors 601 to 664.

The input terminal 100 is a terminal to which the digital input D is input in series for each chip value. The signal line extended from the input terminal 100 is divided into two at the tip end. One branch line is connected to one input of the multiplier 300, and the other branch line is connected to 64 selectors 601 to 601. 664 is connected to one input.

The spreading code memory 200 stores "+1"
Alternatively, it is storage means for storing chip values P0 to P63 having a length of 64 chips, each of which has a value of “−1”. However, in an actual circuit, the sign bits of “01” and “11” corresponding to the binary negative numbers of “+1” and “−1” are used.
t), ie use "0" and "1". The same value is used for the digital input D in an actual circuit.
That is, the code bits “0” and “1” are used.

By the way, the merit of using "0" or "1" (the merit of not using "+1" or "-1") is the case of "+1" or "-1". While a negative number expression ("01" or "11") requires 2 bits,
This is because the operation can be realized with one bit by using the sign bit “0” or “1”. For this reason, this method is not specific to the present embodiment, but is widely and generally used.

The multiplier 300 is a multiplying means for giving "-1" to the other input to which the branch line is not connected. That is, the multiplication means multiplies the digital input D by "-1". The output of the multiplier 300 is input to each of the 64 selectors 601 to 664.

The multiplier 300 is constituted by an exclusive OR gate (EX-OR gate). Therefore, when the digital input D is the sign bit “0” (when the binary negative number is “01”), the multiplier 300 outputs “1”.
(A binary negative number “11”) is output. When the digital input D is the sign bit “1” (when the binary negative number is “11”), the multiplier 300 outputs “0” (2
The output is "01" in the decimal system.

Each of the selectors 601 to 664 has "-
Selection means for inputting the digital input D multiplied by “1” and the digital input D itself (the same as multiplying by “+1”) and selectively outputting either one of them.

Here, the selectors 601 to 664 are configured to use the chip values P0 to P63 of the corresponding spreading codes as selection signals. That is, each of the selectors 601 to 664 outputs the corresponding chip value P0.
When P63 is a binary negative number expression "+1", the digital input D itself is selected, and the corresponding chip values P0 to P63 are selected.
Is set to select the output of the multiplier 300 when is a binary negative number expression “−1”. This means that the selector 60
1 to 664 means that the same result as the multiplication result of each chip value of the digital input D and each chip value of the spreading code is output.

Each of the adders 502 to 564 is an adding means for adding the output from the corresponding selector 602 to 664 and the output from the preceding register 401 to 463 to itself and outputting to the next stage. is there.

The registers 402 to 464 are storage means for storing the addition results of the adders 502 to 564 located at the preceding stage with respect to the registers. The correlation operation result is output from the register 464 located at the last stage among them. Also,
The register 401 located at the first stage is provided for storing the selection result of the selector 601.

The set of the adders 502 to 564 and the registers 402 to 464 is referred to as an addition register means in the claims.

(A-2) Correlation Calculation Operation Next, the correlation calculation operation in the digital correlation circuit having the above configuration will be described.

Assume that chip values D0, D1, D2,..., D63 of the digital input D are sequentially supplied from the digital input terminal 100. Chip value D of digital input D
0 to D63 are divided into two paths on the way, one of which is supplied in parallel to one input of a multiplier 300 and one input of selectors 601 to 664 having 64 branch lines.

The multiplier 300 sequentially multiplies each chip value of the input digital input D by "-1" (that is, "1" of the sign bit). The output of the multiplier 300 is output to the other of the two inputs provided in each of the 64 selectors 601 to 664.

Each of the selectors 601 to 664 is based on the 64 chip values P0, P1, P2,..., P63 stored in the spread code memory 200 and corresponding to itself (for example, The selector 601 selects and outputs one of the inputs based on the chip value P0 and the selector 663 based on the chip value P62).

For example, when the chip value is “0” of the sign bit
If it is (ie, “+1”), the selector selects the chip value itself of the digital input D. On the other hand, when the chip value is “1” of the sign bit (that is, “−”
1 ”), the selector selects the output of the multiplier 300, that is, the value obtained by multiplying the chip value of the digital input D by“ −1 ”.

The selected output C of these selectors 601 to 664
FIG. 3 shows the contents of 0, C1, C2,..., C63. As can be seen from FIG. 3, each of the selected outputs C0, C0
The values of 1, C2,..., C63 match the multiplication results of each chip value of the digital input D and each chip value stored in the spread code memory 200.

Although the reason is repeated, the value of the digital input D selected when the chip value of the spread code code is "+1" is obtained by multiplying the value by the chip value "+1" of the spread code code. And the multiplier 300 selected when the chip value of the spreading code is “−1”.
Is the same as multiplying the digital input D by the chip value "-1" of the spreading code.

The selection outputs C0, C1, C2,
, C63 are respectively provided with corresponding adders 502 to 56.
4 (however, the selected output C0 is output to the register 401), and is added to the values held in the registers 401 to 463 located at the preceding stages.

Thus, in the time slot in which the 64th chip value D63 is input from the digital input terminal 100, the value (the value added sequentially to the last register 464 via the registers 401 to 463 up to the previous stage ( The sum of the outputs of the selector 664 is stored in the sum. That is, the operation result S0 given as the output of the register 464 is composed of the chip values D0 to D63 of the digital input D and the spread code (chip values P0 to P6).
3).

In the same manner, the digital input terminal 10
The chip values D64, D65, D6 of the digital input D are set to 0.
Each time 6,... Are sequentially given, 64 chip values D1 to D1
Correlation result S of D64, D2 to D65, D3 to D66, ...
0 (correlation result in a 64-chip section) is output.

Thus, when the correlation result S0, which is the output of the digital correlation circuit, is monitored in time series,
A high correlation value is obtained when the chip sequence pattern of the input signal matches the pattern of the waiting spread code. However, the value obtained here is the sum of “0” and “1” of the output value of the selector, and when the pattern matches, the correlation result S0 becomes “0”. That is, in this digital correlation circuit, the correlation becomes highest when the correlation result S0 is "0".

(A-3) Effects of Embodiment As described above, according to the present embodiment, the digital input D
Is divided into two, and only one of them is multiplied by “−1”, so that the value of the digital input D as it is (in the same state as multiplied by “+1”) is multiplied by the value multiplied by “−1”. And one of them is selectively output from each selector, so that only one multiplier is prepared in the circuit, but the multiplication of the digital input and each chip value of the spreading code is performed. An output corresponding to the result can be obtained.

Thus, a further reduction in the gate size can be realized as compared with the conventional device in which a multiplier for the spreading code length must be prepared. This effect becomes more remarkable as the spreading code length increases.

Further, in the digital correlation circuit having this configuration, a desired correlation value can be obtained by one product operation and one sum operation after the last chip value of the chip sequence whose correlation is to be obtained is input. Therefore, the influence of the delay in the calculation of the correlation value can be ignored.

(B) Spread Spectrum Signal Receiving Apparatus Next, an application example of the digital correlation circuit having the above configuration will be described. Here, an example of application to a receiving apparatus (spread spectrum signal receiving apparatus) of a spread spectrum communication system will be described. Note that the communication system includes Code Division Multiple Acces (CDMA) in a mobile phone service.
s) There are communication systems, satellite communication systems, fixed communication systems and the like.

FIG. 4 shows a configuration example of a spread spectrum signal receiving apparatus. FIG. 4 shows only a main part of the receiving system in the configuration. As shown in FIG. 4, the apparatus includes an antenna 1 for receiving a spread spectrum signal, a spread spectrum demodulation circuit 2 for demodulating a received broadband signal into a narrowband information modulated wave, and information from the information modulated wave. It comprises an information demodulation circuit 3 for demodulation and a synchronization circuit 4 for establishing and following synchronization.

The digital correlation circuit is mounted on the synchronization circuit 4 among them. Thus, the gate size of the synchronous circuit 4 is smaller than that of the conventional device. As a result, restrictions on the layout are reduced, and the size and design of the entire spread spectrum signal receiver can be improved.

(C) Other Embodiments In the above-described embodiment, a case has been described in which a spread code for one transmission data is stored in the spread code memory 200. However, a spread code for a plurality of transmission data is stored. May be accumulated in a superimposed manner. In this case, the configuration similar to that of FIG. 1 corresponding to the extended portion, that is, the multiplier 300, the registers 401 to 464, and the adders 502 to 56
4. Selectors 601 to 664 may be provided accordingly.

In the above-described embodiment, an example of a spread spectrum communication system has been described as an application example of the digital correlation circuit. In addition, a spread spectrum ranging system (for example, a GPS (Global Positioning System)
m)).

[0045]

As described above, the first invention (Claim 1)
According to the above, a digital correlation circuit is composed of a reference pattern storage means for storing a reference pattern having a code length of N given a chip value of +1 or -1 and a chip value of each digital input received from an input terminal. (One irrespective of the code length N), and the corresponding chip value of the reference pattern is used for the control signal, and the digital input itself from the input terminal or the multiplier is used. N selectors for selectively outputting either one of the digital inputs multiplied by -1 are provided, and each of the N selectors is provided. In the first stage, the output of the corresponding multiplier is temporarily stored. , And in the next and subsequent stages, the output of the corresponding selector and the output of the preceding stage are added and accumulated by N number of addition register means.
The correlation value can be calculated only by the number of multipliers, and a digital correlation circuit that requires a very small gate size as compared with the related art can be realized.

According to the second invention (claim 2),
By applying the digital correlation circuit having this configuration to a spread spectrum signal receiving apparatus that receives a spread spectrum signal that has been spread spectrum, the size of the spread spectrum signal receiving apparatus can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a digital correlation circuit.

FIG. 2 is a block diagram showing a conventional configuration example of a digital correlation circuit.

FIG. 3 is a table showing a relationship between a selector output and a digital input.

FIG. 4 is a block diagram illustrating an embodiment of a spread spectrum signal receiving apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Antenna, 2 ... Spread-spectrum demodulation circuit, 3 ... Information demodulation circuit, 4 ... Synchronization circuit, 4A ... Digital correlation circuit, 100 ... Input terminal, 200 ... Spread code memory, 300, 301-364 ... Multiplier, 401 ... 464 register, 502-564 ... adder, 601-664 ... selector.

Claims (2)

[Claims] 1. A reference pattern accumulating means for accumulating a reference pattern having a code length of N given a chip value of +1 or -1 and -1 for each chip value of a digital input received from an input terminal. A multiplier for multiplying, each of which uses a corresponding chip value of the reference pattern as a control signal, and is either a digital input itself input from the input terminal or a digital input multiplied by -1 by the multiplier. N for selectively outputting one
And the N selectors are provided corresponding to each of the N selectors. The output of the corresponding multiplier is temporarily stored in the first stage, and the output of the corresponding selector and the output of the previous stage are stored in the subsequent stages. A digital correlation circuit comprising: N addition register means for adding and accumulating the sum. 2. A spread spectrum signal receiving apparatus for receiving a spread spectrum signal obtained by spreading a spectrum, the spread spectrum signal receiving apparatus comprising the digital correlation circuit according to claim 1.