JP2001217550A - Multilayer circuit board and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer circuit board advantageous for increasing the wiring density and mounting electronic components at higher densities. SOLUTION: The multilayer circuit board and semiconductor device including electronic components mounted on this circuit board are characterized as follows. A plurality of circuit boards each having conductor circuits on one or both surfaces of an insulative hard base and vias composed of a conductive substance filled in holes piercing the insulative hard base to reach the conductor circuits are laminated through adhesive layers and heated and pressed en bloc, solder bumps are formed just above the vias on the surface of the outermost conductor layer of one of the laminated circuit boards and electrically connected to these vias, and conductive pins or conductive balls are disposed just above the vias on the surface of the outermost conductor layer of the other circuit board and electrically connected to these vias.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board which is advantageous for ultra-high-density wiring, and more particularly to a single-sided circuit board having filled via holes, or a single-sided circuit board having a double-sided circuit board as a core. The present invention proposes a multilayer circuit board formed by laminating substrates, and performing heat-pressing of the laminated circuit boards together via an adhesive, and a semiconductor device using the multilayer circuit board.

[0002]

2. Description of the Related Art The outermost surface of a multilayer circuit board has L
Various electronic components such as SI chips are mounted. As a method of mounting an electronic component on such a multilayer circuit board, a component hole for inserting a terminal portion of the electronic component at a predetermined position on a conductor circuit formed on the outermost surface of the multilayer circuit board, A connection land with a diameter slightly larger than the diameter of the component hole is formed at the place surrounding the component hole,
Here, a solder paste is used to connect the lead group of the electronic component by soldering, or cream solder is applied in advance on the land formed at a predetermined position on the conductor circuit, and the terminal part of the electronic component is After mounting so as to be in contact with each other, a reflow process is performed in an atmosphere maintained within a temperature range in which the solder is melted, so that a surface mounting method in which an electronic component is connected is used.

[0003]

However, in the above-mentioned method, it is essential to provide a land having an appropriate size on the conductor circuit. However, with the recent demand for smaller and more sophisticated electronic devices, if the number of mounted electronic components is large, the total area of the lands becomes so large that it cannot be ignored. Was.

[0004] In addition, during the soldering work for connecting electronic parts, solder flows to unnecessary parts and short-circuits occur.
It is indispensable to apply a solder resist for preventing disconnection or the like from occurring in advance. For this reason, it is necessary to design with a margin between the wirings in consideration of a displacement error at the time of solder resist printing, and this also has been a hindrance factor to the high density.

The present invention has been developed to solve the above-mentioned problems of the prior art. It is an object of the present invention to provide a multi-layer circuit board capable of high density and a semiconductor device using the same. It is to propose.

[0006]

Means for Solving the Problems The inventors of the present invention have intensively studied for realizing the above-mentioned object, and as a result, have arrived at an invention having the following content as a gist configuration. That is, (1) The multilayer circuit board of the present invention has a conductive circuit on one or both surfaces of an insulating hard base material, and an opening reaching the conductive circuit through the insulating hard base material is filled with a conductive substance. In a multilayer circuit board formed by laminating a plurality of circuit boards having via holes formed through an adhesive layer and performing heat pressing collectively, of the plurality of laminated circuit boards, On the surface of the one circuit board located outside, a conductive bump is formed, which is located immediately above the via hole and is electrically connected to the via hole,
Further, a conductive pin or a conductive ball, which is located immediately above the via hole and electrically connected to the via hole, is disposed on the surface of the other outermost circuit board. And

(2) The multilayer circuit board of the present invention has a conductor circuit on one surface of an insulating hard base material, and a conductive material penetrates the insulating hard base material to reach the conductor circuit. A single-sided circuit board having a plurality of single-sided circuit boards having via holes filled with a conductor circuit and a conductor circuit on one side of an insulative hard substrate, and having an opening reaching the conductor circuit through the insulative hard substrate. In a multilayer circuit board formed by laminating a substrate and an adhesive layer, respectively, and performing heat pressing collectively, one of the plurality of laminated circuit boards, which is the outermost circuit board, A conductive bump is formed on the surface of the circuit board directly above the via hole and electrically connected to the via hole, and a conductive circuit of the circuit board is formed in an opening of the other circuit board located on the outermost side. Electrical Wherein the conductive pins or conductive balls that are connected is provided.

Each of the circuit boards constituting the multilayer circuit board according to the above (1) and (2) is electrically connected to the via hole corresponding to the position of the via hole, and has a projection shape projecting from the surface of the circuit board. It is desirable that a conductor is formed.

The conductive material filled in the via hole of each circuit board constituting the multilayer circuit board of the above (1) and (2) is preferably metal plating by electrolytic plating.

Further, in the multi-layer circuit boards (1) and (2), the distance between adjacent via holes formed in each of the stacked circuit boards is from the one circuit board to the other circuit board. It is desirable that the film be formed so as to increase in size.

(3) A semiconductor device according to the present invention is a multilayer circuit board according to any one of claims 1 to 9, and a conductive bump formed on one of the outermost circuit boards of the multilayer circuit board. And an electronic component electrically connected to the electronic component.

A stiffener is arranged at a peripheral portion of the circuit board on which the electronic component is mounted, and a via hole formed in the outermost circuit board facing the circuit board, a position facing the electronic component mounting position. It is desirable that the chip capacitor be electrically connected to the via hole in the above.

(4) The semiconductor device of the present invention has a conductor circuit on one or both sides of an insulating hard base material, and an electrolytic plating is performed on an opening penetrating the insulating hard base material and reaching the conductor circuit. And a plurality of circuit boards each having a protruding conductor electrically connected to the via hole corresponding to the position of the via hole and laminated via an adhesive layer. A semiconductor device comprising a multilayer circuit board formed by heat-pressing all together and an electronic component such as an LSI chip electrically connected to a circuit board located on the outermost side of the multilayer circuit board A conductive bump positioned directly above the via hole and electrically connected to the via hole, is formed on the surface of the one outermost circuit board; The electronic component is electrically connected to the electronic component, and the surface of the outermost circuit board located on the opposite side to the circuit board on which the electronic component is mounted has a chip with respect to a via hole immediately below the electronic component. The capacitor is electrically connected.

In the above-mentioned semiconductor device, it is desirable that a stiffener for preventing warpage of the circuit board is bonded and fixed to a peripheral portion of the circuit board on which the electronic components are mounted.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention has a conductor circuit on one or both sides of an insulating hard substrate, and an opening penetrating the insulating hard substrate and reaching the conductor circuit is filled with a conductive substance. As a structural unit, a circuit board having a via hole consisting of, appropriately combining a plurality of these, or if necessary, in addition to these single-sided or double-sided circuit board,
Combine with a circuit board that has via holes filled with a conductive substance in the opening but does not have a conductive circuit, and after laminating via an adhesive layer, heat-press collectively to form a multilayer circuit board package That is, it is used as a substrate.

That is, the outermost one of the plurality of laminated and collectively press-molded circuit boards has a surface located just above the via hole to be connected to a connection terminal of an electronic component. A conductive bump electrically connected to the via hole is formed, and on the surface of the other outermost circuit board, a conductive bump is provided directly above the via hole so as to be connected to the connection hole or the connection pad on the motherboard. And a conductive pin or a conductive ball electrically connected to the via hole.

In the case where the above-mentioned multilayer board is formed using, for example, four single-sided circuit boards A to D, for example, as shown in FIG. The conductor circuit is exposed, and the outermost circuit board D has a structure in which a protruding conductor connected to the via hole is exposed on the surface of the other outermost circuit board D. Further, as shown in FIG. On the surfaces of the substrates A and D, the conductor circuits are exposed.

When the multilayer circuit board is configured using three single-sided circuit boards A, B, and C and one double-sided circuit board E, for example, as shown in FIG. Each of the circuit boards A and C located outside has a structure in which a conductor circuit is exposed.

Further, when the above-mentioned multilayer circuit board is configured using three single-sided circuit boards A, B, and C and a single circuit board F having no conductor circuit, for example, FIG.
As shown in (1), on the surfaces of the outermost circuit boards A and F, the protruding conductors connected to the via holes are respectively exposed.

Although a multilayer circuit board can be constructed other than the above combinations, the portion of the outermost circuit board located directly above the via hole of the conductor circuit is formed on a conductor pad and the outermost circuit board is formed on the outermost circuit board. The protruding conductor of the circuit board has its exposed portion melted during hot pressing to form a substantially circular conductor pad on the surface of the insulating base material.

According to the combination shown in FIG. 1, an LSI is formed on a conductor circuit exposed on the surface of the uppermost circuit board.
In order to be connected to electronic components including semiconductor chips such as
A solder bump is formed by supplying an appropriate solder body, and a conductor pad formed by a protruding conductor at a via hole position of a lowermost circuit board is connected to a connection hole or a connection pad on a motherboard. Therefore, it is preferable that a T-shaped pin or a solder ball is connected.

Further, by supplying an appropriate solder body onto the conductor circuit exposed on the surface of the uppermost circuit board, a T-shaped pin or a solder ball is connected, and a projection is formed at a via hole position of the lowermost circuit board. A solder bump may be formed on a conductor pad formed by the conductor.

In any of the combinations, the solder bump is formed by a conductor formed by a protruding conductor on a conductor pad formed on a part of a conductor circuit of one of the outermost circuit boards or on a via hole. The T-pin or solder ball formed on the pad
It is arranged on the conductor pad formed by the protruding conductor immediately above the via hole exposed on the surface of the other outermost circuit board or on the conductor pad formed in a part of the conductor circuit.

According to such a configuration, the filled via holes are provided at high density in the multilayer circuit board, and the via holes of the densified via holes are exposed immediately above the via holes exposed on the surface of the outermost circuit board. Since the conductive bumps, the conductive pins or the conductive balls are disposed, the wiring layer in the multilayer circuit board is formed through the conductive bumps, the conductive pins or the conductive balls, LSI
It is connected to an electronic component including a semiconductor chip such as the above or a motherboard with the shortest wiring length, thereby enabling high-density wiring.

Further, since a single-sided or double-sided circuit board is formed of the same material and the two layers are laminated, cracks and peeling at the interface originating from thermal expansion hardly occur.
Therefore, the reliability for the temperature cycle test is also improved. In addition, when a multilayer circuit board is configured using only a single-sided circuit board, warpage hardly occurs regardless of whether or not wiring is formed.

Further, the conductive bumps, the conductive pins and the conductive balls are formed immediately above the via holes exposed on the surface of the circuit board located on the outermost side of the multilayer circuit board. There is no need to form a solder resist layer. This is because the insulating layer on the outermost circuit board functions as a solder resist.

In addition, the multilayer circuit board of the present invention is arranged such that a surface of one of the outermost circuit boards among a plurality of stacked circuit boards is located immediately above a via hole and electrically connected to the via hole. A conductive bump to be connected is formed,
Another feature is that a conductive pin or a conductive ball electrically connected to the conductive circuit is provided in the opening of the other circuit board located at the outermost side.

According to such a configuration, one of the outermost circuit boards of the stacked single-sided circuit boards functions as a reinforcing plate having no filled via hole (because the via hole is a via land in the inner layer). (Because it is smaller than that, the state at the time of via formation is that the insulating layer of the outermost circuit board is pressing around the via land)
In addition, since a conductive pin or a conductive ball is provided in an opening provided in such a circuit board so as to be electrically connected to a conductive circuit, a solder resist layer is not required.

A semiconductor device according to the present invention includes the above-mentioned multilayer circuit board and electronic components such as an LSI chip electrically connected to conductive bumps formed on the outermost circuit board. And According to such a configuration,
Since the flatness of the bump is maintained, there is an effect that there is no disconnection with the electronic component.

In the above-described semiconductor device, the stiffener is disposed on the periphery of the circuit board on which the electronic component is mounted, and the stiffener is disposed on the outermost circuit board facing the circuit board on which the electronic component is mounted. It is desirable that a chip capacitor be directly connected to a via hole located at a position facing the electronic component mounting position among the formed via holes. According to such a configuration, the distance between the electronic component such as the LSI chip and the chip capacitor can be minimized, and the loop inductance between the two can be reduced.

Further, the semiconductor device of the present invention comprises a multilayer circuit board having a filled via hole formed by electrolytic plating;
An electronic component such as an LSI chip electrically connected to the outermost circuit board of the multilayer circuit board, and the surface of the outermost one circuit board is provided directly above the via hole. And a conductive bump electrically connected to the via hole is formed,
An electronic component is electrically connected to the conductive bump via a solder ball, and the electronic component is mounted on a surface of an outermost circuit board on a side opposite to a circuit board on which the electronic component is mounted. The chip capacitor is electrically connected to the via hole immediately below. According to such a configuration, the distance between the electronic component such as an LSI and the chip capacitor can be minimized, and the loop inductance between the two can be reduced.

In the above-described semiconductor device, a stiffener for preventing warpage of the entire substrate due to a difference in coefficient of thermal expansion of each material constituting the circuit board is provided on a peripheral portion of the circuit board on which electronic components are mounted. Is desirably adhered and fixed. This stiffener is, for example, BT, FR
4, it is preferably formed of a glass-resin composite material such as FR5 or a metal material such as copper, and is disposed so as to surround the electronic component mounted on the circuit board.

The insulating base material used in the multilayer circuit board and the semiconductor device according to the present invention as described above is not a semi-cured prepreg but a hard insulating base material formed of a completely cured resin material. When such a material is used, when the copper foil is pressed on the insulating base material by a hot press, the final thickness of the insulating base material does not fluctuate due to the pressing pressure, so that the position of the via hole can be reduced. The via land diameter can be reduced by minimizing the deviation. Therefore, the wiring pitch can be reduced and the wiring density can be improved. In addition, since the thickness of the base material can be kept substantially constant, when the opening for forming the filled via hole is formed by laser processing, the setting of the laser irradiation condition becomes easy.

Examples of such insulating resin base materials include glass cloth epoxy resin base material, glass cloth bismaleimide triazine resin base material, glass cloth polyphenylene ether resin base material, aramid nonwoven fabric-epoxy resin base material, and aramid nonwoven fabric-polyimide. It is preferable to use a hard base material selected from resin base materials, and a glass cloth epoxy resin base material is most preferable.

Further, the thickness of the insulating substrate is 20 to 6
00 μm is desirable. The reason is to ensure insulation. If the thickness is less than 20 μm, the strength is reduced and handling becomes difficult, and the reliability with respect to electrical insulation is reduced. If the thickness is more than 600 μm, it becomes difficult to form a fine via hole forming opening and the substrate itself Is to be thick.

A via hole forming opening formed on a glass epoxy substrate having a thickness in the above range has a pulse energy of 0.5 to 100 mJ and a pulse width of 1 to 100 μJ.
s, pulse interval 0.5 ms or more, number of shots 3-5
It is preferably formed by a carbon dioxide laser irradiated under the condition of 0, and its opening diameter is desirably in the range of 50 to 250 μm. The reason is that if it is less than 50 μm, it is difficult to fill the opening with a conductive substance and the connection reliability is lowered. If it exceeds 250 μm, it is difficult to increase the density.

Before the opening is formed by the carbon dioxide gas laser, a resin film is preferably adhered to the surface of the insulating substrate opposite to the surface on which the conductor circuit is formed, and laser irradiation is preferably performed on the resin film.

The resin film functions as a protective mask when the inside of the opening for forming the via hole is desmeared, and the opening after the desmearing treatment is filled with metal plating by electrolytic plating. It functions as a printing mask for forming the protruding conductor directly on the layer.

In the resin film, for example, the thickness of the pressure-sensitive adhesive layer is 1 to 20 μm, and the thickness of the film itself is 1 to 20 μm.
It is preferably formed from a PET film of 0 to 50 μm. The reason is that the height of the protruding conductor described later is determined depending on the thickness of the PET film. Therefore, when the thickness is less than 10 μm, the protruding conductor is too low, and connection failure is likely to occur. This is because, if the thickness is too large, the protruding conductor spreads too much at the connection interface, so that a fine pattern cannot be formed.

As the conductive substance filled in the opening penetrating the insulating base material, a conductive paste or metal plating formed by electrolytic plating is preferable. In order to simplify the filling process, reduce the manufacturing cost, and improve the yield, filling with a conductive paste is suitable, but in terms of connection reliability, metal plating formed by electrolytic plating, for example, Tin, silver, solder,
Metal plating such as copper / tin and copper / silver is preferred.
Electrolytic copper plating is optimal.

The opening filled with the conductive material forms a via hole for electrically connecting the conductor circuits formed on the insulating base material. The multilayer circuit board according to the present invention and the semiconductor using the same are provided. In the device, the via hole formed on each circuit board to be laminated is such that the distance between the adjacent via holes is the smallest for the outermost circuit board on the side where electronic components such as LSI chips are mounted, and the distance to the motherboard The outermost other circuit board on the side to be connected is formed to be the largest,
That is, the arrangement density of via holes formed in each circuit board to be laminated is formed so as to decrease from the circuit board on which electronic components such as LSI chips are mounted to the circuit board connected to the motherboard. Preferably, according to such a configuration, the routing of the wiring is improved.

The conductor circuit formed on one or both sides of the insulating base material is obtained by hot pressing a copper foil having a thickness of 5 to 18 μm through a resin adhesive layer maintained in a semi-cured state. It is preferably formed by performing an appropriate etching process. Such a heat press is performed under an appropriate temperature and pressure, more preferably, under a reduced pressure, and by curing only the semi-cured resin adhesive layer, the copper foil is insulated. Since it can be firmly adhered to the substrate, the manufacturing time is shortened as compared with a circuit board using a conventional prepreg.

A circuit board in which such a conductor circuit is formed on both sides of an insulating substrate can be used as a core of a multilayer circuit board. Via land (pad) as part
It is preferable that the diameter is formed in the range of 50 to 250 μm.

A single-sided circuit board in which a conductor circuit is formed on one side of an insulating base material is used not only as a circuit board to be laminated with a double-sided circuit board but also as a multilayer by laminating only a single-sided circuit board. A modified substrate can also be formed. In such a single-sided circuit board, it is preferable that the projecting conductor is formed directly above the filled via hole.

The projecting conductor is preferably formed of a conductive paste or a low-melting-point metal. In the step of laminating the respective circuit boards and heat-pressing them collectively, the conductive paste or the low-melting-point metal is heated. Since it is deformed, it is possible to absorb a variation in the height of the conductive material or the metal plating layer filled in the via hole, thereby preventing a connection failure and obtaining a multilayer circuit board excellent in connection reliability. be able to. The protruding conductor may be formed of the same material as the conductive material filled in the via hole, for example, the conductive paste, and may be formed by the same filling process.

Of the outermost circuit boards of the multilayer circuit board formed by the above-mentioned laminating and heating press, L
The conductive bump formed on the surface of the circuit board on the side on which the electronic component such as the SI chip is mounted and located directly above the via hole is formed, for example, in a dot matrix shape or a slightly shifted matrix shape. .

Further, of the outermost circuit board, a conductive pin or a conductive ball formed on the surface of another circuit board on the side connected to the motherboard, which is formed immediately above the via hole. Are formed, for example, in the form of a dot matrix or a matrix slightly shifted therefrom, like the conductive bumps described above.

Hereinafter, a method of manufacturing a multilayer circuit board and a semiconductor device using the same according to the present invention will be specifically described with reference to the accompanying drawings. (A) Formation of Laminating Circuit Board (1) In manufacturing a multilayer circuit board according to the present invention, a basic circuit board constituting the multilayer circuit board has a copper foil 12 adhered to one surface of an insulating base material 10. Used as starting material.

The insulating base material 10 is, for example, a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramid nonwoven fabric-epoxy resin base material, an aramid nonwoven fabric-polyimide resin. A hard laminated substrate selected from substrates can be used, but a glass cloth epoxy resin substrate is most preferred.

The thickness of the insulating substrate 10 is 20 to 60
0 μm is desirable. The reason for this is that if the thickness is less than 20 μm, the strength is reduced and handling becomes difficult, and the reliability with respect to electrical insulation is reduced. If the thickness exceeds 600 μm, fine via holes are formed and the conductive paste is filled. And the thickness of the substrate itself is increased.

The thickness of the copper foil 12 is preferably 5 to 18 μm. The reason is that, when forming an opening for forming a via hole in an insulating base material by using laser processing as described later, if it is too thin, it penetrates. This is because it is difficult to form a conductor circuit pattern having a large line width.

The insulating base material 10 and the copper foil 12 are preferably made of a glass cloth impregnated with an epoxy resin.
It is preferable to use a single-sided copper-clad laminate obtained by laminating a prepreg as a stage and a copper foil and pressing the laminate under heat. The reason is that the positions of the wiring patterns and the via holes do not shift during handling after the copper foil 12 is etched as described later, and the positional accuracy is excellent.

(2) Next, when manufacturing a circuit board having conductor circuits formed on both surfaces, such an insulating substrate 1
The protective film 14 is attached to the surface opposite to the surface to which the copper foil 12 of No. 0 is attached (see FIG. 6A).

The protective film 14 is used as a mask for printing a conductive paste for forming a protruding conductor to be described later. For example, a polyethylene terephthalate (PET) film having an adhesive layer on the surface can be used. The PET film 14 has a pressure-sensitive adhesive layer having a thickness of 1 to 20 μm.
m, a film having a thickness of 10 to 50 μm is used.

(3) Then, a carbon dioxide laser is irradiated from above the PET film 14 attached to the insulating substrate 10 to penetrate the PET film 14 and
An opening 16 reaching the copper foil 12 (or the conductive circuit pattern) from the surface of No. 0 is formed (see FIG. 6B). This laser processing is performed by a pulse oscillation type carbon dioxide laser processing apparatus.
It is preferable that the pulse width is 5 to 100 mJ, the pulse width is 1 to 100 μs, the pulse interval is 0.5 ms or more, and the number of shots is 3 to 50. The via diameter that can be formed under such processing conditions is desirably 50 to 250 μm.

(4) Opening 1 formed in step (3)
In order to remove the resin residue remaining on the side and bottom surfaces of No. 6, desmear treatment is performed. This desmear treatment is performed by oxygen plasma discharge treatment, corona discharge treatment, ultraviolet laser treatment, excimer laser treatment, or the like. In particular, desmearing by irradiating the opening with an ultraviolet laser or an excimer laser is desirable from the viewpoint of ensuring connection reliability.

When the desmear treatment is performed by, for example, ultraviolet laser irradiation using the third harmonic of YAG, the laser irradiation conditions are as follows: a transmission frequency of 3 to 15 KHz, a pulse energy of 0.1 to 5 mJ, and a shot number of 10 ~ 3
A range of 0 is desirable.

(5) Next, the desmeared substrate is
Then, the copper foil 12 is used as a plating lead under the following conditions.
Electrolytic copper plating treatment, and electrolytic copper plating
To form a filled via hole 20 (see FIG.
6 (c)). By this plating process, the opening 16
Small gap for filling the conductive paste 22 described later in the part
The electrolytic copper plating 18 is filled with a space left. [Aqueous electrolytic copper plating solution] Copper sulfate pentahydrate: 65 g / l Leveling agent (manufactured by Atotech, HL): 20 ml / l Sulfuric acid: 220 g / l Brightener (manufactured by Atotech, UV): 0.5 ml / l chloride ion : 40 ppm [Electroplating conditions] Bubbling: 3.0 L / min Current density: 0.5 A / dm²  Set current value: 0.18 A Plating time: 130 minutes

(6) With respect to the gap or dent of the opening 18 where the electrolytic copper plating 20 was not filled in the above (5),
The conductive film 22 is filled with the conductive paste 22 using the protective film 14 as a printing mask, and a conductor portion 24 (hereinafter, referred to as a “projecting conductor”) protruding from the surface of the insulating substrate 10 by an amount corresponding to the thickness of the protective film 14 is formed. It is formed (see FIG. 6D).

(7) Next, an adhesive layer 26 is formed on the surface of the insulating substrate 10 including the protruding conductors 24 (FIG. 6).
(E)). The adhesive 26 is an adhesive in a semi-cured state, that is, a B-stage adhesive, for bonding a copper foil on which a conductor circuit pattern is to be formed.
Epoxy resin varnish is used and its layer thickness is 10-50
The range of μm is preferred.

(8) A copper foil 28 is pressed on the surface of the insulating substrate 10 provided with the adhesive layer 26 in the step (7) by a hot press to cure the adhesive layer 26 (FIG. 6). (f)
reference). At this time, the copper foil 28 is adhered to the insulating base material 10 via the cured adhesive layer 26, and the protruding conductor 24 and the copper foil 28 are electrically connected. The thickness of this copper foil 28 is
5 to 18 μm is desirable.

(9) Next, an etching protection film is stuck on each of the copper foils 12 and 28 stuck on both sides of the insulating base material 10, and is covered with a mask having a predetermined circuit pattern. Go, conductor circuit 3
0 and 32 (including via lands) are formed (FIG. 6).
(g)).

In this processing step, first, the copper foil 12
And after applying a photosensitive dry film resist on the surface of 28 and exposing and developing along a predetermined circuit pattern to form an etching resist, etching the metal layer of the etching resist non-formed portion, including via lands The conductor circuit patterns 30 and 32 are formed. As the etchant, at least one selected from aqueous solutions of sulfuric acid and hydrogen peroxide, persulfate, cupric chloride, and ferric chloride.
An aqueous solution of the seed is desirable.

As a pretreatment for forming the conductor circuits 30 and 32 by etching the copper foils 12 and 28, in order to easily form a fine pattern, the entire surface of the copper foil is previously etched to a thickness of 1 to 10 to facilitate formation of a fine pattern. The thickness can be reduced to 10 μm, more preferably to about 2 to 8 μm. The via land as a part of the conductor circuit has an inner diameter substantially similar to the via hole diameter, but has an outer diameter of 50.
It is preferable that the film is formed in a range of about 250 μm.

(10) Next, the surfaces of the conductor circuits 30 and 32 formed in the step (8) are subjected to a roughening treatment as required (the indication of a roughened layer is omitted), and the double-sided circuit board is omitted. 34
To form This roughening treatment is for improving adhesion to the adhesive layer and preventing peeling (delamination) when forming a multilayer. As a roughening method, for example, a soft etching process, a blackening (oxidation) -reduction process, a copper-
There are the formation of a needle-like alloy plating made of nickel-phosphorus (manufactured by Ebara Uzilite; trade name: Interplate), and the surface roughening by an etching solution called “Mech Etch Bond” manufactured by Mec.

In this embodiment, the roughened layer is preferably formed by using an etching solution.
For example, it can be formed by etching the surface of a conductor circuit from a mixed aqueous solution of a cupric complex and an organic acid using an etchant. Such an etchant can dissolve the copper conductor circuit pattern under oxygen-existing conditions such as spraying and bubbling, and the reaction is presumed to proceed as follows. Cu + Cu (II) A _n → 2Cu (I) _{An / 2} 2Cu (I) _{An / 2} + n / 4O ₂ + nAH (aeration) → 2Cu (II) A _n + n / 2H ₂ O In the formula, A is a complex. Agent (acting as a chelating agent), n represents the coordination number.

As shown in the above formula, the generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to copper oxidation. The cupric complex used in the present invention is preferably a cupric complex of azoles.
The etching solution comprising the organic acid-cupric complex can be prepared by dissolving a cupric complex of an azole and an organic acid (halogen ion as required) in water. Such an etchant is, for example, imidazole copper
(II) It is formed from an aqueous solution in which 10 parts by weight of a complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride are mixed. The double-sided circuit board constituting the multilayer circuit board according to the present invention is manufactured according to the above-mentioned steps (1) to (10).

(11) Next, when manufacturing a single-sided circuit board laminated on the front and back surfaces of such a double-sided circuit board, first, the copper foil 12 adhered to one side of the insulating base material 10 is placed on the copper foil 12. After attaching an etching protection film and covering it with a mask having a predetermined circuit pattern, an etching process is performed to form a conductor circuit 40 (including a via land) (see FIG. 7B). In this processing step, first, after a photosensitive dry film resist is attached to the surface of the copper foil 12, exposure and development are performed along a predetermined circuit pattern to form an etching resist, and the metal in a portion where the etching resist is not formed is formed. The layer is etched to form a conductor circuit pattern 40 including via lands.

As the etchant, at least one aqueous solution selected from aqueous solutions of sulfuric acid and hydrogen peroxide, persulfate, cupric chloride and ferric chloride is desirable. The above copper foil 1
As a pretreatment for forming the conductor circuit 40 by etching the copper foil 2, in order to easily form a fine pattern, the entire surface of the copper foil is etched in advance to reduce the thickness to 1 to 10 mm.
μm, more preferably about 2 to 8 μm.

(12) The conductor circuit 4 is provided on one side of the insulating base material 10.
After forming 0, the process according to the above steps (2) to (6) is performed, and then the PET film 14 is peeled off from the surface of the insulating substrate 10 (FIGS. 7C to 7E). )
reference).

The protruding height of the projecting conductor 44 formed in accordance with the step (6) from the surface of the insulating base material 10 (indicated by reference numeral 44 to distinguish it from the projecting conductor 24 of the double-sided circuit board) is as follows. Approximately equal to the thickness of the protective film 14,
A range of 5 to 30 μm is desirable. The reason is that if it is less than 5 μm, poor connection is likely to occur, and if it exceeds 30 μm, the resistance value becomes high, and when the protruding conductor 24 is thermally deformed in the heating press step, it spreads too much along the surface of the insulating substrate. Therefore, a fine pattern cannot be formed.

It is desirable that the protruding conductor 44 be precured. The reason is that the protruding conductor 44 is hard even in a semi-cured state, and is capable of making electrical contact with a conductor circuit (conductor pad) of another circuit board to be laminated before the adhesive layer is softened at the stage of lamination pressing. Because it becomes. Such a projecting conductor 44 is deformed at the time of hot pressing to increase the contact area, so that the conduction resistance can be reduced and the variation in the height of the projecting conductor 44 is corrected.

(13) Next, a resin adhesive 46 is applied to the surface of the insulating substrate 10 including the protruding conductors 44 (FIG. 7).
(f)). Such a resin adhesive is applied to, for example, the entire surface of the insulating substrate 10 including the projecting conductors 44 or the surface not including the projecting conductors 44, and is formed of an uncured resin in a dried state. It is formed as an agent layer. This adhesive layer is preferably precured for easy handling, and its thickness is preferably in the range of 5 to 50 μm.

The adhesive layer 46 is preferably made of an organic adhesive. Examples of the organic adhesive include epoxy resin, polyimide resin, thermosetting polyphenolene ether (PPE), and epoxy resin and thermoplastic resin. Composite resin, epoxy resin and silicone resin, BT
Desirably, the resin is at least one resin selected from resins. As a method of applying the uncured resin which is an organic adhesive, a curtain coater, a spin coater, a roll coater, a spray coat, a screen printing, or the like can be used. Further, the formation of the adhesive layer can also be performed by laminating an adhesive sheet.

The single-sided circuit board 50 is made of the insulating base material 10.
Has a conductive circuit 40 on one surface and a projecting conductor 4 formed by exposing a part of the conductive paste on the other surface.
Insulating base material 1 having a protrusion 4 and further including a projecting conductor 44
0 is formed with an adhesive layer 46 on its surface, and a plurality of these layers are laminated and adhered to each other, or laminated and adhered to a double-sided circuit board 34 manufactured in advance to form a multilayer substrate 60. The resin adhesive 46 is preferably used in such a lamination stage.

(B) Multilayering of Laminating Circuit Boards Three single-sided circuit boards 50, 52 and 54 are laminated on both sides of a double-sided circuit board 34 manufactured according to each of the processing steps (A). The four-layer substrate has a heating temperature of 150
Under conditions of ~ 200 ° C and pressure of 1M ~ 4MPa, 1
The multi-layer substrate 60 is formed by a single press molding (see FIG. 8). Under the above conditions, the adhesive layer 4 of each single-sided circuit board is heated by pressing and heating at the same time.
6 is hardened, and strong bonding is performed between the adjacent single-sided circuit boards. It is preferable to use a vacuum heat press as the heating press. In the embodiment described above,
Using a double-sided circuit board of one layer and a single-sided circuit board of three layers,
Although the layers are multi-layered, the invention can also be applied to multi-layers having more than five or six layers.

(C) Arrangement of conductive bumps, pins and balls Among the multilayered circuit boards formed in accordance with the respective processing steps (B), conductive bumps are formed on the outermost circuit board. And electronic components such as LSIs are directly mounted, and conductive pins or conductive balls are disposed on the other outermost circuit board to connect to connection terminals or conductive balls on the motherboard. It is configured as a package substrate that can be directly connected.

For example, a multilayer substrate 6 as shown in FIG.
Numeral 0 denotes a structure in which the conductor circuits 40 of the outermost circuit boards 50 and 54 are exposed to the outside, respectively.
An appropriate solder pad portion located directly above the via hole is provided thereon, and an appropriate solder body is supplied on these solder pad portions to form the conductive bumps 62 or the conductive pins 64.
Alternatively, the conductive balls 66 are connected.

As a solder body for forming the conductive bumps 62, tin / lead solder (melting point: 183 ° C.) or tin / silver solder (melting point: 220 ° C.) having a relatively low melting point is used.
As a solder body for connecting the conductive pins 64 and the conductive balls 66, tin / antimony solder, tin / silver solder, tin / silver / copper solder having a relatively high melting point of 230 ° C. to 270 ° C. may be used. preferable.

A four-sided circuit board 70, 72, 74 and 76 as shown in FIG.
In the case of using a multi-layer substrate 80 in which the layer substrate is integrated by a single press molding under appropriate heating and pressure conditions, one of the circuit boards 70 located on the outermost side is provided with the via hole. The protruding conductor immediately below is melted to form a substantially circular conductor pad on the surface of the insulating base material 10, and the other circuit board 76 is formed such that the portion immediately above the via hole of the conductor circuit 40 is formed on the conductor pad. Structure.

In the case of such a multi-layer board 80, the lowermost circuit board 70 has conductive pins 64 or conductive balls 66 connected to the conductive pads immediately below the via holes, and a mother board (not shown). The circuit board 76 of the uppermost layer has conductive bumps 62 formed on conductive pads formed on a part of the conductive circuit 40. Balls 84 of electronic components 82 such as LSI chips
(See FIG. 10). Also,
A semiconductor device as a whole including a multilayer substrate 80 including conductive pads, conductive pins or conductive balls, electronic components 82 mounted on the multilayer substrate 80, and a motherboard to which the multilayer substrate 80 is attached Is configured.

FIG. 11 shows that a chip capacitor 86 is connected and fixed to one of the circuit boards 70 located on the outermost side of the multi-layer board 80, and is provided along the outer peripheral edge of the other circuit board 76 to prevent warping. 14 shows another semiconductor device to which the stiffener 88 is fixed. In such a semiconductor device, the chip capacitor 86 is formed of a high dielectric material such as ceramics or barium titanate, and is electrically connected to a via hole located immediately below the mounted electronic component 82 to reduce loop inductance. Can be achieved. Further, the stiffener 88 is formed of a glass epoxy composite material such as BT, FR4, FR5, or a metal material such as copper, and prevents warping caused by a difference in the amount of thermal expansion of each material constituting the circuit board. I have.

Further, as shown in FIG. 12, one of the outermost circuit boards constituting the multi-layer board 80 has conductive bumps 62 formed on the conductor pads formed on the conductor circuit 40, and the other circuit board has the other circuit board. Substrate (here, the lowermost circuit board 7
0) has a configuration in which the electrolytic copper plating layer is not filled in the opening 16 provided in the insulating base material 10, and an appropriate solder body is applied to the conductor pad portion formed in the conductor circuit 40 exposed in the opening 16. It is also possible to adopt a structure in which the conductive pins 64 are connected to supply. Such a structure is used for the conductive pins 64.
Is surrounded by the insulating base material 10, so that it is not necessary to provide a solder resist layer again.

As shown by a broken line in FIG.
A solder resist layer 83 may be formed on the surfaces of the outermost circuit boards 70 and 76. In this case, after applying the solder resist composition and drying the coating film, a photomask film having an opening drawn thereon is placed on the coating film, exposed, and developed, whereby the conductive circuit 40 is formed. Then, an opening exposing the solder pad portion is formed, and a conductive bump 62, a conductive pin 64 or a conductive ball 66 is provided in the exposed solder pad portion.

In the above embodiment, it is preferable that a metal layer made of “nickel-gold” is formed on each solder pad portion, the nickel layer is preferably 1 μm to 7 μm, and the gold layer is preferably 0.01 μm to 0.06 μm. Is good. The reason for this is that if the nickel layer is too thick, the resistance value will increase, and if it is too thin, it will easily peel off. On the other hand, if the gold layer is too thick, the cost increases, and if it is too thin, the effect of adhering to the solder body decreases.

A solder body is supplied on a nickel-gold metal layer provided on such a solder pad portion, and a conductive bump is formed by melting and solidifying the solder body.
Alternatively, a conductive pin or a conductive ball is joined to the solder pad to form a multilayer circuit board.

As a method for supplying the solder, a solder transfer method or a printing method can be used. Here, in the solder transfer method, a solder foil is bonded to a prepreg, and the solder foil is etched leaving only a portion corresponding to an opening, thereby forming a solder pattern to form a solder carrier film. After applying the flux to the solder resist opening of the board, laminate the film so that the solder pattern contacts the pad,
This is a method of transferring by heating. On the other hand, the printing method
This is a method in which a printing mask (metal mask) having an opening provided in a portion corresponding to a pad is placed on a substrate, and a solder paste is printed and heated. Tin-silver,
Tin-indium, tin-zinc, tin-bismuth and the like can be used. Hereinafter, description will be made based on embodiments.

[0088]

EXAMPLES (Example 1) (1) First, a double-sided circuit board constituting a multi-layer circuit board is manufactured. This circuit board is made of a prepreg formed by impregnating an epoxy resin into a glass cloth into a B stage, and copper A single-sided copper-clad laminate obtained by laminating a foil and hot pressing is used as a starting material. The thickness of the insulating base material 10 is 75 μm, the thickness of the copper foil 12 is 12 μm, and the thickness of the laminate is 10 μm on the surface opposite to the copper foil forming surface.
m, and the thickness of the film itself is 12 μm.
The PET film 14 having a thickness of m is laminated.

(2) Next, carbon dioxide laser irradiation is performed from above the PET film 14 to form a via hole forming opening 16 that penetrates through the PET film 14 and the insulating base material 10 and reaches the copper foil 12. 16 was subjected to desmear treatment by ultraviolet laser irradiation. In this embodiment, an opening for forming a via hole was formed using a high-peak short-pulse oscillation type carbon dioxide laser processing machine manufactured by Mitsubishi Electric, and a 22 μm-thick PET film was laminated on the resin surface as a whole. A 75 μm thick glass cloth epoxy resin substrate is irradiated with a laser beam from the PET film side by the mask image method at a speed of 100 holes / sec.
An opening for forming a via hole of 150 μmφ was formed. The UV laser irradiation apparatus using YAG third harmonic for desmear processing uses GT605LDX manufactured by Mitsubishi Electric Corporation. The laser irradiation conditions for the desmear processing are as follows.
Transmission frequency is 5KHz, pulse energy is 0.8m
J, the number of shots was 10.

(3) The substrate subjected to the desmearing treatment is subjected to electrolytic copper plating using the copper foil 12 as a plating lead, leaving a slight gap above the opening 16 so as to leave the electrolytic solution in the opening 16. Filling with copper plating 18 and via hole 2
0 is formed.

(4) Further, using the PET film 14 as a print mask, the conductive paste 22 is filled on the copper plating layer 18 filled in the opening 16 so that the PET film 14 is almost completely removed from the surface of the insulating base material 10. The protruding conductor 24 protruding by the thickness is formed.

(5) Next, after the PET film 14 is peeled off from the surface of the insulating base material 10, an epoxy resin adhesive is applied to the entire surface of the projecting conductor 24 side, and dried at 100 ° C. for 30 minutes. As a result, an adhesive layer 26 having a thickness of 20 μm was formed.

(6) The adhesive layer 26 formed in the above (5)
On top, a copper foil 28 having a thickness of 12 μm was heated at 180 ° C.
Heating time 70 minutes, pressure 2MPa, degree of vacuum 2.5 × 10 ³
Heat press was performed under Pa conditions.

(7) Thereafter, the copper foils 12 and 28 on both sides of the substrate were subjected to an appropriate etching treatment to form conductor circuits 30 and 32 (including via lands), thereby producing a double-sided circuit board 34.

(8) Next, a single-sided circuit board for lamination is manufactured. The circuit board used was a single-sided copper-clad laminate similar to the double-sided circuit board 34 as a starting material. First, the copper foil 12 on the insulating base material 10 is subjected to an appropriate etching treatment to form a conductive circuit 40. Further, a PET film is formed on the surface of the insulating base material 10 located on the opposite side to the conductive circuit 40. 14
Was laminated.

(9) After that, the conductor circuit 40 is formed on one surface of the insulating base material 10 by performing the processing according to the above steps (2) to (5).
The opening that reaches the conductor circuit 40 from the other surface of the copper is filled with the electrolytic copper plating 18 and the electrolytic copper plating 18
A protruding conductor 44 is formed thereon, and the protruding conductor 44
Epoxy resin adhesive 4 on the surface of the insulating substrate 10 containing
6 was applied. This epoxy resin adhesive was precured to form an adhesive layer for multilayering, and three such single-sided circuit boards 50 were produced.

(10) The one double-sided circuit board 34 and the three single-sided circuit boards 50, 52 and 54 formed by the processes (1) to (9) are At 180 ° C using a vacuum hot press
By pressing the stack at a temperature of
A multilayer substrate 60 having an H structure was created (see FIG. 8).

(11) One of the outermost circuit boards constituting the multilayer circuit board 60 is one of the circuit boards 50
The melting temperature is about 230 on the conductive circuit 40 (lower substrate).
The T-pin 64 or the solder ball 66 is connected by tin / antimony solder at a temperature of ℃. Is supplied to form a solder bump 62 to produce a multilayer circuit board. Further, in a state in which the electronic component 82 is mounted on the upper circuit board of the multilayer circuit board, the electronic component 82 is placed in an atmosphere near the tin / lead solder melting point. By reflowing and melting and fixing the solder balls 84 of the electronic component 82 to the solder bumps 62, a semiconductor device including the multilayer circuit board and the electronic component was manufactured.

(Example 2) A four-layered single-sided circuit board is laminated at a predetermined position as shown in FIG. 1, and a multi-layered board is formed by batch heating and pressing. A solder bump is formed on the conductor circuit (conductor pad), and a T-pin or a solder ball is bonded to the conductor pad formed by heating and pressing the protruding conductor exposed outside the other circuit board. Other than that,
A multilayer circuit board and a semiconductor device were manufactured in the same manner as in Example 1.

(Embodiment 3) As shown in FIG. 12, one of the outermost circuit boards among the four-layer single-sided circuit boards is formed by forming conductive bumps on the conductor pads formed on the conductor circuit. Then, the other circuit board is configured so that the opening provided in the insulating base material is not filled with the electrolytic copper plating layer, and the conductor pad formed in the conductor circuit exposed in the opening has
A multilayer circuit board and a semiconductor device were manufactured in the same manner as in Example 1 except that the structure was such that the conductive pins 64 were connected by supplying a solder body.

As to the above Examples 1 to 3, the wiring length from the LSI chip to the solder bumps, BGA (ball grid array) or PGA (pin grid array), the number of lands formed, and the total land area were examined. From the wiring board, the wiring length is 8/10 to 1/2, the number of lands formed is 1.5 to 2.0 times, and the land area is 2/3 to
8/10, and high-density wiring became possible.

[0102]

As described above, according to the multilayer circuit board of the present invention, a hard insulating base material has a conductor circuit on one or both sides, and laser irradiation is performed from the surface opposite to the surface on which the conductor circuit is formed. Of the multi-layer substrate formed by laminating a plurality of circuit boards having via holes filled with a conductive substance in the fine openings formed by
One outermost circuit board has conductive bumps formed directly under the via hole, and the other circuit board has a package board with conductive pins or conductive balls placed directly under the via hole. In addition to being able to increase the density of wiring in a multi-layer substrate, conductive bumps, conductive pins or conductive balls that make electrical connections with electronic components and motherboards are arranged on the outermost surface of the multi-layer substrate at high density Therefore, high-density wiring and high-density mounting of electronic components can be achieved. In addition, since the stress is relieved, the wiring is not warped, and the flatness of the T pin and the conductive bump can be secured.

[Brief description of the drawings]

FIG. 1 is a view showing a single-layer circuit board constituting a multilayer circuit board according to the present invention in a single-layer state;

FIG. 2 is a diagram showing another laminated state of the single-sided circuit board constituting the multilayer circuit board according to the present invention.

FIG. 3 is a diagram showing another laminated state of the single-sided circuit board constituting the multilayer circuit board according to the present invention.

FIG. 4 is a diagram showing still another laminated state of the single-sided circuit board constituting the multilayer circuit board according to the present invention.

5 (a) to 5 (g) are views showing a part of a manufacturing process of a double-sided circuit board constituting a multilayer circuit board according to the present invention.

FIGS. 6A to 6F are views showing a part of a manufacturing process of a single-sided circuit board constituting the multilayer circuit board according to the present invention.

FIG. 7 is a diagram showing one embodiment of a multilayer circuit board according to the present invention.

FIG. 8 is a diagram for explaining a via hole position of a single-sided circuit board constituting the multilayer circuit board according to the present invention.

FIG. 9 is a diagram showing another embodiment of the multilayer circuit board according to the present invention.

FIG. 10 is a view showing still another embodiment of the multilayer circuit board according to the present invention.

FIG. 11 is a diagram showing another embodiment of the multilayer circuit board according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Insulating base material 12 Copper foil 14 Protective film 16 Via hole forming opening 18 Electrolytic copper plating 20 Filling via hole 22, 42 Conductive paste 24, 44 Protrusion conductor 26, 46 Resin adhesive layer 28 Copper foil 30, 32 Conductor circuit 34 Double-sided circuit board 40 Conductor circuit 50 Single-sided conductor circuit 60, 80 Multi-layered board 62 Solder bump 64 Pin 66 Solder ball 70, 72, 74, 76 Single-sided circuit board 82 Electronic components such as LSI 83 Solder resist layer 84 Solder ball 86 Chip Capacitor 88 Stiffener

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 1/11 H01L 23/12 BNF term (Reference) 5E317 AA01 AA24 BB01 BB11 CC08 CC25 CC31 CC53 CD34 CD40 GG09 GG14 5E338 AA03 BB02 BB12 BB25 BB72 BB75 CC01 CD03 CD33 EE26 5E346 AA05 AA06 AA12 AA15 AA22 AA32.

Claims (9)

[Claims] 1. A circuit having a conductive circuit on one or both sides of an insulating hard base material, and having a via hole filled with a conductive material in an opening penetrating the insulating hard base material and reaching the conductive circuit. In a multilayer circuit board formed by laminating a plurality of boards via an adhesive layer and hot-pressing all at once, one of the plurality of stacked circuit boards located at the outermost position A conductive bump is formed on the surface of the substrate and directly connected to the via hole, and is electrically connected to the via hole. And a conductive pin or a conductive ball electrically connected to the via hole. 2. A single-sided circuit having a conductor circuit on one side of an insulating hard base material and having a via hole filled with a conductive material in an opening penetrating the insulating hard base and reaching the conductor circuit. A plurality of boards and a single-sided circuit board having a conductor circuit on one side of the insulating hard base material and having an opening reaching the conductor circuit through the insulating hard base material respectively via an adhesive layer In the multilayer circuit board formed by being laminated and heat-pressed collectively, the surface of one of the outermost circuit boards among the plurality of laminated circuit boards is directly above the via hole. A conductive bump electrically connected to the via hole is formed, and a conductive bump electrically connected to a conductor circuit of the circuit board is formed in an opening of the other circuit board located on the outermost side. Pin or lead Multilayer circuit board, wherein the sex of balls are disposed. 3. A circuit board according to claim 1, wherein each of the circuit boards constituting the multilayer circuit board has a protruding conductor electrically connected to the via hole corresponding to the via hole position. 3. The multilayer circuit board according to 2. 4. The multi-layer circuit board according to claim 1, wherein the conductive material filled in the via hole of each circuit board is a metal plating layer formed by electrolytic plating. Multilayer circuit board. 5. The semiconductor device according to claim 1, wherein a distance between adjacent via holes formed in each of the circuit boards is formed to increase from the one circuit board toward the other circuit board. 2. The multilayer circuit board according to 2. 6. A multilayer circuit board according to claim 1, further comprising an electronic component electrically connected to a conductive bump formed on an outermost circuit board of the multilayer circuit board. Semiconductor device. 7. A stiffener is arranged on a peripheral portion of an outermost circuit board on which the electronic component is mounted, and a capacitor chip is provided on a surface of another outermost circuit board facing the circuit board. 7. The semiconductor device according to claim 6, wherein the semiconductor device is electrically connected. 8. An insulating hard base material having a conductor circuit on one or both surfaces thereof, an opening reaching the conductive circuit through the insulating hard base material, having a via hole filled with electrolytic plating, A plurality of circuit boards each having a projecting conductor electrically connected to the via hole corresponding to the position of the via hole are laminated via an adhesive layer, and are formed by being heat-pressed collectively. One of the outermost circuits is provided in a semiconductor device comprising a multi-layer circuit board, and an electronic component such as an LSI chip electrically connected to the outermost circuit board of the multi-layer circuit board. A conductive bump is formed on the surface of the substrate directly above the via hole and electrically connected to the via hole, and the electronic component is electrically connected to the conductive bump. A chip capacitor is electrically connected to a via hole immediately below the electronic component on a surface of an outermost circuit board located on a side opposite to the circuit board on which the electronic component is mounted. Characteristic semiconductor device. 9. The semiconductor device according to claim 8, wherein a stiffener is adhered and fixed to a peripheral portion of the circuit board on which the electronic component is mounted.