JP2001209069A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To significantly improve the opening ratio in a pixel region and to obtain a display of high luminance. SOLUTION: The semiconductor layer P-SI which constitutes a thin film transistor has such a structure that the gate line GL and the drain line DL are separately formed as upper and lower layers. The contact holes CTH-1 to-4 of the thin film transistor are arranged on or under the drain line DL. Thus, the contact holes are not formed in the pixel region, which improves the opening ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having an increased aperture ratio and improved luminance.

[0002]

2. Description of the Related Art A liquid crystal display device is widely used as a display monitor of an information processing terminal, a video display device of a television receiver, or a light valve for a projection display. This liquid crystal display device basically encloses a liquid crystal between a pair of insulating substrates (hereinafter, also simply referred to as a substrate) at least one of which is transparent, and changes the orientation direction of liquid crystal molecules constituting the liquid crystal. It displays images and videos.

A liquid crystal display device includes a liquid crystal panel and a driving circuit for driving the liquid crystal panel, and various types are known depending on the difference in the pixel formation method of the liquid crystal panel. Among them, an active matrix system in which a switching element (active element) is formed for each pixel on the inner surface of one insulating substrate that forms a liquid crystal panel and a pixel is formed by selecting the switching element is widely used.

The most popular active matrix type liquid crystal display device is a thin film transistor type liquid crystal display device using a thin film transistor (TFT) as the switching element.

Recently, a semiconductor layer using a polycrystalline silicon semiconductor (a so-called polysilicon semiconductor) has been put to practical use as a semiconductor layer which is a constituent material of circuit elements such as a thin film transistor, a driving circuit, etc. which constitute the thin film transistor type liquid crystal display device. Has been In particular, in a projection-type liquid crystal display device, it is necessary to provide a light-shielding film for covering a semiconductor layer portion in order to prevent a change in characteristics of the semiconductor layer due to irradiation with high-luminance illumination light.

FIG. 15 is a schematic cross-sectional view for explaining an example of the structure of a main part of a liquid crystal panel of a conventional liquid crystal display device using a polycrystalline silicon semiconductor. This liquid crystal panel is a liquid crystal panel as a light valve in a projection type display, and the figure shows a thin film transistor TFT portion and a capacitance Cstg portion.

In the figure, SUB1 is one substrate (thin film transistor substrate), and SUB2 is the other substrate (counter substrate). In the liquid crystal panel as a light valve of the projection display, a quartz substrate is used for the thin film transistor substrate SUB1, and a refractory metal (W, WSi
Etc.) are formed. The light-shielding film BS blocks light from entering a semiconductor layer described later.

The light-shielding film BS is covered with a first insulating layer PAS-1, and a polysilicon semiconductor layer P-SI is formed thereon. In the polysilicon semiconductor layer P-SI (hereinafter simply referred to as a semiconductor layer), a so-called channel is formed by implanting impurities.

A gate insulating layer GI is formed on the semiconductor layer P-SI.
, The gate line GL (gate electrode GT) is patterned. The gate line GL (gate electrode GT) is
With an insulating layer PAS-2.

[0010] On the second insulating layer PAS-2,
The drain electrode SD is provided via a first contact hole CTH1 and a third contact hole CTH-3 penetrating the second insulating layer PAS-2 and the gate insulating film GI, respectively.
The conductor layer forming the drain line DL and the source electrode SD1 connected to the semiconductor layer P2 is formed so as to be connected to both ends of the channel of the semiconductor layer P-SI. The drain line DL is disposed so as to shield the channel portion of the semiconductor layer of the thin film transistor TFT from light.

A third insulating layer PAS-3 is formed covering the drain line DL (drain electrode SD2) and the source electrode SD1, and the third insulating layer PAS- is formed on the third insulating layer PAS-3. Contact hole C penetrating through hole 3
Conductive layer MS connected to source electrode SD-1 at TH-2
Is formed. The conductor layer MS is also arranged so as to shield the semiconductor layer in the capacitance portion from light.

The third insulating layer OAS-3 and the conductor layer MS are made flat by coating with a flattening film (smoothing layer) OC, and the pixel electrode ITO-1 is formed thereon. This pixel electrode ITO-1 is connected to the source electrode SD1 connected to the conductor layer MS through the fourth contact hole CTH-4. The uppermost layer is coated with an orientation film ORI-1.

On the other hand, the opposing substrate SUB2 is made of a glass plate, and has an opposing electrode ITO-2 and an orientation film ORI- on its inner surface.
2 is formed.

The thin film transistor substrate SUB1 and the counter substrate SUB2 formed as described above are bonded to each alignment film side, and a liquid crystal LC is sealed in the bonding gap to form a liquid crystal panel.

FIG. 16 is a schematic plan view for explaining the main structure of the liquid crystal panel shown in FIG. 15, and the same parts as those in FIG. 14 are denoted by the same reference numerals. In the figure, the inside surrounded by two adjacent drain lines DL and two adjacent gate lines GL constitutes a unit region (one pixel), and a pixel electrode is formed in this portion. The parts shown in (A) and (B) correspond to the parts shown in pairs (A) and (B) in FIG.

As shown, a thin film transistor TFT
Each of the contact holes CTH-1 to CTH-4 protrudes into the pixel region, which hinders the improvement of the aperture ratio. For example, this liquid crystal panel is a so-called 0.9 type XGA
In this case, both the gate line interval h and the drain line interval w surrounding the pixel region are 18 μm. Since the contact hole forming portion exists in the pixel region of this size as shown in (A) and (B), the aperture ratio is 55%.
As described above, the improvement of the aperture ratio is limited by the above-described contact hole forming portion.

It is to be noted that Japanese Patent Publication No. 7-7827 and EID87-54 disclose this kind of prior art.
(P13-17).

[0018]

However, in Japanese Patent Publication No. 7-7827, the drain line or the gate line is provided as a light shielding layer in the lowermost layer.
When viewed from the channel of the semiconductor layer, the drain line and the gate line are arranged on the same side, and the contact hole portion protrudes into the pixel region.

EID87-54 (P13-17)
In the device described in (1), the drain line is provided in the lowermost layer, and a light-shielding pattern different from the drain line is provided, which limits the improvement of the aperture ratio.

As other means for increasing the light use efficiency and increasing the luminance, a method in which a microlens is provided for each pixel, or a method in which a storage capacitor portion is formed below the wiring to improve the aperture ratio Has also been proposed. However, when the former microlens is formed in a substrate, the manufacturing cost increases. In the latter structure, the contact hole in the storage capacitor portion can be placed under the wiring, but the contact hole for connection with the pixel electrode inevitably protrudes into the pixel region, which is not enough to improve the aperture ratio.

An object of the present invention is to solve the above-mentioned problems in the prior art, and to form a semiconductor layer and a drain line (drain electrode) and a source electrode, a source electrode and a pixel electrode, or a storage capacitor constituting a thin film transistor. The present invention provides a liquid crystal display device having a liquid crystal panel capable of greatly improving an aperture ratio and providing high-luminance display by positioning a contact hole for connecting conductive layers outside the pixel region for the purpose of the invention. .

[0022]

In order to achieve the above object, the present invention relates to a structure in which a gate line (gate electrode) and a drain line (drain electrode) are arranged on different layers in a semiconductor layer forming a thin film transistor. did. For example,
When a drain line is arranged below the semiconductor layer (substrate side), a gate line orthogonal to the drain line is arranged above the semiconductor layer. Conversely, when a gate line is arranged below the semiconductor layer (substrate side), a drain line orthogonal to the gate line is arranged above the semiconductor layer. Then, at least two, and preferably all, of the contact holes of the thin film transistor are arranged above or below the drain line.

As described above, since the drain line and the gate line are vertically separated when viewed from the semiconductor layer (channel), the connection destination through the two contact holes is separated into upper and lower portions, and the two contact holes are separated from the drain by the two contact holes. It does not protrude into the pixel area behind the line pattern. Therefore, the aperture ratio is significantly improved, and a liquid crystal display device having a liquid crystal panel with high luminance (high transmittance) can be obtained.

Hereinafter, typical configurations of the present invention will be described as follows. That is, (1) a liquid crystal panel in which liquid crystal is sealed between a pair of substrates;
A liquid crystal display device comprising: a driving circuit for driving the liquid crystal panel; and a drain line connected to a drain electrode of a thin film transistor on one substrate of the liquid crystal panel;
The thin film transistor is driven by a gate line formed so as to intersect with the drain line via a first insulating layer and a gate insulating film so as to become a gate electrode of the thin film transistor, and the thin film transistor formed near an intersection of the drain line and the gate line. A contact electrode connecting the drain electrode to the drain line, a contact hole connecting the drain electrode to the drain line, and a contact hole connecting the gate electrode and the source electrode to the pixel electrode. Are formed above the drain line or the gate line.

According to this structure, the contact hole required for the thin film transistor substrate can be arranged at a position hidden by the drain line or the gate line, and does not protrude into the pixel region, so that the aperture ratio is greatly improved. .

(2) A liquid crystal display device comprising: a liquid crystal panel in which liquid crystal is sealed between a pair of substrates; and a driving circuit for driving the liquid crystal panel, wherein a thin film transistor is provided on one substrate of the liquid crystal panel. A drain line connected to the drain electrode of the thin film transistor; a gate line formed to intersect with the drain line via the first insulating layer and the gate insulating film so as to be a gate electrode of the thin film transistor; A pixel electrode driven by the thin film transistor formed near the portion, the thin film transistor has a semiconductor layer, the drain electrode connected to one end of a channel formed by the semiconductor layer, and the thin film transistor above the semiconductor layer. A gate electrode formed between a gate insulating film and a second insulating layer, and a saw connected to the other end of a channel formed by the semiconductor layer; Consists of a electrode, said drain electrode and said second insulating layer gate insulating film and the first
A first contact hole penetrating through the insulating layer and the second contact hole.
And connected to one end of the channel through a second contact hole penetrating the gate insulating film, and formed so as to cover the gate line with an upper layer of the second insulating layer, The source electrode is connected to the other end of the channel through a third contact hole penetrating the second insulating layer and the gate insulating film, and a third insulating layer formed so as to cover the source electrode and the third insulating layer. 3
A fourth contact hole that penetrates through the flattening layer formed over the insulating layer to connect to the pixel electrode formed over the flattening layer, and connects the gate line on the second insulating layer. The first, second, third, and fourth contact holes are all arranged on the drain line.

With this configuration, all of the first, second, third, and fourth contact holes required for the thin film transistor substrate can be arranged at positions hidden by the drain line or the gate line. Since there is no protrusion, the aperture ratio is greatly improved.

(3) The drain line is made of a high melting point metal having a high light shielding ability. Since the drain line has a light blocking effect, it is not necessary to form the light blocking film (light blocking layer) with a separate member,
The manufacturing process is also simplified.

(4) The drain line, the drain electrode, and the source electrode are made of a high melting point metal having a high light shielding ability. With this configuration, the same effect as (3) can be obtained.

(5) The semiconductor layer is a polycrystalline silicon semiconductor. In particular, in a projection-type liquid crystal display device, the intensity of irradiation light is high, and by applying the structure of the present invention, a high-brightness image with a high aperture ratio can be displayed.

The present invention is not limited to the above configuration and the configuration of the embodiment described later, and various modifications can be made without departing from the technical idea of the present invention.

[0032]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a perspective view of an essential part for schematically explaining the general relationship between constituent layers formed on the thin film transistor substrate of the first embodiment of the liquid crystal display device according to the present invention. Also,
FIG. 2 is a plan view schematically showing a main part of a thin film transistor substrate of a first embodiment of the liquid crystal display device according to the present invention. The same reference numerals as those in FIG. 1 correspond to the same functional parts. The illustration of the thin film transistor substrate (SUB1) is omitted.

First, a plurality of drain lines DL arranged in parallel are formed on the inner surface of the thin film transistor substrate.
The drain line DL is formed by patterning a thin film of a refractory metal such as tungsten W. Therefore, this drain line DL also has a function as a light shielding layer.

On this, a polycrystalline semiconductor layer P-SI is formed at the position shown in FIG. 2 via an insulating layer (hereinafter, simply a semiconductor layer, not shown in FIG. 1). This semiconductor layer P-
A so-called channel is formed in the thin film transistor forming portion of the SI by implanting impurities.

The insulating layer has a contact hole CTH (CTH-1 in FIG. 2) on the drain line DL, and one end of the channel portion is connected to the drain line DL via a drain electrode via the contact hole CTH. .

A gate line GL is formed on the semiconductor layer P-SI via a gate insulating layer. This gate line GL
Are arranged in parallel at right angles to the drain line DL,
A pixel region is formed in a region surrounded by two gate lines GL adjacent to two drain lines L.

The gate line GL serves as a gate electrode of the thin film transistor, and the semiconductor layer P- is formed thereon via a contact hole CTH-2 (see FIG. 2) formed in the gate insulating layer.
Light-shielding portion MS connected to the drain electrode connected to SI
(Metal shield) is formed.

On the other hand, the source electrode of the thin film transistor has the same contact hole C as the contact hole CTH-2.
It is connected to the other end of the channel portion of the semiconductor layer at TH-3, and is connected to the pixel electrode ITO-1 (see FIG. 1) through a contact hole CTH-4 provided in an insulating layer formed thereon. FIG. 1 shows a state in which the pixel electrode ITO-1 is stacked, and shows only a contact hole CTH corresponding to the contact hole CTH-4. Note that Cs
tg indicates a storage capacity portion.

In this embodiment, as shown in FIG. 2, the contact holes CTH necessary for connection between the constituent electrodes of the thin film transistor and the drain line, source electrode, pixel electrode, etc.
All of -1 to 4 exist on the drain line DL. Since these contact holes CTH-1 to CTH-4 do not protrude into the pixel region, the aperture ratio is greatly improved. When applied to a liquid crystal panel having the same size as that of FIG. 15 shown in FIG. 2, it was confirmed that the aperture ratio exceeded 70% even in the simple description.

Therefore, according to this embodiment, a liquid crystal display device having a high light transmittance and capable of displaying an image with high luminance can be obtained.

FIGS. 3 to 8 are explanatory views of a manufacturing process for further explaining the structure of the first embodiment of the present invention, and are shown in plan views of essential parts. FIG. 3 shows a drain line DL first formed on a thin film transistor substrate (not shown).
Polycrystalline semiconductor layer P-SI is formed on drain line DL via an insulating layer (FIG. 4). After heat treatment for crystallization necessary for the performance of the transistor is performed, a gate line GL is formed orthogonal to the drain line DL (FIG. 5).

As shown in FIG. 6, a contact hole CTH-1 provided through the insulating layer on the drain line DL and a insulating layer and a gate insulating layer provided on the semiconductor layer P-SI are provided. A drain electrode covering the drain line, the semiconductor layer, and the gate line GL (gate electrode) is formed through the contact hole CTH-2 and a contact hole CTH similar to the contact hole CTH-2 is formed.
At -3, a source electrode connected to the semiconductor layer is formed.

On the source electrode side of the thin film transistor, the pixel electrode ITO-1 is connected to the source electrode through a contact hole CTH-4 penetrating an insulating layer formed over the source electrode (FIGS. 7 and 8).

FIG. 9 is a sectional view schematically illustrating the structure of the first embodiment of the liquid crystal display device according to the present invention.
3 shows a cross section along the line C. One substrate S of the liquid crystal panel
UB1 is a quartz substrate on which a thin film transistor T
It has a drain line DL connected to the drain electrode SD2 of the FT. Then, the gate line GL formed so as to intersect with the drain line DL via the first insulating layer PAS-1 and the gate insulating film GI to become the gate electrode GT of the thin film transistor TFT, and the intersection of the drain line DL and the gate line GL. And a pixel electrode ITO-1 driven by a thin film transistor TFT formed near the portion.

The thin film transistor TFT has a semiconductor layer P-
SI, a drain electrode SD2 connected to one end of a channel formed by the semiconductor layer P-SI, and a gate electrode GT formed between the gate insulating film GI and the second insulating layer PAS-2 above the semiconductor layer P-SI. And a source electrode SD1 connected to the other end of the channel formed by the semiconductor layer P-SI.

The drain electrode SD2 is formed of the second insulating layer PAS
-2, gate insulating film GI and first insulating layer PAS-1
Has a first contact hole CTH-1 penetrating through the
The second insulating layer PAS-2 and the second contact hole CTH-2 penetrating through the gate insulating film GI are connected to one end of the channel. The drain electrode SD2 is formed so as to cover the gate line GL on the second insulating layer PAS-2 and has a function as a shielding layer MS.

The source electrode SD1 is connected to the second insulating layer PAS-
3 and a third insulating layer PAS-3 formed to cover the source electrode SD1 while being connected to the other end of the channel of the semiconductor layer P-SI through a third contact hole CTH-3 penetrating the gate insulating film GI. This third insulating layer PA
A fourth contact hole CTH-4 penetrating through the flattening layer (smoothing layer) OC formed over S-3 is connected to the pixel electrode ITO-1 formed over the flattening layer OC and the second contact hole CTH-4. On the insulating layer PAS-2.

All of the first, second, third and fourth contact holes CTH-1 to CTH-4 are connected to the drain line DL.
Is placed on top.

The drain line DL for light shielding on the thin film transistor substrate SUB1 side and the drain electrode SD2 portion MS disposed on the gate line GL and having a light shielding function are connected not by a continuous film but by a conductive layer formed by another process. Can also.

The thin film transistor TFT is shielded from the liquid crystal layer LC side by the shielding layer MS connected to the drain electrode SD2, and shielded from the substrate SUB1 side by the drain line DL, so that the light resistance of the thin film transistor TFT can be improved.

The drain line D of the drain electrode SD2
Since the connection between L and the semiconductor layer P-SI is separated as upper and lower layers, both contact holes CTH-1 and C
TH-2 can be formed on the lowermost drain line DL, and the contact hole CTH- connecting the pixel electrode formed in the opening of the pixel region and the source electrode SD1 can be formed.
3. CTH-4 can be formed without protruding into the pixel area. In addition, a laminated portion of the semiconductor layer P-SI, the gate line GL, and the light shielding layer MS can be used to secure a capacitance value in a small area on the substrate SUB1. This capacity may be either the storage capacity Cstg or the additional capacity Cadd.

On the other hand, on the inner surface of the counter substrate SUB2, a counter electrode ITO-2 and an alignment film ORI-2 are formed, and an alignment film O formed on the uppermost layer of the thin film transistor substrate SUB1.
A liquid crystal LC is sealed in the gap facing RI-1 to form a liquid crystal panel.

As described above, according to this embodiment, the contact holes C required for the thin film transistor substrate SUB1 are formed.
Since TH-1 to TH-4 are arranged at positions hidden by the drain line DL or the gate line GL and do not protrude into the pixel region,
The aperture ratio is greatly improved, and an image with high luminance can be displayed.

FIG. 10 shows a second embodiment of the liquid crystal display device according to the present invention.
It is sectional drawing which illustrates typically the structure of an Example. In this embodiment, the drain line DL and the drain electrode SD2 are provided below the gate line GL, and the semiconductor layer P-SI below the gate line GL is directly connected as the drain electrode SD2 through the contact hole CTH-1. The light shielding film AL-S is formed alone above the GL. The light-shielding film MS is formed on the third insulating layer PAS-3, and the light-shielding film MS is formed of the gate insulating film GI, the second insulating layer PAS-2, and the third insulating layer PAS-3. Semiconductor layer P through contact hole CTH-3 provided through PAS-3
-Connected to SI. Other configurations are substantially the same as those in FIG.

According to this embodiment, the number of contact holes can be reduced, and the contact holes CTH-1, CTH-3 and CTH-4 are hidden by the drain line DL or the gate line GL as in the first embodiment. Since they are arranged at positions and do not protrude into the pixel area, the aperture ratio is greatly improved, and high-luminance image display becomes possible.

FIG. 11 shows a third embodiment of the liquid crystal display device according to the present invention.
It is sectional drawing which illustrates typically the structure of an Example. In this embodiment, the drain line DL and the drain electrode SD2 are provided below the gate line GL, and the semiconductor layer P-SI below the gate line GL is directly connected as the drain electrode SD2 through the contact hole CTH-1. CTH-
3, the light-shielding film MS is formed above the gate line GL by extending the source electrode SD1 connected to the semiconductor layer P-SI above the gate line GL. Other configurations are substantially the same as those of the second embodiment shown in FIG.

According to the present embodiment, as in the second embodiment, the number of contact holes can be reduced. Similarly to the first embodiment, the contact holes CTH-1, CTH-3 and CTH-4 are connected to the drain line DL. Alternatively, the gate line GL
Since it is arranged at a position hidden by and does not protrude into the pixel area, the aperture ratio is greatly improved, and high-luminance image display is possible.

FIG. 12 shows a fourth embodiment of the liquid crystal display device according to the present invention.
It is sectional drawing which illustrates typically the structure of an Example. In the first to third embodiments, the present invention is applied to a so-called vertical electric field (TN) liquid crystal display device that generates an electric field for controlling the molecular orientation direction of liquid crystal between a thin film transistor substrate SUB1 and a counter substrate SUB2. In this embodiment, a so-called transverse electric field is used in which a counter electrode is also formed on the thin film transistor substrate SUB1 to generate an electric field for controlling the molecular orientation direction of the liquid crystal in a direction substantially parallel to the surface of the thin film transistor substrate SUB1. The present invention is applied to a liquid crystal display device of the IPS mode (IPS mode).

As shown in FIG. 12, in the IPS type liquid crystal display device, the drain line DL, the semiconductor layer, the gate line GL, and the like are formed basically in the same layer relation as that described in FIG. . A counter electrode (common electrode) CL is formed above the gate line DL via an insulating layer. Then, a pixel electrode PX connected to a source electrode (not shown) of the thin film transistor TFT is formed in a pixel region surrounded by two adjacent drain lines DL and two adjacent gate lines GL orthogonal to the drain line DL. I have.

FIG. 13 is a schematic plan view illustrating an example of an electrode configuration near one pixel of a liquid crystal panel constituting the IPS type liquid crystal display device shown in FIG. In the drawing, for example, a contact hole or a drain electrode DL connecting the source electrode SD1 of the thin film transistor TFT connected to the pixel electrode PX formed in the pixel region and the semiconductor layer P-SI and the semiconductor layer P
The contact hole CTH4 connecting -SI is formed on the drain line DL.

According to the present embodiment, the contact hole CT
H1 to H4 are arranged at positions hidden by the drain line DL,
Since it does not protrude into the pixel area, the aperture ratio is greatly improved, and high-luminance image display becomes possible.

FIG. 14 is a plan view illustrating the overall structure of a thin film transistor substrate of a projection type liquid crystal display device as an example of a liquid crystal display device to which the present invention is applied. This liquid crystal display device employs the liquid crystal panel of the first to third embodiments of the present invention, that is, the TN mode.

In the figure, AR denotes a display area, in which a thin film transistor TFT connected to a gate line GL and a drain line DL is arranged for each pixel, and the gate line GL is connected to a vertical drive circuit V (gate line drive circuit). , Scanning drive circuit), and the drain line DL is driven by a horizontal drive circuit H (drain line drive circuit, video drive circuit).

External signals to the vertical drive circuit V and the horizontal drive circuit H are transmitted via a terminal TM. In addition,
PG indicates a precharge circuit, and COM indicates a connection terminal for supplying a voltage to a counter electrode (common electrode) formed on the counter electrode. By using the liquid crystal display device as a light valve of a projection type liquid crystal display device, it is possible to display a high-luminance image.

Further, the present invention is not limited to the projection type, but may be a direct-view type liquid crystal display device in which the semiconductor layer may be formed of not only a high-temperature and low-temperature polycrystalline silicon semiconductor but also an amorphous silicon semiconductor. Also applicable to

[0067]

As described above, according to the present invention,
A contact hole for connecting a semiconductor layer forming a thin film transistor and a drain line (drain electrode) or a source electrode, a source electrode and a pixel electrode, or a conductive layer for forming a storage capacitor is located outside a pixel region. As a result, it is possible to provide a liquid crystal display device including a liquid crystal panel having a significantly improved aperture ratio and capable of performing high-luminance display.

[Brief description of the drawings]

FIG. 1 is a perspective view schematically showing a main part of a liquid crystal display device according to a first embodiment of the present invention, schematically illustrating the relationship between constituent layers formed on a thin film transistor substrate.

FIG. 2 is a main part plan view schematically illustrating the configuration of a thin film transistor substrate of the first embodiment of the liquid crystal display device according to the present invention.

FIG. 3 is an explanatory view of a manufacturing process for further explaining the structure of the first embodiment of the present invention.

FIG. 4 is an explanatory view of the manufacturing process subsequent to FIG. 3 for further describing the structure of the first embodiment of the present invention.

FIG. 5 is an explanatory view of the manufacturing process subsequent to FIG. 4 for further describing the structure of the first embodiment of the present invention.

FIG. 6 is an explanatory view of the manufacturing process subsequent to FIG. 5 for further describing the structure of the first embodiment of the present invention.

FIG. 7 is an explanatory view of the manufacturing process subsequent to FIG. 6 for further explaining the structure of the first embodiment of the present invention.

FIG. 8 is an explanatory view of the manufacturing process subsequent to FIG. 7 for further describing the structure of the first embodiment of the present invention.

FIG. 9 is a sectional view schematically illustrating the structure of a first embodiment of the liquid crystal display device according to the present invention.

FIG. 10 is a cross-sectional view schematically illustrating a structure of a second embodiment of the liquid crystal display device according to the present invention.

FIG. 11 is a cross-sectional view schematically illustrating the structure of a third embodiment of the liquid crystal display device according to the present invention.

FIG. 12 is a cross-sectional view schematically illustrating a structure of a fourth embodiment of the liquid crystal display device according to the present invention.

13 is a schematic plan view illustrating an example of an electrode configuration near one pixel of a liquid crystal panel included in the IPS mode liquid crystal display device illustrated in FIG.

FIG. 14 is a plan view illustrating an overall configuration of a thin film transistor substrate of a projection type liquid crystal display device as an example of a liquid crystal display device to which the present invention is applied.

FIG. 15 is a schematic cross-sectional view illustrating an example of a main part structure of a liquid crystal panel of a conventional liquid crystal display device using a polycrystalline silicon semiconductor.

FIG. 16 is a schematic plan view illustrating a main structure of the liquid crystal panel illustrated in FIG.

[Explanation of symbols]

 SUB1 Thin film transistor substrate SUB2 Counter substrate P-S1 Polycrystalline silicon semiconductor layer GI Gate insulating layer GL Gate line DL Drain line SD1 Source electrode SD2 Drain electrode PAS-1 to PAS-4 Insulating layer ITO-1 Pixel electrode ITO-2 Counter electrode ORI -1, ORI-2 alignment film LC liquid crystal layer OC planarization layer CTH (CTH1-4) Contact hole ITO-2 Common electrode.

Claims (5)

[Claims] 1. A liquid crystal display device comprising: a liquid crystal panel in which liquid crystal is sealed between a pair of substrates; and a driving circuit for driving the liquid crystal panel, wherein a thin film transistor is provided on one substrate of the liquid crystal panel. A drain line connected to the drain electrode; a gate line formed to intersect with the drain line via a first insulating layer and a gate insulating film so as to become a gate electrode of the thin film transistor; and an intersection of the drain line and the gate line. A pixel electrode driven by the thin film transistor formed in the vicinity, a source electrode connecting the thin film transistor to the pixel electrode, a contact hole connecting the drain electrode to the drain line, the gate electrode, and the source electrode Forming a contact hole connecting to the pixel electrode above the drain line or the gate line The liquid crystal display device, characterized in that the. 2. A liquid crystal display device comprising: a liquid crystal panel in which liquid crystal is sealed between a pair of substrates; and a driving circuit for driving the liquid crystal panel, wherein a thin film transistor is provided on one substrate of the liquid crystal panel. A drain line connected to the drain electrode; a gate line formed to intersect with the drain line via a first insulating layer and a gate insulating film so as to become a gate electrode of the thin film transistor; and an intersection of the drain line and the gate line. A pixel electrode driven by the thin film transistor formed in the vicinity thereof, wherein the thin film transistor has a semiconductor layer, the drain electrode connected to one end of a channel formed by the semiconductor layer, and the gate above the semiconductor layer. A gate electrode formed between an insulating film and a second insulating layer; and a source electrode connected to the other end of a channel formed by the semiconductor layer. A first contact hole penetrating the second insulating layer, the gate insulating film, and the first insulating layer; and a drain contact penetrating the second insulating layer and the gate insulating film. And a second contact hole, and is formed so as to cover the gate line with an upper layer of the second insulating layer, and the source electrode is connected to the second insulating layer and the second insulating layer. A third insulating layer formed to cover the source electrode while being connected to the other end of the channel through a third contact hole penetrating the gate insulating film, and a planarizing layer formed to cover the third insulating layer And connected to the pixel electrode formed so as to cover the flattening layer through a fourth contact hole penetrating through the second insulating layer and to cover the gate line on the second insulating layer. Ri, said first, second, liquid crystal display device in which all of the third and fourth contact holes, characterized in that arranged on the drain line. 3. The liquid crystal display device according to claim 1, wherein the drain line is a light-shielding high-melting metal. 4. The liquid crystal display device according to claim 1, wherein the drain line, the drain electrode, and the source electrode are made of a light-shielding refractory metal. 5. The liquid crystal display device according to claim 1, wherein said semiconductor layer is a polycrystalline silicon semiconductor.