JP2001203938A - Solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a solid-state image pickup element which can compute respective color image signals faster when the resolution of the solid-state image pickup element is decreased to obtain a color image. SOLUTION: Denoting as A (i, j) pixel cells 104 at positions (X, Y)=(i, j) (i=2 to 2m, j=2 to 2n), held electric signals are read in arbitrary order out of four pixel cells 104 at positions A (i-1, j-1), A (i-1, j), A (i, j-1) and A (i, j) by a shift register and a 1-bit decoder of a row decoder 102 and a 1-bit decoder of a column and multiplexer circuit 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a solid-state image pickup device which realizes image pickup by acquiring image data through light receiving elements such as photodiodes arranged in an array.

[0002]

2. Description of the Related Art The configuration and operation of a conventional solid-state imaging device extracted from a data sheet of a CMOS image sensor MCM2007 manufactured by Motorola will be described below. FIG. 8 is a block diagram showing a schematic configuration of the above-described conventional solid-state imaging device.

As shown in FIG. 8, in a conventional solid-state image pickup device, a pixel cell 204 has three pixels in X and Y directions, respectively.
84 and 304 pixel arrays 201 arranged in an array, and a plurality of pixel cells 204 arranged in an array
Among them, a row decoder 202 for specifying a position in the Y direction (row direction), a column and multiplexer circuit 203 for specifying a position in the X direction (column direction) and amplifying an image signal to be output, and the like It is composed of

FIG. 9 shows a pixel cell 204 and a row decoder 2.
FIG. 2 is a diagram showing a connection configuration between the pixel cell 204 and a column and multiplexer circuit 203 and an internal circuit of a pixel cell 204. As shown in FIG. 9, the pixel cell 204 includes an N-channel MOS transistor (hereinafter, referred to as an NMOS transistor) 205 to 208 and a photodiode 209 which generates and accumulates electric charge proportional to the amount of received light by photoelectric conversion. And a capacitor C0 that holds the charge accumulated by the photodiode 209.

In FIG. 9, the drain of the NMOS transistor 206 is connected to the source of the NMOS transistor 205 whose drain is connected to the high voltage power supply VDD, so that the source of the NMOS transistor 206 is connected to the low voltage power supply (ground potential). The photodiode 20 described above
9 is connected. On the other hand, the drain is a high voltage power supply V
The source of the NMOS transistor 207 connected to the DD is connected to the drain of the NMOS transistor 208, and the gate of the NMOS transistor 207 is connected to the NMO
The source of the S transistor 205 and the other end of the capacitor C0 whose one end is connected to the low voltage power supply are connected.

Each pixel cell 204 has a wiring for inputting a reset signal to the gate of each NMOS transistor 205 in the X direction (horizontal direction in the figure),
Wiring for inputting an image write signal to the gate of the S transistor 206 and wiring for inputting an image read signal to the gate of each NMOS transistor 208 are connected to each other by three common lines.

In particular, in FIG. 9, reset signals RG0 to RG are sequentially output from the top row for each of the reset signal, image write signal, and image read signal.
G303, image write signals TG0 to TG303, and image read signals RS0 to RS303.
The reset signals RG0 to RG303, the image write signals TG0 to TG303, and the image read signal RS
0 to RS 303 are all generated by the row decoder 202.

The sources of the NMOS transistors 208 of the respective pixel cells 204 are connected to each other by a common line for extracting an image signal in the Y direction (vertical direction in the figure). These are represented as ColumnBus 0 to 383 in order from the left column. In addition, these ColumnBus0 to 383
Are all connected to the column and multiplexer circuit 203.

FIG. 10 is a diagram showing an internal configuration of the column and multiplexer circuit 203. As shown in FIG. 10, the column and multiplexer circuit 203 includes an amplifier circuit 210 and a multiplexer circuit 211. The amplification circuit 210 is provided with the above-mentioned ColumnBus0
To 383 are provided in one-to-one correspondence, and NMOS transistors 212 to 215 for performing input / output control of image signals, a capacitor 216 for holding pixel signals output from the pixel array 201, and 217 and an amplifier 218 for amplifying the image signal
To 220.

In FIG. 10, the drain is Column.
The input terminal of the amplifier 218 and one end of the capacitor 216 are connected to the source of the NMOS transistor 212 connected to one of nBus 0 to 383, and the drain is connected to the amplifier 2
NMOS transistor 21 connected to the output terminal 18
The input terminal of the amplifier 220 is connected to the source 4. On the other hand, in contrast to these configurations, the input terminal of the amplifier 219 and one end of the capacitor 217 are connected to the source of the NMOS transistor 213 whose drain is connected to the drain of the NMOS transistor 212, and the drain is connected to the output terminal of the amplifier 219. NMOS transistor 2
The input terminal of the amplifier 220 is connected to 15 sources. The other ends of the capacitors 216 and 217 are connected to a lower power supply voltage (ground potential).

Each of the amplifying circuits 210 transmits a control signal SHR, which will be described later, to an NMOS transistor in the X direction (horizontal direction in the figure).
A wiring for inputting to the gate of the transistor 213;
A control signal SHS described later is transmitted to each NMOS transistor 21.
2, a wiring for inputting a control signal SR described later to the gate of each NMOS transistor 215, and a control signal ZSR described later for each NMOS transistor 215.
Wiring for input to the gate of the transistor 214;
Are connected to each other by four common lines.

On the other hand, the multiplexer circuit 211 includes multiplexers 212 and 213, and each multiplexer includes a tri-state type analog amplifier. Here, in FIG.
s0-383, ColumnBus0-63, Co
lumBus64-127 and ColumnBus1
28-191 and ColumnBus 192-255
And ColumnBus 256-319 and Column
Divided into six groups of nBus 320 to 383, and the multiplexer 212 described above is provided for each of these groups.

Therefore, the multiplexer 212 allocates an analog amplifier to each of the amplifier circuits 210, and the multiplexer 213
An analog amplifier is arranged for every 12 units. That is, the multiplexer 212 has 64 analog amplifiers, and the multiplexer 213 has 6 analog amplifiers.

The multiplexer 212 can control the output of any analog amplifier by inputting a control signal AMUX [0:63] to each analog amplifier. For example, by inputting “H” level AMUX [0] to an analog amplifier that amplifies the output signal TCDS0 of the amplifier circuit 210 corresponding to ColumnBus0, the output of the analog amplifier is set to a low impedance state, and another analog amplifier is set. Can be brought into a high impedance state. That is, only the output of any one analog amplifier can be activated. Similarly, for the multiplexer 213, by inputting the control signal BMUX [0: 5] to each analog amplifier,
Output control of any analog amplifier can be performed.

Next, the operation of the conventional solid-state imaging device will be described. 11 and 12 are timing charts for reading out image signals in a conventional solid-state imaging device. In particular, FIG. 11 shows a case where an image signal is extracted from one pixel cell 204, respectively. FIG. 12 shows a case where image signals are extracted from all the pixel cells 204.

First, the operation of reading an image signal from one pixel cell 204 will be described. In the pixel cell 204 of the solid-state imaging device, there are three operation modes for reading an image signal: an image accumulation mode in which an image signal is accumulated, a reset mode in which a black level signal is output, and an image in which an image signal is output. The mode is sequentially shifted to the read mode.

The image accumulation mode is a state until the image write signal TG0 goes to "H" level in FIG. 11, and during this time, the pixel cell 204 is generated by the photodiode 209 according to the amount of light received. Charge is accumulated.

This means that in FIG. 9, the NMOS transistor 206 is turned off when the image write signal TG0 of "L" level is inputted to the gate thereof, whereby the photodiode 209 is turned off. Since the cathode is connected to the source of the NMOS transistor 206, the accumulation of charges can be maintained.

Next, in this state, the reset mode is set when the reset signal RG0 goes to "H" level. That is, in FIG.
Is turned on by the input of the “H” level reset signal RG0 to its gate, whereby one end of the capacitor C0 (the FD terminal in FIG. 202) is set to NM.
Since it is connected to the source of the OS transistor 205, it is reset to the potential level of the high power supply voltage VDD.

In this state, the NMOS transistor 207
Also indicates that the potential of the gate of the NMOS transistor 207 coincides with the high power supply voltage VDD, and further, assuming that the image read signal RS0 is at the “H” level, both the NMOS transistors 207 and 208 are turned on. Therefore, after that, when the control signal SHR goes to the “H” level, N in the amplifying circuit 210 of the column and multiplexer circuit 203
The MOS transistor 213 is turned on, a current is supplied to ColumnBus0 through the NMOS transistors 207 and 208 of the pixel cell 204, and the capacitor 217 of the amplifier circuit 210 is charged. In this state, reset signal RG0 is at "L" level.

By this charging, a voltage value in a state where there is no image signal, that is, a black level state (hereinafter, referred to as a black level voltage) is stored at both ends of the capacitor 217. Subsequently, the image write signal TG0
Is set to the “H” level, the read mode is set. That is, in FIG. 9, the NMOS transistor 206 is turned on by the input of the “H” level reset signal TG0 to its gate, and the cathode of the photodiode 209 and one end of the capacitor C0 are electrically connected to each other. The image signal accumulated as electric charge in the 209 is FD
It is transferred to the terminal capacitor C0.

As a result, the voltage of the FD terminal changes to a voltage value corresponding to the transferred charge amount. Then, a current corresponding to the voltage value after this change is output to ColumnBus0 in the same procedure as in the above-described reset mode. Thereafter, when the control signal SHS goes to the “H” level, the NMOS transistor 212 is turned on. As a result, the capacitor 216 is charged, and a potential difference is generated between both ends of the capacitor 216. This potential difference (hereinafter, referred to as a signal level voltage) is stored as a value proportional to the image signal stored in the pixel cell 204.

The electric charges accumulated in each of the capacitors 216 and 217 in the amplifying circuit 210 of the column and multiplexer circuit 203, that is, the signal level voltage and the black level voltage are respectively supplied to the amplifier 21.
8 and 219 and the control signals SR and Z
When SR becomes “H” level, it is output as output signal TCDS0 of amplifier 220. And amplifier 2
As shown in FIG. 10, the output signal TCDS0 output from 20 is again amplified through each analog amplifier in the multiplexer circuit 211 and output from the output terminal MUXOUT of the multiplexer 211 to the outside.

Next, the overall operation of the solid-state imaging device, that is, a method of reading image signals from all the pixel cells 204 in the pixel array 201 will be described. In order to read image signals from all the pixel cells 204 in the pixel array 201, reset signals RG0 to RG303, image write signals TG0 to TG303, and image read signals RS0 to R input to the pixel cells 204 in FIG.
S303, control signals SHS, SHR input to the amplifier 210 of the column and multiplex circuit 203,
SR and ZSR, and multiplexers 221 and 22
2 and control signals AMUX [0:63] and B
MUX [0: 5] may be sequentially given in a time division manner according to the timing chart shown in FIG.

In FIG. 12, first, in cycle 0,
The reset signal RG0, the image write signal TG0, and the image read signal RS0 are generated by the row decoder 202. In the pixel array 201, the reset signal RG
0, image write signal TG0 and image read signal R
384 pixel cells arranged in the X direction are connected to S0, and in each of these pixel cells 204, the above-described three operation modes of the image accumulation mode, the reset mode, and the image reading mode are executed.

As a result, the signal level voltage and the black level voltage of the 384 pixel cells 204 are changed to the amplifying circuit 210 of FIG.
Is held. Then, in the next cycles 1 to 384,
Control signals AMUX [0:63] and BMUX [0:
5] is generated. 64 control signals AMUX [0: 6
3] is a signal which becomes "H" level only one bit per cycle in order from bit 0, and is generated at a cycle of 64 cycles. Also, the six control signals BMUX [0: 5] also go to the “H” level only in the order of bit 0 every 64 cycles. Therefore, the signal level voltage held in the amplifier circuit 210 in FIG. 10 is read from the output terminal MUXOUT of the multiplexer 211 in order from the left in the figure.

As described above, in the cycles 0 to 384, the image signals of the 384 pixel cells 204 arranged in the uppermost row of the pixel array 201 can be read. Pixel cell 204 arranged in the second row of pixel array 201
, The reset signal RG1, the image write signal TG1, and the image read signal RS1 connected to the pixel cells 204 in the second row may be generated as in a cycle 385 shown in FIG.

The pulse generation timings of the reset signal RG1, the image write signal TG1, and the image read signal RS1 generated in cycle 385 are the same as those of the reset signal RG0, image write signal TG0, and image read signal RS0 generated in cycle 0. Timing.

Subsequently, control signals AMUX [0:63] and BMUX [0: 5] are generated in cycles 386 to 769, so that the image signal is output to the output terminal MUXOU.
Read from T. Hereinafter, similarly, the pixel array 2
In order to read out the image signals of the pixel cells 204 arranged in the third and subsequent rows of the first row, the pixel cells 20 in the third and subsequent rows are read out.
4, the reset signals RG2 to RG303, the image write signals TG2 to TG303, and the image read signals RS2 to RS303 may be generated every 385 cycles.

In order to colorize the solid-state image pickup device, the light receiving surface of the photodiode 209 of the pixel cell 204 has a light receiving surface represented by red (R), green (G), and blue (B).
This can be realized by covering a resin called a primary color filter. FIG. 13 is an explanatory diagram for explaining the arrangement of color filters in a conventional color high-resolution solid-state imaging device. As shown in FIG.
In a high-resolution solid-state imaging device, color filters of each color are generally arranged in a checkered pattern.

Therefore, in order to display a color image at a resolution of 384 × 304, three image signals for red (R), green (G) and blue (B) are required for all pixels. When the color filters are arranged in a checkered pattern, only one color image signal can be read from one pixel cell 204. In this case, outside of the solid-state imaging device, an insufficient image signal is calculated from the image signal of another pixel cell 204 located near the pixel cell and covered with the other two color filters. An operation called an interpolation process is required.

[0032]

As described above, according to the conventional solid-state imaging device, the row decoder 202
Reset signals RG0 to RG303, image write signal T
G0-TG303 and image read signals RS0-RS
303 from bit 0 to bit 303 every 385 cycles
Up to the multiplexer 21
1 control signals AMUX [0:63] and BMUX [0:
5] is also generated sequentially from bit 0 to the last bit position every cycle and every 64 cycles, thereby adopting a method of reading image signals from all the pixel cells 204 in the pixel array 201. .

In the high-resolution solid-state image pickup device for color, by performing interpolation processing outside the solid-state image pickup device, it is possible to realize colorization of an image while maintaining the resolution.

However, in the conventional solid-state imaging device,
In order to read image signals from all the pixel cells 204 in the pixel array 201, the X address is scanned by scanning the X address while incrementing the address in the X direction by one, and the scanning in the X direction is performed for the Y direction. Is completed, scanning is performed by incrementing the address by one, so that (X, Y) = (i, j) (i
= 2 to 2m, j = 2 to 2n)
In the next cycle after the image signal of (i, j) is read, the image signal of A (i + 1, j) is always read. Therefore, in the next cycle after the pixel signal of the pixel cell A (i, j) is read, the pixel cell A (i, j-1) or the pixel cell A (i, j + 1) in the adjacent row is read. There is a problem that the image signal at the position of cannot be read.

In a color high-resolution solid-state imaging device, when the resolution is reduced to half and the area surrounded by the broken line in FIG. 13 is regarded as one pixel cell, one pixel cell within the broken line is considered. From inside red (R), green (G), blue (B)
Despite the fact that three image signals can be extracted, the conventional high-resolution solid-state image sensor calculates the image signals by performing interpolation processing externally. However, there is a problem that it is always necessary and takes time.

The present invention has been made to solve the above-mentioned problems. In particular, when the resolution of a solid-state imaging device is reduced to realize colorization, red (R) and green (G) are used. , And a solid-state imaging device capable of calculating three image signals for blue (B) more quickly.

[0037]

Means for Solving the Problems To solve the above-mentioned problems,
In order to achieve the object, in a solid-state imaging device according to the present invention, light receiving means for accumulating charge generated by light reception, a transistor for discharging the charge accumulated in the light receiving means, and the light receiving means A second transistor for reading an electric signal proportional to the electric charge stored in the second transistor;
Pixel cells consisting of two in the X and Y directions, respectively.
A pixel array arranged and arranged in an array of m pieces and 2n pieces (m and n are natural numbers), and the first transistor and the second transistor of a specific pixel cell in the pixel array are operated. (X, Y) = (i, j) (i) in the solid-state imaging device having the first addressing means and the second addressing means for
= 2 to 2 m, j = 2 to 2n)
When expressed as (i, j), A (i-1, j-1),
A (i-1, j), A (i, j-1) and A (i,
means for reading out the electric signals from the four pixel cells at the position j) in any order.

According to the present invention, the 2α cell and the Y cell
In a pixel array in which pixel cells of 2.beta. Cells (.alpha. = 1 to m, .beta. = 1 to n) are arranged in the direction, the first direction and the second addressing means set the X direction to 2α-1, 2α. , Y direction can address 2β-1, 2β, respectively, so that four pixel cells A (2α-1,
2β-1), A (2α, 2β-1), A (2α-1,2
β) and A (2α, 2β) (α = 1 to m, β = 1 to
The image signal of n) can be read out in an arbitrary order.

In the solid-state image pickup device according to the next invention, in the above-mentioned invention, the first addressing means comprises an m-bit shift register and m 1-bit decoders, and the second addressing means. Means are
It is characterized by comprising an n-bit shift register and n 1-bit decoders.

According to the present invention, the 2α cell and the Y
In a pixel array in which pixel cells of 2.beta. Cells (.alpha. = 1 to m, .beta. = 1 to n) are arranged in the direction, the 1-bit decoder of the first addressing means makes 2.alpha.
-1, 2α, and any one of 2β-1, 2β can be addressed in the Y direction by the shift register of the second addressing means.

In the solid-state image pickup device according to the next invention, in the above-mentioned invention, red (R),
One of green (G) and blue (B) color filters is arranged in a checkered pattern on the pixel array.
(2α-1,2β-1), A (2α, 2β-1), A
(2α-1,2β) and A (2α, 2β) (α = 1 to
means for acquiring output signals from four pixel cells (m, β = 1 to n) as color signals from pixel cells at the position of (X, Y) = (α, β). I do.

According to the present invention, four pixel cells A (2
α-1,2β-1), A (2α, 2β-1), A (2α
−1, β), A (2α, 2β) (α = 1 to m, β = 1
To (n) can be treated as a color signal from a pixel at the position of (X, Y) = (α, β).

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the solid-state imaging device according to the present invention will be described below in detail with reference to the drawings.
The present invention is not limited by the embodiment.

FIG. 1 is a diagram showing a connection configuration between a pixel cell 204, a row decoder 202, and a column and multiplexer circuit 203 and an internal circuit of the pixel cell 204 in the solid-state imaging device according to the embodiment. As shown in FIG. 1, the solid-state imaging device according to the embodiment includes a pixel array 101 in which 384 and 304 pixel cells 104 are arranged in an X direction and a Y direction, respectively.
Of the plurality of pixel cells 104 arranged in an array,
Row decoder 102 for specifying the direction (row) position
And a column and multiplexer circuit 103 for specifying the position in the X direction (column) and amplifying the image signal to be output.

In FIG. 1, the pixel cell 104 is
It comprises NMOS transistors 105 to 109, a photodiode 110 that generates and accumulates charge proportional to the amount of light received by photoelectric conversion, and a capacitor C1 that holds the charge accumulated by the photodiode 110.

In FIG. 1, the drain of the NMOS transistor 106 is connected to the source of the NMOS transistor 105 whose drain is connected to the high voltage power supply VDD, and the source of the NMOS transistor 106 is
The drain of the NMOS transistor 109 is connected. The photodiode 110 is connected between the source of the NMOS transistor 109 and a low voltage power supply (ground potential). On the other hand, the NMOS transistor 107 whose drain is connected to the high voltage power supply VDD
Is connected to the drain of the NMOS transistor 108, and the gate of the NMOS transistor 107 is connected to the source of the NMOS transistor 105 and the other end of the capacitor C1 whose one end is connected to the low voltage power supply. .

Each pixel cell 104 has a wiring for inputting a reset signal to the gate of each NMOS transistor 105 in the X direction (horizontal direction in the figure),
The wiring for inputting an image writing signal to the gate of the S transistor 106 and the wiring for inputting an image reading signal to the gate of each NMOS transistor 108 are connected to each other by three common lines.

In particular, in FIG. 1, the reset signals RG0 to RG for the reset signal, the image write signal, and the image read signal are sequentially described from the top row.
G303, image write signals TG0 to TG303, and image read signals RS0 to RS303.
The reset signals RG0 to RG303, the image write signals TG0 to TG303, and the image read signal RS
0 to RS 303 are all generated by the row decoder 102.

Each pixel cell 104 is connected to the source of the NMOS transistor 108 in the Y direction (vertical direction in the figure) by a common line for extracting an image signal. , Are represented as ColumnBus 0 to 383 in order from the left column. In addition, these ColumnBus0 to 383
Are all connected to the column and multiplexer circuit 103.

Further, in the solid-state imaging device according to this embodiment, the NMOS transistor 1 of each pixel cell 104
The gates 09 are connected to each other by a common line for extracting a column read signal in the Y direction (vertical direction in the figure), and the column read signals are sequentially read from the left column in FIG. CL0 to 383. Note that these column read signals CL0 to CL3
83 is a column and multiplexer circuit 103
Generated by

FIG. 2 is a circuit diagram showing the internal configuration of the row decoder 102. In FIG. 2, the row decoder 102
Are a reset signal generation circuit 111, an image write signal generation circuit 112, and an image read signal generation circuit 113
And The inside of the reset signal generation circuit 111, the image write signal generation circuit 112, and the image read signal generation circuit 113 include a 152-bit shift register 114 composed of D flip-flops (DF / F) F1 to F152, and an inverter. IV1, IV
2 and a 1-bit decoder 115 composed of AND gates G0 to G303.

The reset signal generation circuit 111 includes:
The shift clock RGCK, the shift signal RGIN, the decode clock RGCKX2, and the lowest address signal R
GAD0 is input. Similarly, a shift clock TGCK, a shift signal TGIN, a decode clock TGCKX2,
The lowest address signal TGAD0 is input to the image read signal generation circuit 113, and the shift clock RSC
K, shift signal RSIN, and decode clock RSC
KX2 and the lowest address signal RSAD0 are input.

The shift register 114 includes reset signals RG0 to RG30 in the reset signal generation circuit 111.
3 are sequentially divided into two sets, and as shown in FIG. 2, one D flip-flop is assigned to each set. Then, these D flip-flops F1 to F
152 receives the shift signal RGIN as the D input of the first-stage D flip-flop F1 corresponding to the set of the reset signals RG0 and RG1, and the subsequent lower-stage D flip-flops F2 to F152 receive the upper-stage Q flip-flops F2 to F152, respectively. The output is a D input. Further, the Q outputs of the D flip-flops F1 to F152 are input to the 1-bit decoder 115.

On the other hand, the 1-bit decoder 115 assigns two 3-input AND gates to each of the above sets, and uses the output of each AND gate as a reset signal.
A signal obtained by inverting the lowest address signal RGAD0 by the inverter IV1, the decode clock TGCKX2, and the Q output of the D flip-flop are input to one AND gate. And the other AN
The D-gate has the lowest address signal RGAD0 obtained by further inverting the output signal of the inverter IV1 by the inverter IV2, and the decode clock TGCK.
X2 and the Q output of the D flip-flop described above are input.

For example, referring to FIG.
0 is the lowest address signal RG by the inverter IV1.
AD0 inverted signal and decode clock TGCK
X2 and the Q output of the D flip-flop F1 are input, and a reset signal RG0 is output. The AND gate G1 is further connected to the inverter I2 by the inverter IV2.
The lowest address signal RGAD0 obtained by inverting the output signal of V1 and the decode clock TGCKX2
And the Q output of the D flip-flop F1 and output a reset signal RG1.

FIG. 3 is a circuit diagram showing an internal configuration of the column and multiplexer circuit 103. In FIG.
The column and multiplexer circuit 103 includes the amplifier circuit 1
16, a multiplexer 117, and a column decoder 118.
And

The amplification circuit 116 has the above-mentioned Column
NM 0 to 383 are provided in one-to-one correspondence with each other, and perform NM control for input / output control of image signals.
The OS transistors 119 to 122 and the pixel array 101
1 for holding the pixel signal output from
23 and 124, and amplifiers 125 to 127 for amplifying image signals.

In FIG. 2, the drain is Column.
The input terminal of the amplifier 125 and one end of the capacitor 123 are connected to the source of the NMOS transistor 119 connected to one of the buses Bus0 to 383, and the drain is connected to the amplifier 12
NMOS transistor 121 connected to the output terminal 5
Is connected to the input terminal of the amplifier 127. On the other hand, in contrast to these configurations, the input terminal of the amplifier 126 and one end of the capacitor 124 are connected to the source of the NMOS transistor 120 whose drain is connected to the drain of the NMOS transistor 119, and the drain is connected to the output terminal of the amplifier 126. NMOS transistor 1
The input terminal of the amplifier 127 is connected to the source 22. The other ends of the capacitors 123 and 124 are connected to a lower power supply voltage (ground potential).

Each of the amplifying circuits 116 transmits a control signal SHR, which will be described later, to the NMOS in the X direction (horizontal direction in the figure).
A wiring for inputting to the gate of the transistor 120;
A control signal SHS described later is transmitted to each NMOS transistor 11.
9, a wiring for inputting a control signal SR to be described later to the gate of each NMOS transistor 122, and a wiring for inputting a control signal ZSR to be described later to each NMOS transistor 122.
A wiring for inputting to the gate of the transistor 121;
Are connected to each other by four common lines. On the other hand, the multiplexer 117 includes a tri-state type analog amplifier 130 for each of the amplifier circuits 116 described above.
Is allocated and equipped. That is, the multiplexer 1
17 has 384 analog amplifiers.

The multiplexer 117 can control the output of any analog amplifier by inputting the control signals CL0 to CL383 to each analog amplifier 130. For example, by inputting “H” level CL0 to the analog amplifier 130 that amplifies the output signal TCDS0 of the amplifier circuit 116 corresponding to ColumnBus0, the output of the analog amplifier is set to a low impedance state, and the output of another analog amplifier is output. Can be in a high impedance state. That is, only the output of any analog amplifier can be activated.

The column decoder 118 is composed of a 192-bit shift register 131 composed of a D flip-flop (DF / F) and a 1-bit decoder 132 composed of an inverter and an AND gate. The internal configurations of the shift register 131 and the 1-bit decoder 132 of the column decoder 118 are the same as those of the above-described shift register 114 and the 1-bit decoder 115, respectively, and a description thereof will be omitted.

However, in FIG. 3, the shift clock C
LCK, shift signal CLIN, decode clock CLC
KX2, lowest address signals CLAD0 and CL0
CL383 is the reset signal generation circuit 11 shown in FIG.
1 corresponds to the shift clock RGCK, the shift signal RGIN, the decode clock RGCKX2, the lowest address signal RGAD0, and RG0 to RG303, respectively.

Next, the operation of the solid-state imaging device according to this embodiment will be described. 4 to 7 are timing charts for reading out image signals in the solid-state imaging device. In particular, FIGS. 4 and 5 each show a timing chart when an image signal is taken out from one pixel cell 104, FIG. 6 shows a timing chart when an image signal is read out at a resolution of 384 × 304, and FIG. , Reducing the resolution by half to 197x1
52 shows a timing chart when an image signal is read.

First, the operation of reading an image signal from two pixel cells 104 whose columns are adjacent will be described with reference to the timing chart of FIG. In the pixel cell 104 of the solid-state imaging device, there are three operation modes for reading an image signal: an image accumulation mode in which an image signal is accumulated, a reset mode in which a black level signal is output, and an image in which an image signal is output. The mode is sequentially shifted to the read mode.

The image accumulation mode is the cycle 0 shown in FIG.
, The state until the image write signal TG0 becomes “H” level. During this time, the photodiode 110 in the pixel cell 104 accumulates charges generated according to the amount of light received. This corresponds to N in FIG.
This indicates that the MOS transistor 106 is turned off when the image write signal TG0 of “L” level is input to its gate, whereby the photodiode 1
Since the cathode 10 is connected to the source of the NMOS transistor 106, it can maintain the accumulation of electric charge.

Next, in this state, the reset mode is set when the reset signal RG0 goes to "H" level. That is, in FIG.
Is turned on when the reset signal RG0 of the “H” level is input to the gate thereof, whereby the capacitor C1 has one end (the FD terminal in FIG. 1) connected to the NMOS.
Since it is connected to the source of the transistor 105, it is reset to the potential level of the high power supply voltage VDD.

In this state, the NMOS transistor 107
Also indicates that the potential of the gate of the NMOS transistor 107 coincides with the high power supply voltage VDD. When the image read signal RS0 is at the “H” level, both the NMOS transistors 107 and 108 are turned on. Therefore, after that, the control signal SH
When R becomes “H” level, the NMOS transistor 120 in the amplifier circuit 116 of the column and multiplexer circuit 103 is turned on, a current is supplied to ColumnBus0 through the NMOS transistors 107 and 108, and the capacitor of the amplifier circuit 116 is turned on. 124 is charged. By this charging, the capacitor 124 holds the black level voltage. In this state,
Reset signal RG0 is at "L" level.

Subsequently, the read mode is set when the image write signal TG0 goes to "H" level. In this state, the column read signal CL0 is at "H" level. That is, in FIG. 1, the NMOS transistor 106 has an “H” level reset signal T
When G0 is input, it is turned on and NM
Since the OS transistor 109 is in the ON state, the cathode of the photodiode 110 and one end of the capacitor C1 conduct, and the image signal accumulated as charge in the photodiode 110 is transferred to the capacitor C1 of the FD terminal.

As a result, the voltage of the FD terminal changes to a voltage value corresponding to the transferred charge amount. Then, a current corresponding to the voltage value after this change is output to ColumnBus0 in the same procedure as in the above-described reset mode. Thereafter, when the control signal SHS goes to the “H” level, the NMOS transistor 212 is turned on. Thereby, the capacitor 123 is charged, and the capacitor 123 is charged.
Holds the signal level voltage as a value proportional to the image signal stored in the pixel cell 104.

The electric charges accumulated in each of the capacitors 123 and 124 in the amplifier circuit 116 of the column and multiplexer circuit 103, that is, the signal level voltage and the black level voltage are respectively supplied to the amplifier 12
5 and 126, the control signals SR and Z
When SR becomes “H” level, it is output as output signal TCDS0 of amplifier 127. Then, in cycle 1, the lowest address CLAD0 changes from “L” to “H” level in the column and multiplexer circuit 103, and the shift clock CL of the column decoder 118 is changed.
When CK goes to “H” level, the column read signal CL
1 becomes "H" level.

At this time, the shift clocks RGCK, TGCK and RSCK of the reset signal generation circuit 111, the image write signal generation circuit 112 and the image read signal generation circuit 113 of the row decoder 102, the shift inputs RGIN, TGIN and RSIN, Control signals such as the lowest address signals RGAD0, TGAD0, and RSAD0 all remain at "L" level.

Therefore, in cycle 1, the same Y as that of pixel cell 104 from which the image signal was read in cycle 0 is used.
The pixel cell 104 at the address and the position where the X address is shifted by one operates. That is, in the cycle 1, the pixel cell 104 on the right side of the pixel cell 104 operated in the cycle 0 operates, and the signal level voltage and the black level voltage are supplied through the Column Bus 1 to the amplifier circuit 11.
6 and are again amplified through the multiplexer 117 and output to the outside from the output terminal MUXOUT of the multiplexer 117.

Next, the operation of reading image signals from two pixel cells 104 whose rows are adjacent will be described with reference to the timing chart of FIG. The operation in cycle 0 is the same as the operation in FIG. 4. At this time, the signal level voltage and the black level voltage are held in capacitors 123 and 124 of amplifying circuit 116 through ColumnBus 0 and are amplified again through multiplexer 117. The signal is output from the output terminal MUXOUT to the outside.

Subsequently, in cycle 1, the lowest address signal RGAD0 of the reset signal generation circuit 111 of the row decoder 102 and the image write signal generation circuit 112
And the least significant address signal TGAD0 of the image read signal generation circuit 113 changes from “L” to “H” level. for that reason,
The reset signal RG0, the image write signal TG0, and the image read signal RS0 are all fixed at the “L” level, but instead of the reset signal RG1, the image write signal T0.
G1 and the image read signal RS1 transition to the “H” level.

Since the lowest address signal CLAD0 changes from "L" to "H" level in the column and multiplexer circuit 103, the column read signal CL0 changes to "H" level. Therefore, in this cycle 1, the pixel cell 104 that has read the image signal in cycle 0
The pixel cell 104 at the same X address as the above and at a position shifted by one Y address operates.

That is, in the cycle 1, the pixel cell 104 below the pixel cell 104 operated in the cycle 0 operates, and the signal level voltage and the black level voltage are changed to Colu.
mnBus0 through the capacitor 12 of the amplifier circuit 116
3 and 124, are amplified again through the multiplexer 117 and output to the outside. As a result, it is possible to operate the pixel cells 104 at the positions of the adjacent rows without completing the scanning in the X direction.

Next, a timing chart of the overall operation of the solid-state imaging device shown in FIGS. 6 and 7 will be described. In FIG. 6, the pixel cells 104 are operated from the cycle 0 to the cycle 383 by the scanning method of the timing chart shown in FIG. Thereby, all the pixel cells 104 arranged in the X direction operate. Then, in cycle 384, FIG.
After the use of the scanning method of FIG.
Is used. By repeating this 152 times, all the pixel cells 104 are operated. By performing such an operation, the same operation as that of a conventional solid-state imaging device can be realized.

In FIG. 7, from cycle 0 to cycle 767
In the case where a transition is made to the next cycle after the even-numbered cycle, the pixel cells at adjacent row positions are scanned using the scanning method shown in FIG. The scanning method 4 is used to scan the pixel cells at the same position in the row. As a result, cycle 0
2 are R → G → B, which is exactly the same as FIG.
3 corresponds to a signal of a pixel cell surrounded by a broken line. In other words, this indicates that the color signal in the pixel cell when the resolution in the X direction and the Y direction has been reduced to half has been read out as it is.

As described above, according to the solid-state imaging device according to the embodiment, 2α cells are arranged in the X direction and 2β cells (α = 1 to m, β = 1 to n) are arranged in the Y direction. In the pixel array obtained, (X, Y) = (α, β) is addressed by the shift register 114 of the row decoder 202, and the column and multiplexer circuit 10
2α−1, 2α in the X direction by the third column decoder 118.
And the reset signal generation circuit 111,
Since 2β-1 and 2β in the Y direction can be selected by the 1-bit decoder 115 of the image write signal generation circuit 112 and the image read signal generation circuit 113, four pixel cells A (2α-1, 2β-1) and A ( 2α, 2β-
1), A (2α-1,2β), A (2α, 2β) (α =
1 to m, β = 1 to n) can be read out in any order, and even if the scanning of the pixel cells in the same row is not completed in the next cycle after reading out the image signal of one pixel cell. In addition, the image signal of the pixel cell in the adjacent row can be read.

Further, four pixel cells A (2α-1, 2β
-1), A (2α, 2β-1), A (2α-1,2)
β), A (2α, 2β) (α = 1 to m, β = 1 to n) as output color signals from the pixel at the position of (X, Y) = (α, β) So you can
When the resolution is lowered, the interpolation processing becomes unnecessary, and three image signals for red (R), green (G), and blue (B) can be calculated more quickly.

[0081]

As described above, according to the present invention, 2α cells in the X direction and 2β cells in the Y direction (α = 1 to
In the pixel array in which the pixel cells of (m, β = 1 to n) are arranged, the first direction and the second addressing means select either 2α-1, 2α in the X direction and 2 in the Y direction.
Since β-1, 2β can be addressed individually,
Four pixel cells A (2α-1,2β-1), A (2α,
2β-1), A (2α-1,2β) and A (2α, 2
β) (α = 1 to m, β = 1 to n) can be read out in an arbitrary order, and in the next cycle of reading out the image signal of one pixel cell, scanning of the pixel cells in the same row is performed. Is completed, the image signal of the pixel cell in the adjacent row can be read.

According to the next invention, 2α cells in the X direction,
In a pixel array in which 2.beta. Cells (.alpha. = 1 to m, .beta. = 1 to n) are arranged in the Y direction, the 1-bit decoder of the first addressing means operates in the X direction so
Any one of α-1, 2α can be addressed, and any of 2β-1, 2β can be addressed in the Y direction by the shift register of the second addressing means, so that the image signal of one pixel cell is read out. In the next cycle, it is possible to read an image signal of a pixel cell in an adjacent row even if scanning of a pixel cell in the same row is not completed.

According to the next invention, four pixel cells A
(2α-1,2β-1), A (2α, 2β-1), A
(2α-1,2β), A (2α, 2β) (α = 1 to m,
The output signal from β = 1 to n) is (X, Y) = (α, β)
Can be treated as a color signal from the pixel at the position of. Therefore, even if the resolution is lowered, the interpolation processing is unnecessary, and three image signals for red (R), green (G), and blue (B) can be processed. This has the effect of being able to calculate faster.

[Brief description of the drawings]

FIG. 1 shows a solid-state imaging device according to an embodiment;
FIG. 2 is a diagram illustrating a connection configuration between a pixel cell and a row decoder and a column and multiplexer circuit, and an internal circuit of the pixel cell.

FIG. 2 illustrates a solid-state imaging device according to an embodiment;
FIG. 3 is a circuit diagram showing an internal configuration of a row decoder.

FIG. 3 illustrates a solid-state imaging device according to an embodiment;
FIG. 3 is a circuit diagram illustrating an internal configuration of a column and multiplexer circuit.

FIG. 4 illustrates a solid-state imaging device according to an embodiment;
6 is a timing chart illustrating an operation when an image signal is extracted from one pixel cell.

FIG. 5 illustrates a solid-state imaging device according to an embodiment;
6 is a timing chart illustrating an operation when an image signal is extracted from one pixel cell.

FIG. 6 illustrates a solid-state imaging device according to an embodiment;
6 is a timing chart illustrating an operation when an image signal is read at a resolution of 384 × 304.

FIG. 7 illustrates a solid-state imaging device according to an embodiment;
9 is a timing chart showing an operation when an image signal is read out at half the resolution of 197 × 152.

FIG. 8 is a block diagram illustrating a schematic configuration of a conventional solid-state imaging device.

FIG. 9 is a diagram illustrating a connection configuration between a pixel cell and a row decoder and a column and multiplexer circuit and an internal circuit of the pixel cell in a conventional solid-state imaging device.

FIG. 10 is a diagram showing an internal configuration of a column and multiplexer circuit in a conventional solid-state imaging device.

FIG. 11 is a timing chart showing an operation in a case where an image signal is taken out from one pixel cell in a conventional solid-state imaging device.

FIG. 12 is a timing chart showing an operation in a case where an image signal is taken out from all pixel cells in a conventional solid-state imaging device.

FIG. 13 is an explanatory diagram for explaining an arrangement of a color filter in a conventional color high-resolution solid-state imaging device.

[Explanation of symbols]

101 pixel array, 102 row decoder, 103
Column and multiplexer circuit, 104 pixel cells,
105 to 109, 119 to 122 NMOS transistor, 110 photodiode, 111 reset signal generation circuit, 112 image writing signal generation circuit, 113
Image readout signal generation circuit, 114, 131 shift register, 115, 132 1-bit decoder, 116
Amplification circuit, 117 multiplexer, 118 column decoder, 123, 124, C1 capacitor, 125-1
27 amplifier, 130 analog amplifier, F1 to F15
2D flip-flops, G0 to G303 AND gates, IV1 and IV2 inverters.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Kunihiko Hara 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Kenichi Shimoson 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) in Mitsubishi Electric Corporation 4M118 AA10 AB01 BA14 CA02 DB09 DD12 GC08 GC14 5C024 AX01 CY16 CY38 DX01 DX03 GX03 GX16 GY35 GY36 GY37 GZ04 GZ16 HX02 HX17 HX33 HX35 HX40 HX41 HX50 JX09 JX DD5 GG25 GG35 GG36

Claims (3)

[Claims] 1. A light receiving means for storing electric charge generated by light reception, a transistor for discharging the electric charge stored in the light receiving means, and an electric signal proportional to the electric charge stored in the light receiving means for reading out an electric signal. A pixel array comprising 2m and 2n (m and n are natural numbers) arrayed in the X and Y directions, respectively, in the pixel array. A first addressing means and a second addressing means for operating the first transistor and the second transistor of the specific pixel cell of (a), (X, Y) = ( i, j) (i = 2-2m, j = 2-2)
When the pixel cell at the position n) is denoted as A (i, j), A (i-1, j-1), A (i-1, j), A
A solid-state imaging device comprising: means for reading out the electric signals from the four pixel cells at the positions of (i, j-1) and A (i, j) in an arbitrary order. 2. The first addressing means comprises an m-bit shift register and m 1-bit decoders, and the second addressing means comprises an n-bit shift register and n 1-bit decoders. The solid-state imaging device according to claim 1, wherein: 3. A red (R), green (G),
One of the blue (B) color filters is arranged in a checkered pattern on the pixel array, and A (2α-1,
2β-1), A (2α, 2β-1), A (2α-1,2
β) and A (2α, 2β) (α = 1 to m, β = 1 to
n) output signals from the four pixel cells are (X, Y) =
3. The solid-state imaging device according to claim 1, further comprising: means for acquiring a color signal from a pixel cell at a position (α, β).