JP2001202892A - AC type plasma display panel - Google Patents

Abstract

(57) Abstract: Provided is an AC-type plasma display panel capable of reducing the cost and power consumption of a display device. A plurality of scan electrodes and a plurality of sustain electrodes are provided in parallel on a first insulating substrate in a state of being covered with a dielectric layer and a protective film layer. Further, a light-shielding layer 6 is provided between each pair of the scanning electrode 4 and the sustain electrode 5 forming a pair. On the other hand, a plurality of data electrodes 9 are provided on the second insulating substrate 7 while being covered with the insulator layer 8. Further, a plurality of barrier ribs 10 are provided on the insulator layer 8 between the data electrodes 9 in parallel with the data electrodes 9. Further, in a portion of the surface of the insulator layer 8 between the partition walls 10 except for a portion facing the light shielding layer 6,
An intermittent striped phosphor 11 is provided. And
The first insulating substrate 1 and the second insulating substrate 7 are opposed to each other with the discharge space 12 interposed therebetween so that a plurality of pairs of scan electrodes 4 and sustain electrodes 5 and data electrodes 9 are orthogonal to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel used for displaying an image on a television, an advertising display, or the like.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional AC type plasma display panel (hereinafter sometimes abbreviated as "panel"). As shown in FIG. 6, on the first insulating substrate 1,
A plurality of scan electrodes 4 and sustain electrodes 5 are provided in parallel in pairs while being covered with the dielectric layer 2 and the protective film layer 3. A light-shielding layer 6 is provided between each pair of the scanning electrode 4 and the sustaining electrode 5 forming a pair. On the other hand, a plurality of data electrodes 9 are provided on the second insulating substrate 7 while being covered with the insulator layer 8. Also, the data electrode 9
A plurality of barrier ribs 10 are provided on the intervening insulator layer 8 in parallel with the data electrodes 9. Furthermore, the partition 1 between the partitions 10
The phosphors 11 are provided in the form of stripes without breaks on the side surfaces 0 and the surface of the insulator layer 8. The first insulating substrate 1 and the second insulating substrate 7 are opposed to each other with the discharge space 12 interposed therebetween so that a plurality of pairs of the scan electrode 4 and the sustain electrode 5 are orthogonal to the data electrodes 9. I have. In this panel, the region of the discharge space 12 corresponding to the intersection of a pair of the scan electrode 4 and the sustain electrode 5 and one of the data electrodes 9 constitutes one discharge cell. The discharge space 12 is filled with one of helium, neon, argon, xenon, or a mixed gas thereof as a discharge gas. In the phosphor 11, a combination of the phosphors 11r, 11b, and 11g that emit red, blue, and green light, respectively, is arranged in order.

FIG. 7 shows an electrode arrangement diagram of this panel.
As shown in FIG. 7, the electrode arrangement of this panel is M rows × N
A matrix arrangement of rows of discharge cells, the scan electrodes SCN ₁ of the M rows in the row direction ～SCN _M and sustain electrodes S
US _{1 to} SUS _M are arranged, and N columns of data electrodes D _{1 to DN} are arranged in the column direction.

Next, a brief description will be given of a method of driving a conventional AC plasma display panel. FIG. 8 shows an operation drive timing chart.

First, in the initialization period, all the
Extreme SUS₁ ~ SUS_M And data electrode D₁ ~ D_N To 0
(V) and all the scanning electrodes SCN₁ ~ SCN_M To
Lamp power gradually rising from Vj (V) to Vp (V)
By applying pressure, the discharge space 1 of all discharge cells
2, all scan electrodes SCN₁ ~ SCN_M Protective film
Layer 3 surface and data electrode D₁ ~ D_N The upper phosphor 11 (1
1r, 11b, 11g).
Thus, the surface of the phosphor 11 (11r, 11b, 11g)
And a wall voltage is accumulated between all the sustain electrodes 5 and the scan electrodes 4.
Between (SUS₁ And SCN₁ Between and SUS_Two And SCN_Two When
During, SUS_M And SCN_M Between) and the protective film layer
3 accumulates wall voltage on the surface. Then, all the sustain electrodes
SUS₁ ~ SUS_M Is maintained at Vq (V), and all scans
Electrode SCN₁ ~ SCN_M From Vk (V) to 0 (V)
By applying a ramp voltage that falls slowly,
The wall voltage on the surface of the body 11 (11r, 11b, 11g)
In this state, all the sustain electrodes 5 and the scan electrodes 4
(SUS₁ And SCN₁ Between and SUS_Two And SCN _Two 
Between,…, SUS_M And SCN_M Between) and protective film
The polarity of the wall voltage on the surface of the layer 3 is reversed.

Next, during the writing period, all data
Electrode SUS₁ ~ SUS_M Is maintained at Vq (V).
Also, all scan electrodes SCN₁ ~ SCN_M Once Vs
(V) and correspond to the discharge cells to be displayed in the first row.
Predetermined data electrode D₁ ~ D_N Positive writing pal
Voltage Vd (V), and the scan electrodes SCN of the first row are applied.
₁ Scan pulse from Vs (V) to 0 (V)
When a voltage -Vs (V) is applied, a predetermined data electrode D₁ 
~ D_N Table of phosphors 11 (11r, 11b, 11g) above
The surface voltage is applied to the wall voltage and the write pulse voltage Vd (V) is applied.
The data electrode D₁ ~ D_N And the second
Scan electrode SCN on the first row₁ Write at the intersection with
Discharge occurs. Next, the discharge cells to be displayed in the second row are
Corresponding predetermined data electrode D₁ ~ D_N Write positive polarity to
A pulse voltage Vd (V) is applied, and the scan electrodes S on the second row are applied.
CN_Two From negative Vs (V) to 0 (V)
When a loose voltage -Vs (V) is applied, a predetermined data electrode
D₁ ~ D_N Upper phosphor 11 (11r, 11b, 11g)
The surface voltage is written into the wall voltage and the pulse voltage Vd (V) is
The data electrode D₁ ~ D_N When
Scan electrode SCN in second row _Two Write at the intersection with
Only discharge occurs. In the same way, continue the scanning drive operation.
And finally correspond to the discharge cells to be displayed in the Mth row.
Predetermined data electrode D ₁ ~ D_N Positive write pulse
A voltage Vd (V) is applied, and the scan electrode SCN of the M-th row is applied._M 
Scan pulse voltage from Vs (V) to 0 (V)
When the voltage -Vs (V) is applied, a predetermined data electrode D₁ ~
D_N Surface of the upper phosphor 11 (11r, 11b, 11g)
Is applied to the wall voltage and the write pulse voltage Vd (V) is applied.
The data electrode D₁ ~ D_N And M
Scan electrode SCN in row_M Write at the intersection with
Electricity occurs.

[0007] Next, in the sustain period, all scan electrodes SCN ₁ ~SCN _M and all the sustain electrodes SUS ₁ to SU
After holding in the S _M once 0 (V), first, sustain pulse voltage Vm of positive polarity to all the scanning electrodes SCN ₁ ~SCN _M
Applying a (V), the scanning electrode SCN ₁ at the intersection portion that caused the address discharge ～SCN _M and the sustain electrodes SU
Sustain discharge occurs between S _{1 and} SUS _M. Next, by applying a positive sustain pulse voltage Vm (V) to all the sustain electrodes SUS ₁ ~SUS _M, in the intersection portion that caused the address discharge, the scanning electrodes SCN ₁ ~SCN _M and sustain electrodes SUS ₁ ~ Sustain discharge occurs again with SUS _M. Further, subsequently, all the scan electrodes SCN _{1 to} SCN _M
If by applying all the sustain electrodes SUS ₁ ~SUS _M and the positive polarity sustain pulse voltage Vm (V) is alternately sustain discharge occurs continuously. Light emitted by the sustain discharge is used for display on a panel.

Next, in the erasing period, the erasing discharge is performed by applying a ramp voltage Ve (V) which gradually rises from 0 (V) to Ve (V) to all sustain electrodes SUS _{1 to} SUS _M. To stop the discharge. With the above operation, one screen of the AC type plasma display panel is displayed.

Here, the operation of forming a wall voltage on the phosphor surface during the initialization period and the operation of writing discharge during the writing period will be described in detail again.

[0010] Figure 9, in the above-mentioned initialization period, red on all the scanning electrodes SCN ₁ ~SCN voltage waveforms of the ramp voltage Vscn applied to the _M data electrodes D ₁ to D _N,
The wall voltages Vwr, Vwb, Vwg respectively formed on the surfaces of the blue and green phosphors 11r, 11b, 11g are shown. The weak discharge due to the application of the ramp voltage during the above-described initialization period is caused by the surface of the protective film layer 3 on the scan electrode 4 on the anode side and the data electrode 9 on the scan electrode 4 as shown by the arrow in the direction of current flow in FIG. Is a discharge in which the surface of the phosphor 11 is on the cathode side. Accordingly, the value of the discharge voltage at this time depends on the physical and electrical properties of the surfaces of the phosphors 11 (11r, 11b, 11g) of the respective colors on the cathode side, so that the red, blue and green phosphors 11r , 11b, and 11g are different in the discharge voltage between the discharge cells. Here, as shown in FIG. 11, red, blue, and green phosphors 11r, 11b, and 11 respectively.
g of the phosphor 11r on the data electrode 9 of the discharge cell having g.
The discharge voltages between the surfaces of the protective films 11b and 11g and the surface of the protective film layer 3 on the scan electrode 4 are respectively represented by Vbr, Vbb and Vb.
g, for example, Vbr <Vbb <Vbg.

As shown in FIG. 9, during the initialization period,
First, the lamp voltage Vscn is set to Vj at time t0.
Starting from (V), rise slowly over time. At time t1, the lamp voltage Vscn changes from the surface of the protective film layer 3 on the scan electrode 4 to the red phosphor 11 on the data electrode 9.
When the discharge voltage Vbr (V) for discharging in the direction in which the current flows on the surface of r reaches between the surface of the protective film layer 3 on the scan electrode 4 and the surface of the red phosphor 11 r on the data electrode 9. , A weak discharge starts, and as the lamp voltage Vscn rises, the voltage between the surface of the protective film layer 3 on the scan electrode 4 and the surface of the red phosphor 11r on the data electrode 9 is reduced to the discharge voltage Vb.
The weak discharge continues while maintaining the voltage at r (V), and the wall voltage Vwr (V) is applied to the surface of the red phosphor 11 r on the data electrode 9.
Begins to accumulate. Similarly, at time t2, a discharge voltage Vbb (V) when the lamp voltage Vscn discharges in a direction in which a current flows from the surface of the protective film layer 3 on the scan electrode 4 to the surface of the blue phosphor 11b on the data electrode 9. ),
A weak discharge starts between the surface of the protective film layer 3 on the scan electrode 4 and the surface of the blue phosphor 11b on the data electrode 9, and as the lamp voltage Vscn increases, the protective film layer on the scan electrode 4 increases. 3 and the voltage between the surface of the blue phosphor 11b on the data electrode 9 and the discharge voltage Vbb (V), the weak discharge continues, and the blue phosphor 11b on the data electrode 9 is maintained.
, The wall voltage Vwb (V) starts to accumulate on the surface of the substrate. Similarly, at time t3, the discharge voltage Vbg at the time when the lamp voltage Vscn discharges in the direction in which current flows from the surface of the protective film layer 3 on the scan electrode 4 to the surface of the green phosphor 11g on the data electrode 9 is applied. When the voltage reaches (V), a weak discharge starts between the surface of the protective film layer 3 on the scan electrode 4 and the surface of the green phosphor 11g on the data electrode 9, and the scan is performed with an increase in the lamp voltage Vscn. The weak discharge continues while the voltage between the surface of the protective film layer 3 on the electrode 4 and the surface of the green phosphor 11g on the data electrode 9 is maintained at the discharge voltage Vbg (V),
The wall voltage Vw is applied to the surface of the green phosphor 11g on the data electrode 9.
g (V) begins to accumulate.

At time t4, when the lamp voltage Vscn reaches Vp (V) and the rise of the lamp voltage Vscn stops, the wall voltages accumulated on the surfaces of the red, blue, and green phosphors 11r, 11b, and 11g, respectively. Vwr (V), Vwb
(V) and Vwg (V) are Vp−Vbr (V),
Vp−Vbb (V) and Vp−Vbg (V). Further, the lamp voltage Vscn is equal to Vk at time t5.
From (V) to 0 (V) at time t6, the wall voltages Vp-Vbr (V), Vp-Vbb
(V) and Vp−Vbg (V) are both data electrodes 9
The value of Vp (V) is set such that the current is lower than the discharge voltage of the discharge in which a current flows from the surfaces of the upper phosphors 11r, 11b, and 11g toward the surface of the protective film layer 3 on the scan electrode 4. Therefore, no discharge occurs, and these wall voltages Vp−
Vbr (V), Vp-Vbb (V), Vp-Vbg
(V) remains accumulated on the surfaces of the phosphors 11r, 11b, and 11g of each color from the time t6 until the writing operation in the next writing period.

FIGS. 12A and 12B show the relationship between the discharge start voltage of the write discharge, the wall voltage, and the applied write pulse voltage during the write period.

FIG. 12A shows a write pulse voltage Vd applied to the data electrode 9 in a write operation during a write period.
(V) is not applied, and in the initialization operation, the wall voltage of the surface of any color phosphor on the data electrode 9, that is, Vp-Vbr (V), Vp-Vbb
(V) and Vp-Vbg (V) also indicate that they did not reach the lowest discharge start voltage Vign (V) of the write discharge. Therefore, no write discharge occurs in the discharge cells in this state. Here, in order to stably satisfy this condition, the discharge start voltages Vign (V) and Vpd
(V) and the accumulated wall voltage Vp-Vbr (V), Vp-
Vp-Vbr (V), Vp-Vbr (V), Vp-Vbg (V)
Operating conditions during the initialization period such that the maximum wall voltage of Vp-Vbb (V) and Vp-Vbg (V) is lower than the lowest discharge start voltage Vign (V) by the off-margin Voff (V). And Vp (V). In this case, the wall voltage Vp-Vbr on the surface of the red phosphor 11r
(V) so that (V) is lower than the lowest discharge start voltage Vign (V) by the off-margin Voff (V).
The value of (V) is set.

FIG. 12B shows a write pulse voltage Vd applied to the data electrode 9 in a write operation during a write period.
(V) indicates a state in which the phosphors 11r, 11r of any color on the data electrode 9 are in the initialization operation.
b, wall voltage on the surface of 11 g, that is, Vp−Vbr
(V), Vp-Vbb (V), and Vp-Vbg (V) are all added with the write pulse voltage Vd (V), which exceeds the maximum discharge start voltage Vpd (V) of the write discharge. ing. Therefore, write discharge occurs in the discharge cells in this state. Here, similarly, in order to stably satisfy this condition, Vp−Vbr + Vd
(V), Vp−Vbb + Vd (V), Vp−Vbb + V
The minimum voltage of d (V) is the highest discharge starting voltage Vp
The value of the write pulse voltage Vd (V) is set so as to be higher than d (V) by the ON margin Von (V). In this case, the wall voltage Vp−
Vp−Vbg + Vd (V) obtained by adding the write pulse voltage Vd (V) to Vbg (V) is the highest discharge start voltage Vp
The value of Vd (V) is set so as to be higher than d (V) by the ON margin Von (V).

From the above description, the write pulse voltage Vd
Conditions for the value of (V) are as follows (1) to (3) with reference to FIG.

Vign = Voff + (Vp−Vbr) (1) Vpd + Von = (Vp−Vbg) + Vd (2) (Vp−Vbr) − (Vp−Vbg) = Vbg−Vbr = Vdif (3) Therefore, the value of the write pulse voltage Vd (V) is as shown in the following (4) from the above (1) to (3).

Vd = (Vpd−Vign) + Von + Voff + Vdif (4) Here, the value of (Vpd−Vign) (V) is the size and shape of the discharge cell in the panel, the surface state of the protective film layer 3, and the like. Von (V) and Vof
The value of f (V) is a value determined as an operation margin for achieving operation stability, and the value of Vdif (V) is, for example, the value between the red phosphor 11r and the green phosphor 11g in this case. Like the discharge voltage difference, the value is determined from the physical and electrical characteristics of the phosphor 11.

In this manner, the value of the write pulse voltage Vd (V) applied to the data electrode 9 is set, and a discharge cell that generates a write discharge and a discharge cell that does not generate a write discharge during a write period are selected. Only the discharge cells in which the write discharge has occurred generate a sustain discharge in the next sustain period, and display one screen of the panel.

[0020]

However, in the conventional panel described above, the initializing discharge during the initializing period is
This is a discharge in which a current flows from the protective film layer 3 on the scanning electrode 4 to the surface of the phosphor 11 of each color on the data electrode 9.
Since the surface of No. 1 functions as a cathode, there is a problem that the discharge voltage of the write discharge is greatly different between the discharge cells of each color.

That is, as described above, the set write pulse voltage Vd (V) = (Vpd−Vign) + V
On + Voff + Vdif (V), (Vpd−
(Vign) (V) is a normal voltage variation of a panel having a large number of discharge cells, and Von (V), Voff
(V) is an operation margin necessary for a display device using a panel to operate stably. However, Vdif (V)
Is a value determined from the physical and electrical characteristics of the phosphor 11 like the difference in discharge voltage between the red phosphor 11r and the green phosphor 11g in this case, and the value of this difference is large. It is a problem. For example, in a prototype panel of 42 ″, 480 rows × 852 columns, Vdif = 30 (V), (Vp
d-Vign) = 20 (V). Von =
In the case of 10 (V) and Voff = 10 (V), the value of the write pulse voltage Vd (V) must be set to 70 (V). Normally, an IC used for a drive circuit for supplying a write pulse voltage Vd (V) to the data electrode 9 is as follows:
The manufacturing process is greatly different with a withstand voltage of 50 (V) as a branch point. Therefore, the write pulse voltage Vd is applied to the data electrode 9.
The price of the IC used for the drive circuit for supplying (V) is significantly different, and the reactive power generated when the write pulse voltage Vd (V) is supplied to the data electrode 9 is equal to the write pulse voltage Vd (V). ) Is proportional to the square of the value, and therefore, there is a problem that the cost and power consumption of the driving circuit of the data electrode 9 increase.

The present invention has been made to solve the above-mentioned problems in the prior art, and has as its object to provide an AC type plasma display panel capable of reducing the cost and power consumption of a display device. I do.

[0023]

In order to achieve the above object, an AC-type plasma display panel according to the present invention has a structure in which a plurality of scan electrodes and sustain electrodes form a pair while being covered with a dielectric layer. A plurality of data electrodes provided in a state covered by the first insulating substrate and the insulating layer,
A second insulating substrate in which phosphors of different emission colors are sequentially formed between a plurality of partition walls provided on the insulating layer, wherein the first insulating substrate and the second insulating substrate are An AC-type plasma display panel disposed so as to face a discharge space so that the scan electrodes and sustain electrodes provided in a plurality of pairs are orthogonal to the plurality of data electrodes, Wherein the phosphor on the insulator layer at a portion facing between each pair of the scan electrode and the sustain electrode is removed. According to the configuration of the AC type plasma display panel, the write pulse voltage to the data electrode can be considerably reduced in the operation during the write period, so that the IC used in the drive circuit for supplying the write pulse voltage to the data electrode can be used. Cost and reactive power can be reduced. As a result, in the display device using the AC plasma display panel, cost and power consumption can be reduced.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described more specifically with reference to embodiments.

FIG. 1 is a block diagram of an AC power supply according to an embodiment of the present invention.
FIG. 1 is a partially cutaway perspective view showing a plasma display panel of a type (hereinafter, may be abbreviated as “panel”). As shown in FIG. 1, on a first insulating substrate 1, a plurality of scan electrodes 4 and a plurality of sustain electrodes 5 are formed in parallel while being covered with a dielectric layer 2 and a protective film layer 3. It is provided in. A light-shielding layer 6 is provided between each pair of the scanning electrode 4 and the sustaining electrode 5 forming a pair. On the other hand, a plurality of data electrodes 9 are provided on the second insulating substrate 7 while being covered with the insulator layer 8. A plurality of barrier ribs 10 are provided on the insulator layer 8 between the data electrodes 9 in parallel with the data electrodes 9. Further, a portion of the surface of the insulator layer 8 between the partition walls 10 except for a portion facing the light-shielding layer 6 is provided with a phosphor 11.
Are provided in an intermittent stripe shape. The first insulating substrate 1 and the second insulating substrate 7 are opposed to each other with the discharge space 12 interposed therebetween so that a plurality of pairs of the scan electrode 4 and the sustain electrode 5 are orthogonal to the data electrodes 9. I have. In this panel, the area of the discharge space 12 corresponding to the intersection of a pair of the scan electrode 4 and the sustain electrode 5 and one of the data electrodes 9 constitutes one discharge cell. In addition, discharge space 1
2 includes helium, neon, argon as a discharge gas,
A type of xenon or a mixed gas thereof is enclosed. In the phosphor 11, a combination of a pair of phosphors 11r, 11b, and 11g that emit red, blue, and green, respectively, is arranged in the order of intermittent stripes adjacent to each other with the partition wall 10 interposed therebetween.

As the first and second insulating substrates 1 and 7,
A glass substrate or the like can be used.

As the material of the dielectric layer 2, a transparent insulating material such as glass can be used, and as the material of the protective film layer 3, magnesium oxide or the like can be used.

As a material of the light-shielding layer 6, glass containing black pigment, glass containing metal oxide, or the like can be used. As a material for the insulator layer 8, glass, glass containing metal oxide, or the like can be used.

As the material of the partition 10, glass, metal oxide, or the like can be used.

The material of the data electrode 9 can be silver or the like, and the material of the scan electrode 4 and the sustain electrode 5 can be a composite of silver and a transparent material such as SnO ₂ or ITO. .

The difference between the panel according to the prior art and the panel according to the present embodiment lies in the arrangement of the phosphor 11. That is, in the prior art panel, the phosphors 11 (11r, 11b, 1
1g) is provided in a stripe shape without any break,
In the panel of the present embodiment, a portion facing between each pair of scan electrode 4 and sustain electrode 5 forming a pair of surfaces of insulator layer 8 between partition walls 10, that is, a portion facing light blocking layer 6. The insulator layer 8 is exposed to the
(11r, 11b, 11g) are removed (a state in which intermittent stripe-shaped phosphors 11 are provided).

Since the electrode arrangement of this panel is the same as that shown in FIG. 7, its description is omitted.

Next, a method of driving the AC plasma display panel according to the present embodiment having the above-described configuration will be described. The operation drive timing chart is the same as that shown in FIG. However, there is a difference in the operation, so the difference will be described in detail, and the description of the other points will be omitted.

First, during the initialization period, all the maintenance
Extreme SUS₁ ~ SUS_M And data electrode D₁ ~ D_N To 0
(V) and all the scanning electrodes SCN₁ ~ SCN_M To
Lamp power gradually rising from Vj (V) to Vp (V)
By applying pressure, data is applied to all discharge cells.
Data electrode D₁ ~ D_N Phosphor 1 facing upper light shielding layer 6
The wall voltage is applied to the surface of the insulator layer 8 where no 1 is provided.
Between the sustain electrodes 5 and the scanning electrodes 4 at the same time.
(SUS₁ And SCN₁ Between and SUS_Two And SCN _Two With
Between, SUS_M And SCN_M Between) and protective film layer 3
Accumulates wall voltage on the surface of Thereafter, all the sustain electrodes S
US₁ ~ SUS_M Is maintained at Vq (V), and all scanning voltages are
Extreme SCN₁ ~ SCN_M Gradually from Vk (V) to 0 (V)
Insulation by applying ramp voltage
While maintaining the wall voltage on the surface of layer 8, all
Between the holding electrode 5 and the scanning electrode 4 (SUS₁ And SCN₁ With
SUS_Two And SCN_Two Between,…, SUS_M And S
CN_M Between the surface voltage of the protective film layer 3 and the polarity of the wall voltage.
Invert.

Next, during the writing period, all data
Electrode SUS₁ ~ SUS_M Is maintained at Vq (V).
Also, all scan electrodes SCN₁ ~ SCN_M Once Vs
(V) and correspond to the discharge cells to be displayed in the first row.
Predetermined data electrode D₁ ~ D_N Positive writing pal
Voltage Vd (V), and the scan electrodes SCN of the first row are applied.
₁ Scan pulse from Vs (V) to 0 (V)
When a voltage -Vs (V) is applied, a predetermined data electrode D₁ 
~ D_N The voltage on the surface of the exposed insulator layer 8 on the upper
The write pulse voltage Vd (V) increases when applied.
And a predetermined data electrode D ₁ ~ D_N And the first row of scan electrodes
SCN₁ A write discharge occurs at the intersection with. Next
The predetermined data corresponding to the discharge cell to be displayed on the second row is
Electrode D₁ ~ D_NHas a positive write pulse voltage Vd
(V) to apply the second row of scan electrodes SCN. _Two To Vs
A negative scanning pulse voltage -V from (V) to 0 (V)
When s (V) is applied, a predetermined data electrode D₁ ~ D_N Up
The voltage on the surface of the exposed insulator layer 8 is written to the wall voltage
Since the pulse voltage Vd (V) increases with the addition of the pulse voltage Vd,
Data electrode D₁ ~ D_N And the scanning electrode SCN in the second row_Two When
A write discharge occurs at the intersection of. Run in the same way
Continue the inspection-driven operation, and finally display the M-th line
Data electrode D corresponding to the discharge cell₁ ~ D_N To
A positive write pulse voltage Vd (V) is applied,
Scan electrode SCN in row_M From Vs (V) to 0 (V)
When a negative scanning pulse voltage -Vs (V) is applied,
Predetermined data electrode D ₁ ~ D_N Of the exposed insulator layer 8
The surface voltage is written into the wall voltage and the pulse voltage Vd (V) is
The data electrode D₁ ~ D_N When
Scan electrode SCN in the M-th row_M Write at the intersection with
Only discharge occurs.

The operation in the next sustain period and erase period is the same as that described in the prior art, and the description is omitted.

Here, the operation of forming a wall voltage on the surface of the insulator layer during the initialization period and the operation of writing discharge during the writing period will be described in detail again.

[0038] Figure 2, in the initialization period described above, the surface of all the scanning electrodes SCN ₁ ~SCN voltage waveforms of the ramp voltage Vscn applied to the _M data electrodes D ₁ to D _N on the insulating layer 8 5 shows the formed wall voltage Vw.

As shown in FIG. 2, during the initialization period,
First, the lamp voltage Vscn is set to Vj at time t0.
Starting from (V), rise slowly over time. At time t1, the lamp voltage Vscn reaches the discharge voltage Vb (V) at which the discharge is performed in the direction in which current flows from the surface of the protective film layer 3 on the scan electrode 4 to the surface of the exposed insulator layer 8 on the data electrode 9. Then, a weak discharge starts between the surface of the protective film layer 3 on the scan electrode 4 and the exposed surface of the insulator layer 8 on the data electrode 9, and as the lamp voltage Vscn rises, The voltage between the surface of the protective film layer 3 and the surface of the insulator layer 8 on the data electrode 9 is defined as a discharge voltage Vb (V).
, The weak voltage continues, and the wall voltage Vw (V) starts to accumulate on the surface of the insulator layer 8 on the data electrode 9.
At time t2, when the lamp voltage Vscn reaches Vp (V), the wall voltage Vw (V) becomes Vp-Vb (V). Further, although the ramp voltage Vscn decreases from Vk (V) at time t3 toward 0 (V) at time t4, the wall voltage Vw = Vp−Vb (V) is reduced to the exposed insulator layer on the data electrode 9. 8 is set so as to be lower than the discharge voltage of the discharge in which the current flows from 8 to the surface of the protective film layer 3 on the scan electrode 4, so that no discharge occurs.
The wall voltage Vw = Vp−Vb (V) is the phosphor 11 of each color after the time t4 until the writing operation in the next writing period.
Remains on the surface of the surface.

At this time, the weak discharge due to the application of the lamp voltage during the above-described initialization period is caused by the surface of the protective film layer 3 on the scan electrode 4 as shown by the arrow in the direction of current flow in FIG. In this discharge, the exposed surface of the insulator layer 8 on the data electrode 9 is on the cathode side. Therefore, red, blue,
In the discharge cells provided with the green phosphors 11r, 11b, and 11g, the value of the discharge voltage at this time depends on the physical and electrical properties of the surface of the exposed insulator layer 8 on the cathode side, Since the exposed surface of the insulator layer 8 is the same in each discharge cell, the discharge voltage is equal in each discharge cell. That is, as shown in FIG. 4, the discharge voltage values between the surface of the protective film layer 8 on the scan electrode 4 and the exposed surface of the insulator layer 8 on the data electrode 9 are red, blue, and green, respectively. Vb (V) between the discharge cells having the phosphors 11r, 11b, and 11g.

FIGS. 5A and 5B show the discharge start voltage of the writing discharge and the exposed insulator layer 8 during the writing period.
Shows the relationship between the wall voltage on the surface and the applied write pulse voltage. In general, the discharge starting voltage is specific to a discharge cell, but is different for each discharge cell in a panel. Therefore, when viewed from the whole panel, the lowest discharge starting voltage Vi
It is necessary to consider the distribution width from gn (V) to the highest firing voltage Vpd (V).

FIG. 5A shows a write pulse voltage Vd applied to the data electrode 9 in a write operation during a write period.
(V) is not applied, and in the initialization operation, the wall voltage Vp−Vb (V) on the exposed surface of the insulator layer 8 on the data electrode 9 is reduced to the minimum discharge start voltage Vign ( V) has not been reached. Therefore, no write discharge occurs in the discharge cells in this state. Here, in order to stably satisfy this condition, the discharge starting voltages Vign (V) and Vpd (V)
And the accumulated wall voltage Vp-Vb (V) during the panel operation and the variation over time are taken into account, and the wall voltage Vp-Vb (V) is taken into account.
(V) so that (V) is lower than the lowest discharge start voltage Vign (V) by the off-margin Voff (V).
The value of (V) is set.

FIG. 5B shows a write pulse voltage Vd applied to the data electrode 9 during a write operation during a write period.
(V) is applied, and in the initialization operation, the write pulse voltage Vd (V) is added to the wall voltage Vp−Vb (V) on the exposed surface of the insulator layer 8 on the data electrode 9.
And the highest discharge start voltage Vpd of the write discharge
(V) is exceeded. Therefore, write discharge occurs in the discharge cells in this state. here,
Similarly, in order to stably satisfy this condition, Vp
-Vb + Vd (V) is the highest discharge starting voltage Vpd (V)
Higher than the on-margin Von (V) by
The voltage of the write pulse voltage Vd (V) is set.

In this manner, the value of the write pulse voltage Vd (V) applied to the data electrode 9 is set, and a discharge cell that generates a write discharge and a discharge cell that does not generate a write discharge during a write period are selected. Only the discharge cells in which the write discharge has occurred generate a sustain discharge in the next sustain period, and display one screen of the panel.

From the above description, the write pulse voltage Vd
Conditions for the value of (V) are as shown in (5) and (6) below with reference to FIG.

Vign = Voff + (Vp−Vb) (5) Vpd + Von = (Vp−Vb) + Vd (6) Accordingly, the value of the write pulse voltage Vd (V) is determined by the above (5), (6) ) Is as shown in (7) below.

Vd = (Vpd−Vign) + Von + Voff (7) Here, the value of (Vpd−Vign) (V) is the size and shape of the discharge cell in the panel, the surface state of the protective film layer 3, and the like. Von (V) and Vof
The value of f (V) is a value determined as an operation margin for achieving operation stability. For example, 42 ", 480 lines x
In the prototype panel of 852 rows, (Vpd-Vign)
= 20 (V). Von = 10 (V), V
When off = 10 (V), a reliable writing operation and a stable panel display operation were obtained even when the value of the writing pulse voltage Vd was set to 40 (V).

Therefore, the price of the IC used for the drive circuit for supplying the write pulse voltage Vd (V) to the data electrode 9 is reduced by half compared with the conventional one, and the write pulse voltage Vd (V ) Is reduced in proportion to the square of the value of the write pulse voltage Vd (V), and is therefore reduced to one third as compared with the prior art. As a result, in the display device using the panel of this embodiment, cost and power consumption can be reduced.

[0049]

As described above, according to the present invention,
In the operation during the writing period, the writing pulse voltage to the data electrode can be considerably reduced, so that the cost and the reactive power of the IC used in the drive circuit that supplies the writing pulse voltage to the data electrode can be reduced. . As a result, in the display device using the AC plasma display panel, cost and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a partially cutaway perspective view showing an AC type plasma display panel according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between a voltage waveform of a lamp voltage applied during an initialization period and a wall voltage in the AC plasma display panel according to one embodiment of the present invention;

FIG. 3 is a cross-sectional view taken along the line AA ′ of FIG. 1 showing a state of weak discharge due to application of a lamp voltage during an initialization period.

FIG. 4 is a sectional view taken along line BB ′ of FIG. 1 showing a discharge voltage of the setup discharge.

FIG. 5 is a diagram showing a relationship between a discharge starting voltage of a write discharge in a write period, a wall voltage of an exposed insulator layer surface, and an applied write pulse voltage in the AC plasma display panel according to one embodiment of the present invention;

FIG. 6 is a partially cutaway perspective view showing an AC type plasma display panel in the prior art.

FIG. 7 is an electrode arrangement diagram of an AC type plasma display panel.

FIG. 8 is an operation drive timing chart of an AC type plasma display panel.

FIG. 9 is a diagram showing a relationship between a voltage waveform of a lamp voltage applied during an initialization period and a wall voltage in an AC plasma display panel according to the related art.

FIG. 10 is a cross-sectional view taken along the line CC ′ in FIG. 6, showing a state of a weak discharge due to application of a lamp voltage during an initialization period.

FIG. 11 shows a discharge voltage DD of FIG.
Sectional view

FIG. 12 is a diagram showing a relationship between a discharge starting voltage of a write discharge, a wall voltage on a phosphor surface, and an applied write pulse voltage in a write period in a conventional AC plasma display panel.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 First insulating substrate 2 Dielectric layer 3 Protective film layer 4 Scan electrode 5 Sustain electrode 6 Light shielding layer 7 Second insulating substrate 8 Insulator layer 9 Data electrode 10 Partition wall 11 Phosphor 12 Discharge space

Claims (1)

[Claims] A first insulating substrate provided with a plurality of scanning electrodes and sustaining electrodes in pairs in a state covered by a dielectric layer; and a plurality of data in a state covered by the insulating layer. An electrode, and a second insulating substrate in which phosphors having different emission colors are sequentially formed between a plurality of partitions provided on the insulator layer; and the first insulating substrate and the second insulating substrate. An AC-type plasma display panel disposed so as to oppose each other with a discharge space interposed therebetween such that the plurality of pairs of scan electrodes and sustain electrodes are orthogonal to the plurality of data electrodes. An AC-type plasma display panel, wherein the phosphor on the insulator layer at a portion facing the pair of the scanning electrode and the sustaining electrode is removed.