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JP2001291670A - Semiconductor manufacturing equipment - Google Patents

Semiconductor manufacturing equipment

Info

Publication number
JP2001291670A
JP2001291670A JP2000107948A JP2000107948A JP2001291670A JP 2001291670 A JP2001291670 A JP 2001291670A JP 2000107948 A JP2000107948 A JP 2000107948A JP 2000107948 A JP2000107948 A JP 2000107948A JP 2001291670 A JP2001291670 A JP 2001291670A
Authority
JP
Japan
Prior art keywords
wafer
heat insulating
semiconductor manufacturing
wafers
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000107948A
Other languages
Japanese (ja)
Inventor
Masakatsu Minami
南  政克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Denki Electric Inc
Original Assignee
Hitachi Kokusai Electric Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Kokusai Electric Inc filed Critical Hitachi Kokusai Electric Inc
Priority to JP2000107948A priority Critical patent/JP2001291670A/en
Publication of JP2001291670A publication Critical patent/JP2001291670A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To increase the evenness of a film thickness over a plurality of substrates in a semiconductor manufacturing device, in which a plurality of substrates are stacked and held vertically and are processed. SOLUTION: In the semiconductor manufacturing device, a plurality of wafers 4 and dummy wafers 5 disposed above and below the wafers 4 are stacked and held in the downward direction in a boat 3 disposed in a reaction tube 1, and a plurality of heat insulating plates 6 are stacked and held in the downward direction below the wafers. In such a semiconductor manufacturing apparatus, the dummy wafers 5 and the heat insulating plates 6 are disposed successively.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、反応管の外側に基
板加熱用のヒータを備えた半導体製造装置に関する。
The present invention relates to a semiconductor manufacturing apparatus provided with a heater for heating a substrate outside a reaction tube.

【0002】[0002]

【従来の技術】従来の半導体製造装置は、基板を処理す
る反応管と、反応管の外側に該反応管を取り囲んで設け
た基板加熱用のヒータと、反応管の内側に配置され、処
理すべき多数の基板を垂直方向に積層して保持するボー
ト等を備えてなる。
2. Description of the Related Art A conventional semiconductor manufacturing apparatus includes a reaction tube for processing a substrate, a heater for heating a substrate provided outside the reaction tube and surrounding the reaction tube, and a processing tube disposed inside the reaction tube for processing. It is provided with a boat or the like that holds a number of substrates to be stacked in the vertical direction and holds them.

【0003】図3は、従来の半導体製造装置におけるボ
ートの断面図である。なお、半導体製造装置の全体構成
については、図2を参照のこと(後述)。
FIG. 3 is a sectional view of a boat in a conventional semiconductor manufacturing apparatus. For the overall configuration of the semiconductor manufacturing apparatus, see FIG. 2 (described later).

【0004】4は製品となる基板、例えば半導体ウェ
ハ、5はダミーウェハ、6は断熱板、3はウェハ4、ダ
ミーウェハ5、断熱板6を垂直方向に積層して保持する
ボート、11はウェハ領域、12はダミーウェハ領域、
13は製品ウェハ領域、14は断熱板領域、10はウェ
ハ領域11と断熱板領域14との間の(ダミーウェハ5
と断熱板6との間の)空間である。
Reference numeral 4 denotes a product substrate, for example, a semiconductor wafer, 5 denotes a dummy wafer, 6 denotes a heat insulating plate, 3 denotes a boat for vertically stacking and holding the wafer 4, dummy wafer 5, and heat insulating plate 6, 11 denotes a wafer area, 12 is a dummy wafer area,
13 is a product wafer region, 14 is a heat insulating plate region, 10 is a space between the wafer region 11 and the heat insulating plate region 14 (dummy wafer 5).
And the heat insulating plate 6).

【0005】ボート3は、製品となる複数のウェハ4の
上下に所定の枚数配置されるダミーウェハ5を含む多数
のウェハを垂直方向に積層して保持し、その下方に、複
数の断熱板6を垂直方向に積層して保持するようになっ
ている。例えば、製品ウェハ4を150枚、製品ウェハ
4の上方のダミーウェハ5を5枚、製品ウェハ4の下方
のダミーウェハ5を10枚、断熱板6を6枚保持する。
なお、断熱板6は、反応管の下方の炉口部における断熱
効果を得るため、また、該炉口部の温度を調整するため
に使用される。
[0005] The boat 3 vertically holds a large number of wafers including a predetermined number of dummy wafers 5 arranged above and below a plurality of wafers 4 as products, and holds a plurality of heat insulating plates 6 below the wafers. They are stacked vertically and held. For example, 150 product wafers 4, five dummy wafers 5 above the product wafer 4, ten dummy wafers 5 below the product wafer 4, and six heat insulating plates 6 are held.
The heat insulating plate 6 is used for obtaining a heat insulating effect in the furnace port below the reaction tube and for adjusting the temperature of the furnace port.

【0006】[0006]

【発明が解決しようとする課題】従来の上記のような半
導体製造装置においては、ウェハ領域11と断熱板領域
14との間には、例えば縦方向40mm程度の空間10
があった。この空間10は、ウェハ領域11の一番下に
配置されるダミーウェハ5より下には、ウェハ移載機が
移動できないという装置上の都合のために存在してい
た。
In the conventional semiconductor manufacturing apparatus as described above, a space 10 having a length of, for example, about 40 mm is provided between the wafer region 11 and the heat insulating plate region 14.
was there. This space 10 exists below the dummy wafer 5 arranged at the bottom of the wafer region 11 for the convenience of the apparatus that the wafer transfer machine cannot move.

【0007】従来の半導体製造装置では、この空間10
が存在するために、この空間10部で気相反応が起こり
やすく、また、この空間10部で反応ガスの流れが急激
に変化したり、不安定なガスの流れが生じる等の理由
で、製品ウェハ領域13の下方の領域のウェハ4の膜厚
均一性が低下するという課題があった。
In a conventional semiconductor manufacturing apparatus, this space 10
, Gas phase reaction is likely to occur in this space 10 part, and the reaction gas flow changes abruptly in this space 10 part, and unstable gas flow occurs. There is a problem that the film thickness uniformity of the wafer 4 in the region below the wafer region 13 is reduced.

【0008】本発明の目的は、複数の基板を垂直方向に
積層して保持し、処理する半導体製造装置において、複
数の基板全体にわたる膜厚均一性を向上できる半導体製
造装置を提供することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor manufacturing apparatus for stacking and holding a plurality of substrates in a vertical direction and processing the same so that the film thickness uniformity over the entire plurality of substrates can be improved. .

【0009】[0009]

【課題を解決するための手段】前記課題を解決するため
に、本発明の半導体製造装置は、複数の基板(ダミー基
板を含む)を垂直方向に積層して保持し、その下方に、
複数の断熱板を垂直方向に積層して保持する半導体製造
装置において、前記基板と前記断熱板とを連続して配置
させることを特徴とする。
In order to solve the above-mentioned problems, a semiconductor manufacturing apparatus of the present invention holds a plurality of substrates (including a dummy substrate) stacked vertically,
In a semiconductor manufacturing apparatus in which a plurality of heat insulating plates are vertically stacked and held, the substrate and the heat insulating plates are continuously arranged.

【0010】基板と断熱板とを連続して配置するという
のは、不要な気相反応や不安定なガスの流れを発生させ
る基板と断熱板との間の空間部をなくすことを意味す
る。
[0010] The continuous arrangement of the substrate and the heat insulating plate means eliminating a space between the substrate and the heat insulating plate, which generates an unnecessary gas phase reaction or an unstable gas flow.

【0011】例えば、一番下の基板と一番上の断熱板と
の間隔を、基板のピッチと略同じにする。
For example, the interval between the lowermost substrate and the uppermost heat insulating plate is made substantially equal to the pitch of the substrates.

【0012】また、例えば、基板に隣接する部分の断熱
板のピッチを、基板のピッチと略同じにする。
Further, for example, the pitch of the heat insulating plate in a portion adjacent to the substrate is made substantially the same as the pitch of the substrate.

【0013】また、例えば、部位により断熱板のピッチ
を異ならせる。
Further, for example, the pitch of the heat insulating plate is made different depending on the portion.

【0014】本発明では、複数の基板を垂直方向に積層
して保持し、処理する半導体製造装置において、基板と
その下方の断熱板とを連続して配置し、不要な気相反応
や不安定なガスの流れを発生させる空間部をなくすこと
により、複数の基板全体にわたる膜厚均一性が向上でき
る。
According to the present invention, in a semiconductor manufacturing apparatus in which a plurality of substrates are vertically stacked and held and processed, a substrate and a heat insulating plate below the substrate are continuously arranged to prevent unnecessary gas phase reactions and unstable operations. Eliminating the space for generating a flow of the gas can improve the uniformity of the film thickness over the plurality of substrates.

【0015】[0015]

【発明の実施の形態】以下、図面を用いて本発明の実施
の形態について詳細に説明する。なお、以下で説明する
図面で、同一機能を有するものは同一符号を付け、その
繰り返しの説明は省略する。
Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings described below, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

【0016】図2は、本発明の実施の形態の半導体製造
装置の全体構成を示す断面図である。
FIG. 2 is a sectional view showing the overall configuration of the semiconductor manufacturing apparatus according to the embodiment of the present invention.

【0017】1はウェハを処理する反応管、1aは外側
反応管、1bは内側反応管、16は反応管1の下方の炉
口部、2は反応管1の外側に反応管1を取り囲んで設け
たウェハ加熱用のヒータ、15はヒータの断熱層、4は
製品となる処理すべき多数の半導体ウェハ、5は反応条
件の不安定な領域に置かれるダミーウェハ、6は反応管
1の炉口部16における断熱効果を得、炉口部16の温
度を調整するための断熱板、3は反応管1の内側に配置
され、ウェハ4、ダミーウェハ5、断熱板6を垂直方向
に積層して保持するボート、7はボート3に設けられ、
ウェハ4、ダミーウェハ5、断熱板6を保持するための
保持突起、11はウェハ領域、12はダミーウェハ領
域、13は製品ウェハ領域、14は断熱板領域、8は反
応ガス導入手段、9は排気手段である。
1 is a reaction tube for processing a wafer, 1a is an outer reaction tube, 1b is an inner reaction tube, 16 is a furnace port below the reaction tube 1, and 2 is an outside of the reaction tube 1 surrounding the reaction tube 1. The provided heater for heating the wafer, 15 is a heat insulating layer of the heater, 4 is a large number of semiconductor wafers to be processed as products, 5 is a dummy wafer placed in an area where reaction conditions are unstable, and 6 is a furnace port of the reaction tube 1. A heat insulating plate for obtaining the heat insulating effect in the section 16 and adjusting the temperature of the furnace port 16 is disposed inside the reaction tube 1, and the wafer 4, the dummy wafer 5, and the heat insulating plate 6 are vertically stacked and held. Boat 7 is provided on boat 3,
Holding projections for holding the wafer 4, the dummy wafer 5, and the heat insulating plate 6, 11 are a wafer region, 12 is a dummy wafer region, 13 is a product wafer region, 14 is a heat insulating plate region, 8 is a reactive gas introducing unit, and 9 is an exhaust unit. It is.

【0018】図1は、図2の半導体製造装置におけるボ
ート3の拡大詳細断面図である。なお、図1におけるウ
ェハ4、ダミーウェハ5、断熱板6の間隔等の寸法は、
実際の寸法とは異なり、誇張して描かれている。
FIG. 1 is an enlarged detailed sectional view of the boat 3 in the semiconductor manufacturing apparatus of FIG. In addition, the dimension of the space | interval of the wafer 4, the dummy wafer 5, and the heat insulation board 6 in FIG.
Unlike actual dimensions, they are exaggerated.

【0019】Sは一番下のダミーウェハ5と一番上の断
熱板6との間隔、Pは第1のピッチ、Pは第2のピ
ッチで、P<Pである。P1はピッチが第1のピッ
チP である領域、P2はピッチが第2のピッチP
ある領域である。
S represents the lowermost dummy wafer 5 and the uppermost section.
Spacing with hot plate 6, P1Is the first pitch, P2Is the second pick
Switch, P1<P2It is. P1 is the first pitch
Chi-P 1, P2 has a pitch of the second pitch P2so
An area.

【0020】本実施の形態の半導体製造装置では、複数
のウェハ4およびダミーウェハ5を垂直方向に積層して
保持し、その下方に、複数の断熱板6を垂直方向に積層
して保持し、ウェハ領域11のウェハ4およびダミーウ
ェハ5と断熱板6とを連続して配置してある。すなわ
ち、図3に示した従来の装置における空間10のところ
に、ダミーウェハ5あるいは断熱板6を配置してある。
なお、前述のように、空間10のところには、ウェハ移
載機が移動できないため、この部分へのダミーウェハ5
あるいは断熱板6の投入は手で行なう。もしくはウェハ
移載機等を改良し、ウェハ移載機がこの部分にアクセス
できるようにして、ウェハ移載機により投入できるよう
にしてもよい。例えば、本実施の形態では、断熱板6は
従来と同様に6枚、従来の空間10(図3)のところに
ダミーウェハ5を5枚配置してある(なお、ダミーウェ
ハ5の代わりに、断熱板6を配置してもよい)。また、
その上方に従来と同様にダミーウェハ5を10枚、その
上方に製品ウェハ4を150枚、その上方にダミーウェ
ハ5を5枚配置してある。
In the semiconductor manufacturing apparatus of this embodiment, a plurality of wafers 4 and dummy wafers 5 are vertically stacked and held, and a plurality of heat insulating plates 6 are vertically stacked and held below the wafers 4 and dummy wafers 5. The wafer 4 and the dummy wafer 5 in the region 11 and the heat insulating plate 6 are continuously arranged. That is, the dummy wafer 5 or the heat insulating plate 6 is arranged at the space 10 in the conventional apparatus shown in FIG.
As described above, since the wafer transfer device cannot move to the space 10, the dummy wafer 5
Alternatively, the heat insulating plate 6 is manually charged. Alternatively, the wafer transfer device or the like may be improved so that the wafer transfer device can access this portion so that it can be loaded by the wafer transfer device. For example, in the present embodiment, six heat insulating plates 6 are arranged in the same manner as in the related art, and five dummy wafers 5 are arranged in the conventional space 10 (FIG. 3). 6 may be arranged). Also,
Above that, ten dummy wafers 5 are arranged in the same manner as in the prior art, 150 product wafers 4 are arranged above, and five dummy wafers 5 are arranged above.

【0021】本実施の形態では、一番下のダミーウェハ
5と一番上の断熱板6との間隔Sを、ウェハ4、ダミー
ウェハ5のピッチPと略同じにしてある。また、ダミ
ーウェハ5に隣接する上方の断熱板6のピッチを、ウェ
ハ4、ダミーウェハ5のピッチと略同じにしてある(ピ
ッチP)。また、断熱板6のピッチは、部位により異
なっており、ダミーウェハ5に隣接する上方の断熱板6
のピッチはP、下方のピッチはPで、P<P
ある。例えばPは5.2mm、Pは12mmであ
る。なお、図2において、断熱板6のピッチはすべて略
同一に描かれているが、詳細は図1に示すようになって
いる。
[0021] In this embodiment, the spacing S between the dummy wafer 5 at the bottom with heat insulating plate 6 at the top, the wafer 4, are made substantially the same as the pitch P 1 of the dummy wafer 5. The pitch of the upper heat insulating plate 6 adjacent to the dummy wafer 5 is substantially the same as the pitch of the wafer 4 and the dummy wafer 5 (pitch P 1 ). In addition, the pitch of the heat insulating plate 6 differs depending on the portion, and the upper heat insulating plate 6 adjacent to the dummy wafer 5.
Is P 1 , the lower pitch is P 2 , and P 1 <P 2 . For example P 1 is 5.2 mm, P 2 is 12 mm. In FIG. 2, the pitches of the heat insulating plates 6 are all substantially the same, but the details are as shown in FIG.

【0022】本実施の形態では、ダミーウェハ5と断熱
板6とを連続して配置し、不要な気相反応や不安定なガ
スの流れを発生させる空間部(従来の図3における空間
10)をなくすことにより、不要な気相反応を抑制し、
また、ガスの流れを安定化させることができるので、製
品となるウェハ4の下方の領域のウェハ4の膜厚均一性
が向上でき、複数の基板全体にわたる膜厚均一性が向上
できる。
In the present embodiment, the dummy wafer 5 and the heat insulating plate 6 are continuously arranged, and a space (a conventional space 10 in FIG. 3) for generating an unnecessary gas phase reaction and an unstable gas flow is formed. By eliminating unnecessary gas phase reactions,
Further, since the gas flow can be stabilized, the film thickness uniformity of the wafer 4 in the region below the product wafer 4 can be improved, and the film thickness uniformity over a plurality of substrates can be improved.

【0023】なお、断熱板6の形状、直径、厚さは、ウ
ェハ4およびダミーウェハ5の形状、直径、厚さと略同
様である。例えば、直径8インチ(200mm)の場合
は、厚さ2mm程度である。また、直径12インチ(3
00mm)の場合は、厚さ2mm〜4mm程度である。
断熱板6の材質は、例えば石英、あるいはSiCであ
る。
The shape, diameter and thickness of the heat insulating plate 6 are substantially the same as those of the wafer 4 and the dummy wafer 5. For example, when the diameter is 8 inches (200 mm), the thickness is about 2 mm. In addition, 12 inches in diameter (3
00 mm), the thickness is about 2 mm to 4 mm.
The material of the heat insulating plate 6 is, for example, quartz or SiC.

【0024】図1、図2に示したような本実施の形態の
半導体製造装置を使用して、シリコンからなる直径8イ
ンチ、厚さ約2mmのウェハ4の表面に、温度620
℃、圧力15Pa、使用反応ガスSiH、ガス流量2
00sccmの条件で、膜厚2500Åの多結晶シリコ
ン膜を形成したところ、製品ウェハ領域13の下方の領
域のウェハ4の膜厚均一性を±0.5%向上することが
できた。
Using the semiconductor manufacturing apparatus of the present embodiment as shown in FIGS. 1 and 2, a surface of a wafer 4 made of silicon having a diameter of 8 inches and a thickness of about 2 mm is heated to a temperature of 620.
° C, pressure 15Pa, used reaction gas SiH 4 , gas flow rate 2
When a polycrystalline silicon film having a film thickness of 2500 ° was formed under the condition of 00 sccm, the film thickness uniformity of the wafer 4 in the region below the product wafer region 13 could be improved by ± 0.5%.

【0025】以上本発明を実施の形態に基づいて具体的
に説明したが、本発明は前記実施の形態に限定されるも
のではなく、その要旨を逸脱しない範囲において種々変
更可能であることは勿論である。
Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various changes can be made without departing from the gist of the present invention. It is.

【0026】[0026]

【発明の効果】以上説明したように、本発明によれば、
複数の基板を垂直方向に積層して保持し、処理する半導
体製造装置において、複数の基板全体にわたる膜厚均一
性を向上させることができる。
As described above, according to the present invention,
In a semiconductor manufacturing apparatus that stacks, holds, and processes a plurality of substrates in a vertical direction, it is possible to improve the film thickness uniformity over the plurality of substrates.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態の半導体製造装置における
ボートの断面図である。
FIG. 1 is a sectional view of a boat in a semiconductor manufacturing apparatus according to an embodiment of the present invention.

【図2】本発明の実施の形態の半導体製造装置の全体構
成を示す断面図である。
FIG. 2 is a cross-sectional view illustrating an overall configuration of a semiconductor manufacturing apparatus according to an embodiment of the present invention.

【図3】従来の半導体製造装置におけるボートの断面図
である。
FIG. 3 is a sectional view of a boat in a conventional semiconductor manufacturing apparatus.

【符号の説明】[Explanation of symbols]

1…反応管、1a…外側反応管、1b…内側反応管、2
…ヒータ、3…ボート、4…ウェハ、5…ダミーウェ
ハ、6…断熱板、7…保持突起、8…反応ガス導入手
段、9…排気手段、11…ウェハ領域、12…ダミーウ
ェハ領域、13…製品ウェハ領域、14…断熱板領域、
15…ヒータの断熱層、16…炉口部。
DESCRIPTION OF SYMBOLS 1 ... Reaction tube, 1a ... Outer reaction tube, 1b ... Inner reaction tube, 2
... Heater, 3 ... Boat, 4 ... Wafer, 5 ... Dummy wafer, 6 ... Heat insulation plate, 7 ... Retention gas introduction means, 9 ... Exhaust means, 11 ... Wafer area, 12 ... Dummy wafer area, 13 ... Product Wafer area, 14 ... heat insulating plate area,
15: Heat insulation layer of heater, 16: Furnace opening.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】複数の基板を垂直方向に積層して保持し、
その下方に、複数の断熱板を垂直方向に積層して保持す
る半導体製造装置において、前記基板と前記断熱板とを
連続して配置させることを特徴とする半導体製造装置。
1. A plurality of substrates are vertically stacked and held,
In a semiconductor manufacturing apparatus which holds a plurality of heat insulating plates vertically stacked below the semiconductor manufacturing apparatus, the substrate and the heat insulating plates are continuously arranged.
JP2000107948A 2000-04-10 2000-04-10 Semiconductor manufacturing equipment Pending JP2001291670A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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US6849131B2 (en) * 2002-10-05 2005-02-01 Taiwan Semiconductor Manufacturing Co., Ltd Truncated dummy plate for process furnace
JP2006032386A (en) * 2004-07-12 2006-02-02 Hitachi Kokusai Electric Inc Heat treatment equipment
JP2007134518A (en) * 2005-11-10 2007-05-31 Hitachi Kokusai Electric Inc Heat treatment equipment
CN100388412C (en) * 2004-04-23 2008-05-14 上海华虹Nec电子有限公司 Method for improving filming homogeneity inside thick surface at double ends of furnace
JP2013069985A (en) * 2011-09-26 2013-04-18 Fuji Electric Co Ltd Method of manufacturing semiconductor device
JP2013080771A (en) * 2011-10-03 2013-05-02 Hitachi Kokusai Electric Inc Substrate processing apparatus and manufacturing method of semiconductor device
JP2014110305A (en) * 2012-11-30 2014-06-12 Toyota Motor Corp Semiconductor device manufacturing method
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Cited By (17)

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Publication number Priority date Publication date Assignee Title
US6849131B2 (en) * 2002-10-05 2005-02-01 Taiwan Semiconductor Manufacturing Co., Ltd Truncated dummy plate for process furnace
CN100388412C (en) * 2004-04-23 2008-05-14 上海华虹Nec电子有限公司 Method for improving filming homogeneity inside thick surface at double ends of furnace
JP2006032386A (en) * 2004-07-12 2006-02-02 Hitachi Kokusai Electric Inc Heat treatment equipment
JP2007134518A (en) * 2005-11-10 2007-05-31 Hitachi Kokusai Electric Inc Heat treatment equipment
JP2013069985A (en) * 2011-09-26 2013-04-18 Fuji Electric Co Ltd Method of manufacturing semiconductor device
JP2013080771A (en) * 2011-10-03 2013-05-02 Hitachi Kokusai Electric Inc Substrate processing apparatus and manufacturing method of semiconductor device
JP2014110305A (en) * 2012-11-30 2014-06-12 Toyota Motor Corp Semiconductor device manufacturing method
JPWO2016042663A1 (en) * 2014-09-19 2017-06-22 株式会社日立国際電気 Semiconductor device manufacturing method, substrate processing apparatus, and recording medium
WO2016042663A1 (en) * 2014-09-19 2016-03-24 株式会社日立国際電気 Semiconductor device manufacturing method, substrate processing device, and recording medium
US10032626B2 (en) 2014-09-19 2018-07-24 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device by forming a film on a substrate, substrate processing apparatus, and recording medium
KR20180075390A (en) * 2016-12-26 2018-07-04 도쿄엘렉트론가부시키가이샤 Film forming apparatus, film forming method and heat insulating member
JP2018107255A (en) * 2016-12-26 2018-07-05 東京エレクトロン株式会社 Film forming apparatus, film forming method, and heat insulating member
KR102207673B1 (en) * 2016-12-26 2021-01-25 도쿄엘렉트론가부시키가이샤 Film forming apparatus, film forming method and heat insulating member
TWI770095B (en) * 2016-12-26 2022-07-11 日商東京威力科創股份有限公司 Film deposition device, film deposition method, and insulating member
CN109256345A (en) * 2017-07-14 2019-01-22 株式会社国际电气 The manufacturing method of substrate board treatment, substrate holder and semiconductor device
JP2019021910A (en) * 2017-07-14 2019-02-07 株式会社Kokusai Electric Substrate processing apparatus, substrate holder, and semiconductor device manufacturing method
CN109256345B (en) * 2017-07-14 2022-08-26 株式会社国际电气 Substrate processing apparatus, substrate holder, and method for manufacturing semiconductor device

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