JP2001290171A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is high in reliability. SOLUTION: This semiconductor device comprises TFTs and pixel parts having retention capacity, and is featured in that the TFT has a channel forming region which is disposed in the first region of a semiconductor layer, a source region and drain region, a gate insulation film which is in contact with the first region and a gate electrode on the gate insulation film, the retention capacity has the second region of the semiconductor layer, an insulation film which is in contact with the second region and a capacity wiring on the insulation film, the second region includes impurity elements for imparting n-type and p-type and the film thickness of the insulation film which is in contact with the second region is thinner than the film thickness of the gate insulation film which is in contact with the first region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter, referred to as TFT) on a substrate having an insulating surface, and a method for manufacturing the same. In particular, the present invention can be used for an electro-optical device typified by a liquid crystal display device having a pixel portion and a driver circuit provided therearound on the same substrate, and an electric device equipped with the electro-optical device. Note that in this specification, a semiconductor device generally means a device that functions by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electric device including the electro-optical device in its category.

[0002]

2. Description of the Related Art Techniques for forming a TFT on a substrate having an insulating surface have been actively developed. TFTs using an amorphous semiconductor (typically amorphous silicon) film as an active layer are:
10cm due to electronic physical factors caused by amorphous structure, etc.
It was impossible to obtain a field effect mobility of ² / Vsec or more. Therefore, in an active matrix type liquid crystal display device, although it can be used as a switching element (pixel TFT) for driving liquid crystal in a pixel portion, it is not possible to form a driving circuit for performing image display. It was impossible. Therefore, the driving circuit is TAB (Tape A
A technique of mounting a driver IC or the like using a utomated bonding (COG) method or a COG (Chip on Glass) method has been used.

On the other hand, a TFT using a semiconductor film having a crystal structure (hereinafter, referred to as a crystalline semiconductor) (typically, a crystalline silicon film or a polycrystalline silicon film) as an active layer.
Since high field-effect mobility can be obtained, various functional circuits can be formed on the same glass substrate. In addition to pixel TFTs, a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, Etc. could be formed.

Conventionally, an aluminum film having a low resistivity has been frequently used as a wiring material for a TFT as described above.

In order to realize a large screen active matrix type liquid crystal display device, a material such as aluminum (Al) or copper (Cu) has been used as a wiring material.
This is because there was no material having a lower resistance than aluminum (Al) or copper (Cu), and a large-screen display device could not be manufactured.

[0006]

However, these materials have disadvantages such as poor corrosion resistance and heat resistance.
It is not always preferable to form an FT gate electrode with such a material, and it is not easy to introduce such a material into a TFT manufacturing process. In the case where a TFT is manufactured using aluminum as a wiring material Hillocks and whiskers are formed by the heat treatment, and aluminum atoms diffuse into the channel formation region, thereby causing TFT malfunction and deterioration of TFT characteristics.

For this reason, aluminum (Al) or copper (C
u) and the like, for example, tantalum (T
(a) Attempts have been made to use materials containing titanium (Ti) as a main component. Tantalum and titanium have a problem of higher resistivity than aluminum, but have high heat resistance.

In comparison with TFT characteristics, it is better to form an active layer using a crystalline semiconductor layer.
In order to manufacture a TFT corresponding to various circuits in addition to the FT, there is a problem that the manufacturing process becomes complicated and the number of steps increases. It is clear that an increase in the number of steps not only causes an increase in manufacturing cost, but also causes a reduction in manufacturing yield.

However, in the pixel portion and the driving circuit, the TFT
The operating conditions of the circuit are not always the same, and the characteristics required for the TFT are not a little different.
For example, a pixel TFT formed of an n-channel TFT
Are driven by applying a voltage to a liquid crystal as a switching element. Since the liquid crystal is driven by alternating current, a method called frame inversion driving is often used. In this method, in order to suppress power consumption, a characteristic required of the pixel TFT is to sufficiently reduce an off-current value (a drain current flowing when the TFT is turned off). On the other hand, since a high driving voltage is applied to a buffer circuit or the like of a driving circuit, it is necessary to increase a withstand voltage so as not to be broken even when a high voltage is applied. Also, in order to increase the current drive capability,
It is necessary to ensure a sufficient on-current value (drain current flowing when the TFT is turned on).

As a structure of a TFT for reducing an off-current value, a lightly doped drain (LDD) is used.
n) Structure is known. In this structure, a region doped with an impurity element at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration. This region is referred to as an LDD region. Calling. As means for preventing deterioration of the on-current value due to hot carriers, a so-called GD in which an LDD region is arranged so as to overlap with a gate electrode via a gate insulating film is provided.
There is an OLD (Gate-drain Overlapped LDD) structure. With such a structure, it is known that a high electric field near the drain is relieved, hot carrier injection is prevented, and deterioration is effectively prevented.

However, the bias state of the pixel TFT is not necessarily the same as that of the TFT of a driving circuit such as a shift register circuit or a buffer circuit. For example, the pixel T
In the FT, a large reverse bias (negative voltage in an n-channel TFT) is applied to the gate.
The FT basically does not operate in the reverse bias state.
The GOLD structure has a high effect of preventing the deterioration of the on-current value, but the off-current value is increased by simply arranging it on the gate electrode. On the other hand, the ordinary LDD structure has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field near the drain to prevent deterioration due to hot carrier injection. Such a problem is particularly problematic in crystalline silicon TF
In T, the characteristics have been enhanced, and the performance required for the active matrix type liquid crystal display device has been enhanced. Therefore, considering the difference in the operation state of the TFT and preventing the hot carrier effect,
It is necessary to optimize the impurity concentration and distribution of the DD region.

The present invention is a technique for solving such a problem. In a semiconductor device typified by an active matrix type display device manufactured using a TFT,
The wiring and electrodes of each circuit are formed using a material having low resistivity and sufficiently high heat resistance, and the structure of the TFT arranged in each circuit is made appropriate according to the function of the circuit. Accordingly, it is an object to improve the operation characteristics and reliability of the semiconductor device, reduce the number of steps, and realize a reduction in manufacturing cost and an improvement in yield.

[0013]

In order to solve the above problems,
The present invention is a semiconductor device including a pixel portion having a pixel TFT and a storage capacitor, wherein the pixel TFT includes a channel forming region, a source region, and a drain region provided in a first region of a semiconductor layer. Having a gate insulating film in contact with the region and a gate electrode on the gate insulating film,
The storage capacitor has a second region of the semiconductor layer, an insulating film in contact with the second region, and a capacitor wiring on the insulating film, and the second region has an n-type or a p-type. The thickness of the insulating film including the impurity element and in contact with the second region is:
A semiconductor device, wherein the thickness of the gate insulating film in contact with the first region is smaller than that of the gate insulating film.

According to another aspect of the invention, there is provided a semiconductor device including a pixel portion having a pixel TFT and a storage capacitor, wherein the pixel TFT includes a channel forming region, a source region, and a source region provided in a first region of a semiconductor layer. A drain region, the first
And a gate electrode on the gate insulating film, the pixel TFT is an n-channel TFT, and the storage capacitor is a second electrode of the semiconductor layer.
Region, an insulating film in contact with the second region, and a capacitor wiring on the insulating film. The second region contains an impurity element imparting one conductivity type at 1 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ ato
ms / cm contains ^three concentration ranges, the film thickness of the insulating film is in contact with the second region, the semiconductor, characterized in that thinner than the thickness of the gate insulating film in contact with said first region Device.

According to another aspect of the invention, there is provided a semiconductor device having a pixel portion and a driving circuit on the same substrate, wherein the driving circuit includes a p-channel TFT and an n-channel TFT.
Wherein the n-channel TFT has a channel formation region in a semiconductor layer, a source region and a drain region, an LDD region, a gate insulating film in contact with the semiconductor layer, and a gate electrode on the gate insulating film, The gate electrode has a first conductive layer and a second conductive layer, and the second conductive layer is formed so as to overlap the LDD region via the gate insulating film. It is a semiconductor device.

Another aspect of the invention is a semiconductor device having a pixel portion and a driver circuit on the same substrate, wherein the pixel portion has a pixel TFT and a storage capacitor, and
The FT includes a channel formation region, a source region, and a drain region provided in a first region of a semiconductor layer, a gate insulating film in contact with the first region, and a gate electrode on the gate insulating film. The TFT is an n-channel TFT, and the storage capacitor has a second region of the semiconductor layer, an insulating film in contact with the second region, and a capacitor wiring on the insulating film, The thickness of the insulating film in contact with the region is smaller than the thickness of the gate insulating film in contact with the first region, and the driving circuit includes a p-channel TFT and an n-channel TFT.
A semiconductor layer of an n-channel TFT of the driving circuit, a channel formation region, a source region and a drain region, an LDD region, a gate insulating film in contact with the semiconductor layer, and a gate electrode on the gate insulating film. The gate electrode has a first conductive layer and a second conductive layer, and the second conductive layer is formed so as to overlap the LDD region with the gate insulating film interposed therebetween; A semiconductor device comprising the same material as a wiring.

Another aspect of the invention is a semiconductor device having a pixel portion and a driver circuit on the same substrate, wherein the pixel portion has an n-channel TFT and a storage capacitor, and the storage capacitor is a semiconductor device. A semiconductor layer, an insulating film serving as a dielectric of a storage capacitor in contact with the semiconductor layer, and a capacitor wiring formed on the insulating film. The semiconductor layer contains 1 × 10 ^{20 of} an impurity element imparting one conductivity type. atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³
The thickness of the insulating film in a region where the n-channel TFT is not formed is thinner than a region where the n-channel TFT is formed, and the driving circuit is a p-channel TFT. A p-channel TFT of the driver circuit and an n-channel TFT of the driver circuit include a semiconductor layer, a gate insulating film in contact with the semiconductor layer, and a gate over the gate insulating film. The semiconductor device has an electrode, and the gate electrode has a shape having a tapered portion.

According to another aspect of the present invention, there is provided a semiconductor device having a pixel portion and a driver circuit on the same substrate, wherein the pixel portion has an n-channel TFT and a storage capacitor, A type TFT, a semiconductor layer having a channel formation region, an LDD region outside the channel formation region, a source region or a drain region outside the LDD region, a gate insulating film in contact with the semiconductor layer, A gate electrode formed on the gate insulating film, and an insulating film which is formed continuously from the gate insulating film and serves as a dielectric of the storage capacitor has a smaller thickness than other regions; The circuit consists of a p-channel TFT and an n-channel TF
An n-channel TFT of the driving circuit, the semiconductor layer having a channel formation region, an LDD region outside the channel formation region, and a source region or a drain region outside the LDD region; A gate insulating film in contact with the semiconductor layer; and a gate electrode on the gate insulating film. The gate electrode of the n-channel TFT in the pixel portion and the gate electrode of the n-channel TFT in the driving circuit are tapered. Wherein the semiconductor device is formed so as to partially overlap the LDD region.

In the above invention, the capacitor wiring forming the storage capacitor and the second conductive layer may be formed of an element selected from aluminum (Al) or copper (Cu), or a compound containing the element as a component. Or a compound material obtained by combining the above elements.

In the above invention, the first conductive layer is formed of an element selected from tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo), or a compound containing the element as a component. , Or a compound of the above elements, or a nitride containing the above elements,
It is characterized by being made of a material selected from silicides containing the above elements as components.

[0021]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, the pixel TFT of the pixel portion and the TF of a driving circuit provided around the pixel portion are used.
A method for manufacturing T on the same substrate will be described in detail according to the steps.

In FIG. 1A, a low alkali glass substrate or a quartz substrate can be used as the substrate 101. In this embodiment, a low alkali glass substrate was used. in this case,
The heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. TFT of this substrate 101
A base film 102 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface on which is formed to prevent impurity diffusion from the substrate 101. For example, SiH ₄ in plasma CVD, the NH _3, N ₂ silicon oxynitride film formed from the O 100 nm, similarly Si
A silicon oxynitride film made of H ₄ and N ₂ O
The layer is formed to a thickness of nm.

Next, 20 to 150 nm (preferably 30 nm)
Semiconductor film 10 having an amorphous structure with a thickness of
3a is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. Since the base film 102 and the amorphous silicon film 103a can be formed by the same film formation method, both may be formed continuously. After the formation of the base film, it is possible to prevent the surface from being contaminated by not once exposing it to the atmosphere, thereby reducing the variation in the characteristics of the TFT to be manufactured and the fluctuation of the threshold voltage (FIG. 1A )).

Then, a crystalline silicon film 103b is formed from the amorphous silicon film 103a using a known crystallization technique. For example, a laser annealing method, a thermal annealing method (solid phase growth method), or a rapid thermal annealing method (RTA method) can be applied as the method. Further, the thermal annealing may be combined with the RTA method or the laser annealing method. When a glass substrate or a plastic substrate having low heat resistance as described above is used, it is particularly preferable to apply a laser annealing method. In the RTA method, an infrared lamp, a halogen lamp, a metal halide lamp, a xenon lamp, or the like is used as a light source.

In this embodiment, the crystalline silicon film 103b is formed by a crystallization method using a catalytic element according to the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652. In the case of performing crystallization treatment by laser, prior to the crystallization step, heat treatment is performed at 400 to 500 ° C. for about 1 hour,
It is desirable to crystallize after reducing the hydrogen content to 5 atomic% or less. When the amorphous silicon film is crystallized, rearrangement of atoms occurs and the film becomes denser. Therefore, the thickness of the crystalline silicon film to be formed is larger than the initial thickness of the amorphous silicon film (55 nm in this embodiment). Was also reduced by about 1 to 15% (FIG. 1 (B)).

Then, the crystalline silicon film 103b is divided into islands, and island-like semiconductor layers 104 to 107 are formed.
The semiconductor layer 107 is a first layer which becomes an active layer of a pixel TFT later.
And a second region that will be the lower electrode of the storage capacitor later. After that, a mask layer 108 of a silicon oxide film having a thickness of 50 to 100 nm is formed by a plasma CVD method or a sputtering method (FIG. 1C).

Then, a resist mask 109 is provided, and island-shaped semiconductor layers 105 to 107 for forming an n-channel TFT are formed.
1 × 10 ^{16 to} 5 for the purpose of controlling the threshold voltage
× 10 ¹⁷ atoms / cm ³ (using the atoms / cm ³ as a unit representing the number of atoms contained in 1 cm ^3.) P at a concentration of about
Boron (B) was added as an impurity element for imparting a mold. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film. Although the addition of boron (B) here is not always necessary, it is preferable that the semiconductor layers 110 to 112 to which boron (B) is added be formed so that the threshold voltage of the n-channel TFT falls within a predetermined range. It was good (FIG. 1 (D)).

Next, a step of removing the mask layer 108 with hydrofluoric acid or the like and activating the impurity element added in FIG. 1D is performed. Activation is performed in a nitrogen atmosphere at 500 to 6
It can be performed by a heat treatment at 00 ° C. for 1 to 4 hours or a laser activation method. Further, both may be performed in combination. In this embodiment, using a laser activation method,
Using KrF excimer laser light (wavelength 248 nm),
A linear beam is formed, scanning is performed with an oscillation frequency of 5 to 50 Hz, an energy density of 100 to 500 mJ / cm ² , and an overlap ratio of the linear beam of 80 to 98%, and the entire surface of the substrate on which the island-shaped semiconductor layer is formed. Was processed.
There are no particular restrictions on the laser light irradiation conditions, and the conditions may be determined appropriately by the practitioner.

Then, the gate insulating film 113 is formed by plasma C
The insulating film containing silicon is formed with a thickness of 10 to 150 nm by a VD method or a sputtering method. For example, 120
A silicon oxynitride film is formed with a thickness of nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure (FIG. 2A).

Next, a conductive layer is formed to form a gate electrode. The conductive layer may be formed as a single layer, or may be formed as a two-layer or three-layer structure as necessary. As the conductive layer 114, tungsten silicide, titanium silicide, or molybdenum silicide may be used as an alternative material. For example, when tungsten (W) has an oxygen concentration of 30 ppm or less, a specific resistance of 20 μΩcm or less can be realized.

The conductive layer 114 may have a thickness of 200 to 400 nm (preferably, 250 to 350 nm). In this embodiment, 350 nm thick tungsten is formed in the conductive layer 114 by a sputtering method. In the film formation by the sputtering method, if an appropriate amount of Xe or Kr is added to Ar of the gas for sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, the conductive layer 11
It is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm underneath. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, the diffusion of the alkali metal element contained in the conductive layer in the gate insulating film 113 can be prevented (FIG. 2). (B)).

Next, resist masks 115 to 118 are formed, and the conductive layer is dry-etched to form a gate electrode 119.
To 122 are formed.

In the step of etching the conductive layer,
A region where the gate electrode is not formed (gate insulating film 11
The portion where the silicon oxynitride film formed continuously with Step 3 is exposed) is also etched by about 20 to 50 nm at the same time, and the film thickness becomes thin. Note that, in the present invention, since the silicon oxynitride film having the reduced thickness is used as the dielectric of the storage capacitor, the capacity of the storage capacitor can be increased without increasing the area of the storage capacitor.

Next, in order to form a source region and a drain region of the p-channel TFT of the driving circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligned manner using the gate electrode 119 as a mask. At this time, a region where the n-channel TFT is to be formed is covered with a resist mask 124. Then, the impurity region 123 was formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 123 formed here is expressed as (p ⁺ ) (FIG. 3A).

In this embodiment, the entire surface of the semiconductor layer 112 is covered with the resist mask 124. However, a step of adding an impurity element imparting p-type without forming a resist mask in a region where a capacitor wiring is to be formed. May go.

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 125 to 128 are formed, and an impurity element for imparting n-type
29 to 132 were formed. This is a phosphine (PH
₃ ), and the phosphorus (P) concentration in this region was set to 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . In this specification, the impurity region 12 formed here is used.
The concentration of the impurity element imparting n-type contained in 9 to 132 is represented by (n ⁺ ). The mask 126 allows the first n
In a semiconductor layer serving as an active layer of a channel type TFT, a region to which an impurity is not added is formed only between a channel formation region and a drain region. In the active matrix type liquid crystal display device, high-speed operation is emphasized by logic circuits such as a shift register circuit, a frequency dividing circuit, a signal dividing circuit, a level shifter circuit, and a buffer circuit. By forming the impurity region only on one side (drain region side) of the channel formation region, a structure in which resistance components are reduced as much as possible and hot carrier measures are emphasized can be achieved. In addition, since a mask is not formed over a semiconductor layer (a second region) to be a lower electrode of a storage capacitor later, an impurity element is added to the semiconductor layer (a second region). This can increase the conductivity of the lower electrode (see FIG. 3).
(B)).

The impurity regions 129 to 132 contain phosphorus (P) or boron (B) already added in the previous step, but phosphorus (P) is added at a sufficiently high concentration. Therefore, it is not necessary to consider the influence of phosphorus (P) or boron (B) added in the previous step. Further, the concentration of phosphorus (P) added to the impurity region 129 is １ ／ to １ ／ of the concentration of boron (B) added in FIG.
The mold was secured and had no effect on the characteristics of the TFT.

Then, a step of adding an impurity for imparting n-type for forming an LDD region of the pixel TFT was performed. Here, n is self-aligned using gate electrode 122 as a mask.
An impurity element for imparting a mold was added by an ion doping method.
The concentration of phosphorus (P) to be added is 1 × 10 ^{16 to} 5 × 10 ¹⁸ at
oms / cm ³ , and the impurity regions 133 and 134 are substantially formed by being added at a lower concentration than the concentration of the impurity element added in FIGS. 3A and 3B. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 133 and 134 is expressed as (n ⁻ ) (FIG. 3C).

Thereafter, a heat treatment step is performed to activate the impurity elements imparting n-type or p-type added at the respective concentrations. This step can be performed by a furnace annealing method, a laser annealing method, a rapid thermal annealing method (RTA method), or a combination thereof. Here, the activation step was performed by the furnace annealing method. The heat treatment has an oxygen concentration of 1 ppm or less, preferably 0.1 ppm.
The heat treatment is performed at 400 to 800 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere of 1 ppm or less. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours. The substrate 10
When a heat-resistant material such as a quartz substrate is used for 1, heat treatment may be performed at 800 ° C. for 1 hour to activate the impurity element and to form an impurity region doped with the impurity element and a channel forming region. Was successfully formed.

In this heat treatment, the gate electrodes 119 to 119
In the metal film forming 122, conductive layers 119b to 122b are formed with a thickness of 5 to 80 nm from the surface. For example,
When the conductive layers 119 to 122 are tungsten (W), tungsten nitride (WN) is formed and tantalum (T
In the case of a), tantalum nitride (TaN) can be formed. Further, the conductive layers 119b to 122b can be formed in a similar manner even when the gate electrodes 119 to 122 are exposed to a plasma atmosphere containing nitrogen using nitrogen or ammonia. Further, heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-shaped semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

When the island-like semiconductor layer was formed from an amorphous silicon film by a crystallization method using a catalyst element, a trace amount of the catalyst element remained in the island-like semiconductor layer. Of course, it is possible to complete the TFT in such a state,
It was more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing the catalytic element is a means utilizing the gettering action of phosphorus (P). The concentration of phosphorus (P) necessary for gettering is almost the same as that of the impurity region (n ⁺ ) formed in FIG. 3B, and the heat treatment in the activation step performed here causes the n-channel TFT and the p-type. The catalyst element could be gettered from the channel formation region of the channel type TFT (FIG. 4A).

FIGS. 6A and 7A are top views of the TFT in the steps up to here, and the AA 'section and the BB' section are taken along AA 'and FIG. 3D. BB '. Although the gate insulating film is omitted in the top views of FIGS. 6 and 7, gate electrodes 119 to 122 are formed on at least the island-shaped semiconductor layers 104 to 107 as shown in FIGS.

When the activation and hydrogenation steps are completed,
In order to form a capacitor wiring in the pixel portion, a film containing aluminum as a main component was formed. It is preferable to use a material whose main component is aluminum (Al) or copper (Cu) which is a low-resistance material. In this embodiment, titanium (Ti) is contained in an amount of 0.1 to 2%.
The aluminum (Al) film 135 containing the weight% is formed,
This film is patterned to form gate wirings 137 and 13
8. A capacitor wiring 139 serving as an upper electrode of the storage capacitor was formed (FIGS. 4B and 4C).

FIGS. 6B and 7B show top views in this state, and the AA 'section and the BB' section are shown in FIG.
(B) corresponds to AA ′ and BB ′. FIG.
7B, part of the gate wirings 137 and 138 overlap with part of the gate electrodes 119, 120, and 122 and are in electrical contact with each other as seen in the region 120c.

Next, a protective insulating film 140 is formed. The protective insulating film 140 may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film obtained by combining these. In any case, the protective insulating film 14
0 is formed from an inorganic insulating material. Protective insulating film 140
Has a thickness of 100 to 200 nm. In this embodiment, a silicon oxide film is used and a plasma CVD method is used to form tetraethyl orthosilicate (TEO).
S) and O ₂ were mixed, the reaction pressure was 10 Pa, and the substrate temperature was 3
It is formed by discharging at a high frequency (13.56 MHz) and a power density of 0.5 to 0.8 W / cm ² at a temperature of 00 to 400 ° C.

Thereafter, in order to flatten, an average thickness of 1.
Interlayer insulating film 1 made of an organic insulating material of 0 to 2.0 μm
41 is formed. As the organic insulator material, an organic resin material such as polyimide, acrylic, polyamide, polyimide amide, and BCB (benzocyclobutene) can be used. In the case of using a polyimide of a type which is thermally polymerized after coating on a substrate, a two-component type is used. After mixing a main material and a curing agent, the solution is applied to the entire surface of the substrate using a spinner. The film can be formed by performing preliminary heating at 60 ° C. for 60 seconds and further firing at 250 ° C. for 60 minutes in a clean oven.

In addition to the planarization, the reason why the interlayer insulating film is generally formed using an organic resin material having a low dielectric constant is that the parasitic capacitance can be reduced. However, since it is not suitable as a protective film because of its hygroscopicity, it must be used in combination with a silicon oxide film or the like formed as the protective insulating film 140 as in this embodiment.

After forming the interlayer insulating film 141, a resist mask having a predetermined pattern is formed, and a contact hole reaching the source region and the drain region formed in the island-shaped semiconductor layer is formed. In this case, CF ₄ ,
First, the interlayer insulating film 141 made of an organic resin material is etched using a mixed gas of O ₂ and He.
By etching the gate insulating film is switched to F _3, it is possible to form a good contact hole.

In order to form source and drain wirings,
In this embodiment, a titanium (Ti) film is formed with a thickness of 50 to 150 nm, and an aluminum (Al) film is formed thereon with a thickness of 300 to 400 nm. Also, Ti /
It may be a laminate made of TiN / Al.

As a pixel electrode, indium oxide (In ₂
O ₃ ) and indium tin oxide alloy (In ₂ O ₃ —Sn)
O ₂ ; ITO) A transparent conductive film is formed by sputtering or vacuum evaporation. The etching of such a material is performed using a hydrochloric acid-based solution. However, in particular, since etching of ITO easily generates residues, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used in order to improve the etching processability. Indium oxide zinc oxide alloy has excellent surface smoothness,
Therefore, it is possible to prevent a corrosion reaction with Al contacting at the end face of the drain wiring. Similarly, zinc oxide (ZnO) is also a suitable material, and gallium (Ga) is used to further increase the transmittance and conductivity of visible light.
For example, zinc oxide (ZnO: Ga) to which is added. In this embodiment, the pixel electrode 156 is formed using an indium zinc oxide alloy as a transparent conductive film.

A resist mask pattern is formed using a photomask, and the source wirings 142 and 1 are formed by etching.
44, 145, 147 and drain wirings 143, 146,
148 and 149 are formed (FIG. 5A).

FIGS. 6C and 7C show top views in this state, and the AA 'section and the BB' section are shown in FIG.
(A) corresponds to AA ′ and BB ′. FIG.
In FIG. 7C and FIG. 7C, the first interlayer insulating film is omitted, but the source wiring 14 is formed in the not-shown source and drain regions of the island-shaped semiconductor layers 104, 105, and 107.
2, 145, 147 and drain wirings 143, 146, 1
Reference numeral 49 is connected via a contact hole formed in the interlayer insulating film.

Thus, on the same substrate, the TFT of the driving circuit
And a substrate having pixel TFTs in the pixel portion. The drive circuit 250 includes a p-channel TFT 20
1, a first n-channel TFT 202, a second n-channel TFT 203, and a pixel TFT 251 in a pixel portion 251.
4. A storage capacitor 205 was formed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the p-channel TFT 201 of the driving circuit, the channel forming region 206, the source regions 207a and 207b, the drain region 208a,
208b. First n-channel TFT 20
2 includes a channel formation region 20 in the island-shaped semiconductor layer 105.
9, an LDD region 210 overlapping with the gate electrode 129 (hereinafter, such an LDD region is referred to as Lov; ov is denoted by over), a source region 212, and a drain region 211. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm.
μm. In the second n-channel TFT 203, a channel formation region 213, LDD regions 214 and 215, a source region 216, and a drain region 2 are formed in the island-shaped semiconductor layer 106.
17. This LDD region is formed with an Lov region and an LDD region that does not overlap with the gate electrode 121 (hereinafter, such an LDD region is referred to as Loff, and off is denoted by offset), and the channel of the Loff region is formed. The length in the long direction is 0.3 to 2.0 μm, preferably 0.5 to
1.5 μm. In the pixel TFT 204, channel forming regions 218 and 219, Loff regions 220 to 223, source or drain regions 224 to
226. The length of the Loff region in the channel length direction is 0.5 to 3.0 μm, preferably 1.5 to 2.5 μm.
m. Further, an upper electrode (capacitance wiring) 139, a dielectric (an insulating film made of the same material as the gate insulating film), and a lower electrode (an impurity element which is connected to the drain region 226 of the pixel TFT 204 and imparts n-type are added. Semiconductor layer)
227 are formed. Although the pixel TFT 204 has a double gate structure in FIG. 5,
A single gate structure may be used, or a multi-gate structure provided with a plurality of gate electrodes may be used.

Further, as shown in FIG. 5B, a columnar spacer 150 is formed. The columnar spacer 150 is
In this embodiment, NN700 manufactured by JSR Co., Ltd. is applied by a spinner, and then exposed and developed to a predetermined pattern (preferably, as shown in FIG.
If the shape of 0 is a column and the top is flat, mechanical strength as a liquid crystal display panel can be secured when the substrates on the opposite side are combined. The shape is not particularly limited to a conical shape or a pyramid shape. For example, when the shape is a conical shape, specifically, the height H is 1.2 to 5 μm, the average radius L1 is 5 to 7 μm, and the average radius L1 is Bottom radius L
The ratio to 2 is 1: 1.5. At this time, the taper angle of the side surface is set to ± 15 ° or less. ). Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like.

The arrangement of the spacers may be determined arbitrarily. Preferably, as shown in FIG. 5B, in the pixel portion, the columnar spacer 150 is overlapped with the contact portion of the drain wiring 149 so as to cover the contact portion. Should be formed. Since the flatness of the contact portion is impaired and the liquid crystal is not well aligned in this portion, the columnar spacer 1 is filled in such a manner that the contact portion is filled with the resin for the spacer.
By forming 50, disclination and the like can be prevented.

As shown in FIG. 5B, the columnar spacer 1
A protective film 151 for protecting the side surface in the process of manufacturing 50 is formed.

Thereafter, after forming an alignment film (not shown) on the surface of the active matrix substrate, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. A region that is not rubbed in the rubbing direction from the end of the columnar spacer 150 provided in the pixel portion is 2
μm or less. In addition, the generation of static electricity is often a problem in the rubbing process.
If the spacer 150 is formed thereon, the original role of the spacer and the effect of protecting the TFT from static electricity can be obtained.

As described above, an active matrix substrate in which the columnar spacer 150 for maintaining the substrate interval is integrated with the substrate 101 is completed.

On the counter substrate that is paired with the active matrix substrate, a light-shielding film 230, a color filter (not shown), a transparent conductive film 231 and an alignment film 232 are formed on the substrate. The light shielding film 230 is made of Ti, Cr, Al or the like.
It is formed with a thickness of 50 to 300 nm.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed is bonded to the counter substrate.
Thereafter, a liquid crystal material 234 is injected into the gap between the substrates, and completely sealed with a sealant (not shown), thereby completing a liquid crystal panel (FIG. 11).

As described above, according to the present invention, the insulating film forming the storage capacitor is thinner than the other regions, and the semiconductor layer is doped with impurities at a high concentration. Can be formed. There has been a problem that the aperture ratio decreases instead of increasing the storage capacitance. However, according to the present invention, a storage capacitor having a large capacity can be formed while the aperture ratio is high. In addition, since the second conductive layer that blocks the LDD region is not formed at the time of the impurity activation step, the LDD region can be sufficiently activated.

Further, it is possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel TFT and the driving circuit, and to improve the operation performance and reliability of the semiconductor device. Further, the gate electrode is formed of a conductive material having heat resistance, thereby facilitating activation of the LDD region, the source region, and the drain region, and the wiring resistance can be sufficiently reduced by forming the gate wiring with a low-resistance material. Therefore, the present invention can be applied to a display device having a pixel portion (screen size) of 4 inch class or more.

[Embodiment 2] FIG. 15 is a view for explaining the structure of the TFT of the present invention. The channel formation region of the semiconductor layer, the LDD region, the gate insulating film on the semiconductor layer, and the gate insulating film In a TFT having an upper gate electrode,
The positional relationship between the gate electrode and the LDD region is described.

Referring to FIG. 15A, a first n-channel TFT will be described. A channel formation region 209,
This figure shows a configuration in which a semiconductor layer having LDD regions 210a and 210b and a drain region 211, and a gate insulating film 113 and a gate electrode 120 provided thereon are provided. The LDD region has a one-sided LDD structure provided only between the channel formation region and the drain region. LDD region 21
Oa is Lov provided so as to overlap the gate electrode 120 with the gate insulating film 113 interposed therebetween. Lov has a function of alleviating a high electric field generated near the drain, and can prevent deterioration due to hot carriers. Therefore, Lov is suitable for use in an n-channel TFT such as a shift register circuit of a control circuit, a level shifter circuit, and a buffer circuit. ing.

Referring to FIG. 15B, a second n-channel TFT will be described. Channel forming region 213,
A semiconductor layer having LDD regions 214a and 214b and a drain region (source region) 216, and a structure in which a gate insulating film 113 and a gate electrode 121 are provided over the semiconductor layer are shown. The LDD region 214a is the gate insulating film 113
Are provided so as to overlap with the gate electrode 121 via the gate electrode 121. The LDD region 214b is Loff provided so as not to overlap with the gate electrode 121. Loff has an action of reducing the off-current value, and by providing Lov and Loff, the off-current value can be reduced while preventing deterioration due to hot carriers. n-channel type TFT
Suitable for use in

Referring to FIG. 15C, the pixel TFT will be described. In the semiconductor layer, a channel formation region 219, L
A DD region 223 and a drain region 226 are provided. The LDD region 223 is Loff provided so as not to overlap with the gate electrode 122 and can effectively reduce an off current value, and thus is suitable for use in a pixel TFT.

[Embodiment 3] Next, the structure of this active matrix type liquid crystal display device will be described with reference to the perspective view of FIG.
This will be described with reference to the top view of FIG. 12 and 13 use the same reference numerals in order to correspond to the sectional structural views of FIGS. 1 to 5 and 11. The cross-sectional structure along BB 'shown in FIG. 13 corresponds to the cross-sectional view of the pixel portion shown in FIG.

In FIG. 12, the active matrix substrate is a pixel portion 306 formed on the glass substrate 101.
, Scanning signal driving circuit 304 and image signal driving circuit 30
5 is comprised. A pixel TFT 204 is provided in the pixel portion, and a driving circuit provided in the periphery is configured based on a CMOS circuit. The scanning signal driving circuit 304 and the image signal driving circuit 305 are connected to the pixel TFT 204 by a gate wiring 137 and a source wiring 145, respectively. Further, the FPC 731 is connected to the external input terminal 734, and is connected to each drive circuit through the input wirings 302 and 303.

FIG. 13 is a top view showing almost one pixel of the pixel section 306. FIG. Although not shown, the semiconductor layer includes:
An Loff region including a source region, a drain region, and an n ⁻ region is formed. 158 is a contact portion between the source wiring 145 and the source region 224, and 159 is a contact portion between the drain region 226 and the drain wiring 149.
The storage capacitor 205 is connected to the drain region 2 of the pixel TFT 204.
The semiconductor layer 227 in the second region serving as the lower electrode extending from 26 and the capacitor wiring 139 serving as the upper electrode overlap with the semiconductor layer 227 via the gate insulating film.

[Embodiment 4] FIG. 10 is a diagram showing an example of an arrangement of input / output terminals, a pixel portion, and a driving circuit of a liquid crystal display device.
In the pixel portion 306, m gate wirings and n source wirings intersect in a matrix. For example, if the pixel density is V
In the case of GA, 480 gate lines and 640 source lines are formed, and in the case of XGA, 768 gate lines and 1024 source lines are formed. The screen size of the pixel unit is 3 inches for a 13-inch class.
40mm, 460m for 18 inch class
m. In order to realize such a liquid crystal display device, it is necessary to form the gate wiring with a low resistance material as shown in the first and second embodiments.

A scanning signal driving circuit 304 and an image signal driving circuit 305 are provided around the pixel section 306. The length of the gate wiring of these driving circuits is inevitably increased with the increase in the screen size of the pixel portion. Therefore, in order to realize a large screen, a low-resistance material as described in the first and second embodiments is used. Preferably, it is formed.

Further, according to the present invention, the input wirings 302 and 303 connecting the input terminal 301 to each drive circuit can be formed of the same material as the gate wiring, which can contribute to lowering the wiring resistance.

FIG. 37 shows a process of forming an input terminal portion. FIG. 11 shows a part of a section taken along the line FF ′ of the input terminal portion 301 in FIG. 10. A common number is used for associating with the steps of the first embodiment. FIG. 37 (A-2)
To FIG. 37 (E-2) show T corresponding to the step of forming the terminal portion.
FIG. 3 is a cross-sectional view illustrating a step of forming an FT.

First, in a step of forming an interlayer insulating film 141 in a drive circuit portion and a pixel portion on a substrate on which a base film is formed, an organic resin material such as polyimide, acrylic, polyamide, polyimide amide, and BCB (benzocyclobutene) is used. The interlayer insulating film 141x is formed by using, for example, (FIG. 37B).

Next, as a metal film for forming source and drain wirings, for example, a titanium (Ti) film is
An aluminum (Al) film is formed with a thickness of 300 to 400 nm on top of that. A transparent conductive film such as indium oxide (In ₂ O ₃ ) or an indium tin oxide alloy (In ₂ O ₃ —SnO ₂ ; ITO) transparent conductive film is formed thereon by sputtering or vacuum evaporation. (FIGS. 37C and 37D).

Thereafter, after the source and drain wirings and the pixel electrode are etched into predetermined shapes, the columnar spacers 15 are formed.
In order to prevent the metal film and the transparent conductive film from peeling when forming 0, a spacer 150x is formed so as to suppress the metal film and the transparent conductive film. Further, the mechanical strength can be increased by forming the spacer 150x (FIG. 37E).

After bonding the active matrix substrate on which the pixel portion and the driving circuit are formed to the counter substrate, the active matrix substrate is connected to a circuit for inputting a circuit and a video signal, and a power supply for supplying power. In the terminal portion, the connection wiring and the FPC 191 are electrically connected by an anisotropic conductive film 195 (FIG. 2).
0).

As shown in FIG. 20, the anisotropic conductive film 195 is composed of tens to hundreds of μm particles 195 b plated with gold or chromium in an adhesive 195 a.
5b comes into contact with the connection wiring and the wiring 191b of the FPC, so that the active matrix substrate 100 and the FPC 1
91 can be electrically connected but formed. FP
C191 protrudes outside the external terminal portion in order to increase the adhesive strength to the substrate 101, and a resin layer 192 is provided at the end.
Is provided, and a connection part with high mechanical strength can be obtained.

[Embodiment 5] FIG. 14 is an example of the circuit configuration of the active matrix substrate shown in Embodiment 1 or 2, and is a diagram showing the circuit configuration of a direct-view display device. The active matrix substrate of this embodiment includes an image signal driving circuit 1001, a scanning signal driving circuit (A) 1007,
Scan signal drive circuit (B) 1011, precharge circuit 1
012 and a pixel portion 1006. Note that the driving circuit described in this specification is an image signal driving circuit 100.
1. General term including the scanning signal drive circuit (A) 1007.

The image signal driving circuit 1001 includes a shift register circuit 1002, a level shifter circuit 1003, a buffer circuit 1004, and a sampling circuit 1005. The scan signal driver circuit (A) 1007 includes a shift register circuit 1008, a level shifter circuit 1009, and a buffer circuit 1010. The scanning signal driving circuit (B) 1011 has the same configuration.

The shift register circuits 1002 and 1008 have a drive voltage of 5 to 16 V (typically 10 V). The n-channel TFT of the CMOS circuit forming this circuit has a structure shown by 202 in FIG. I have. Also, the level shifter circuits 1003 and 1009 and the buffer circuit 100
For 4,1010, the driving voltage is as high as 14 to 16 V,
Similarly to the shift register circuit, the n-channel type TF shown in FIG.
CMOS circuits including T202 are suitable. In these circuits, forming the gate in a multi-gate structure increases the withstand voltage, which is effective in improving the reliability of the circuit.

The sampling circuit 1005 has a driving voltage of 1
The voltage is 4 to 16 V. However, since the polarity is alternately reversed and the off-current value needs to be reduced, n in FIG.
A CMOS circuit including the channel type TFT 203 is suitable. Although only an n-channel TFT is shown in FIG. 5, in an actual sampling circuit, a p-channel TFT is also formed. At this time, the structure shown in FIG. 201 is sufficient for the p-channel TFT.

The driving voltage of the pixel TFT 204 is 14
To 16 V, which is required to further reduce the off-current value compared to the sampling circuit from the viewpoint of low power consumption, and an LDD (Loff) region provided so as not to overlap with the gate electrode like the pixel TFT 204. It is desirable to have a structure having

The structure of this embodiment can be easily realized by fabricating a TFT according to the steps shown in the first embodiment. In the present embodiment, only the configuration of the pixel portion and the control circuit is shown. Further, a signal processing circuit such as a memory circuit or an arithmetic processing circuit, or a logic circuit can be formed over the same substrate. in this way,
The present invention can realize a semiconductor device including a pixel portion and a control circuit thereof over the same substrate, for example, a semiconductor device including a signal control circuit and a pixel portion.

[Embodiment 6] FIG. 16 shows an embodiment of the present invention.
This will be described with reference to FIGS. Here, the pixel T of the pixel portion
A method for simultaneously manufacturing the FT, the storage capacitor, and the TFT of the driver circuit provided around the pixel portion will be described in detail according to steps.

In FIG. 16A, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass, a quartz substrate, or the like is used as a substrate 1101. When a glass substrate is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. Then, a base film 1102 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the surface of the substrate 1101 where a TFT is to be formed, in order to prevent impurity diffusion from the substrate 1101. For example, a plasma CVD method _{SiH 4, NH 3, N 2} O silicon oxynitride film 1102a made from 10 to 20
0 nm (preferably 50-100 nm), as well as SiH ₄ ,
Silicon oxynitride hydride film 110 made of N ₂ O
2b is 50 to 200 nm (preferably 100 to 150 nm)
To a thickness of. Here, the base film 1102 is shown as having a two-layer structure; however, the base film 1102 may be formed as a single-layer film or two or more layers of the insulating films.

The silicon oxynitride film is formed by using a parallel plate type plasma CVD method. Silicon oxynitride film 11
02a is SiH ₄ of 10/60 cm ³ / s and NH ₃ of 100
/ 60 cm ³ / s, N ₂ O was introduced into the reaction chamber at 20/60 cm ³ / s, the substrate temperature was 325 ° C., the reaction pressure was 40 Pa, the discharge power density was 0.41 W / cm ² , and the discharge frequency was 60 MHz. on the other hand,
Hydrogenated silicon oxynitride film 1102b is the SiH ₄ 5
/ 60 cm ³ / s, N ₂ O 120/60 cm ³ / s, H ₂ 125
/ 60 cm ³ / s, and introduced into the reaction chamber, substrate temperature 400
° C, a reaction pressure of 20 Pa, a discharge power density of 0.41 W / cm ² , and a discharge frequency of 60 MHz. These films can be continuously formed only by changing the substrate temperature and switching the reaction gas.

The silicon oxynitride film 1102a thus manufactured has a density of 9.28 × 10 ²² / cm ³ ,
_{2 of} a mixed solution (manufactured by Stella Chemifa Corporation, trade name: LAL500) containing 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and 15.4% of ammonium fluoride (NH ₄ F)
The etching rate at 0 ° C. is as low as about 63 nm / min, and the film is dense and hard. When such a film is used as a base film,
This is effective for preventing an alkali metal element from a glass substrate from diffusing into a semiconductor layer formed thereon.

Next, 25 to 80 nm (preferably 30 to 6 nm)
Semiconductor layer 1103a having a thickness of 0 nm) and having an amorphous structure.
Is formed by a method such as a plasma CVD method or a sputtering method. The semiconductor film having an amorphous structure includes an amorphous semiconductor layer and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. When an amorphous silicon film is formed by a plasma CVD method, the base film 1102 and the amorphous semiconductor layer 1103 are formed.
With a, both can be formed continuously. For example,
As described above, after the silicon oxynitride film 1102a and the silicon oxynitride hydride film 1102b are continuously formed by the plasma CVD method, the reaction gas is changed from SiH ₄ , N ₂ O, H ₂ to Si.
By switching only H ₄ and H ₂ or SiH _4, once it can be continuously formed without exposure to the atmosphere. As a result, contamination of the surface of the hydrogenated silicon oxynitride film 1102b can be prevented, and variation in characteristics of a TFT to be manufactured and fluctuation in threshold voltage can be reduced.

Then, a crystallization step is performed to form a crystalline semiconductor layer 1103b from the amorphous semiconductor layer 1103a. As the method, a laser annealing method, a thermal annealing method (solid phase growth method), or a rapid thermal annealing method (RTA method) can be applied. When a glass substrate or a plastic substrate having low heat resistance as described above is used, it is particularly preferable to apply a laser annealing method. In the RTA method, an infrared lamp, a halogen lamp, a metal halide lamp, a xenon lamp, or the like is used as a light source. Alternatively, the crystalline semiconductor layer 1103b can be formed by a crystallization method using a catalytic element according to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652. In the crystallization step, first, it is preferable to release hydrogen contained in the amorphous semiconductor layer, and heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the amount of hydrogen contained to 5 atomic% (showing the atomic ratio. In the following, atomic% is used as a unit.) Crystallization after the following is preferable because roughness of the film surface can be prevented.

In the step of forming an amorphous silicon film by the plasma CVD method, SiH ₄ and argon (Ar) are used as reaction gases, and the substrate temperature during film formation is 400 to 450 ° C.
When formed, the hydrogen concentration in the amorphous silicon film can be reduced to 5 atomic% or less. In such a case, heat treatment for releasing hydrogen becomes unnecessary.

When crystallization is performed by laser annealing, a pulse oscillation type or continuous emission type excimer laser or argon laser is used as the light source. When a pulse oscillation type excimer laser is used, laser annealing is performed by processing the laser beam into a linear shape. Laser annealing conditions are appropriately selected by the practitioner, for example,
The laser pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 500 mJ / cm ² (typically 300
４００400 mJ / cm ² ). Then, a linear beam is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beam at this time is set to 80 to 98%. In this way, as shown in FIG.
103b can be obtained.

Then, using a first photomask, a resist pattern is formed on the crystalline semiconductor layer 1103b by photolithography, and the crystalline semiconductor layer is divided into islands by dry etching. C)
Then, island-shaped semiconductor layers 1104 to 1108 are formed as shown in FIG. The semiconductor layer 1108 has a first region that will be an active layer of a pixel TFT later and a second region that will be a lower electrode of a storage capacitor later. A mixed gas of CF ₄ and O ₂ is used for dry etching of the crystalline silicon film.

In order to control the threshold voltage (Vth) of the TFT, an impurity element imparting a p-type is added to such an island-like semiconductor layer in an amount of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ . The concentration may be added to the entire surface of the island-shaped semiconductor layer. The impurity element imparting p-type to the semiconductor includes boron (B),
Elements of Group 13 of the periodic table, such as aluminum (Al) and gallium (Ga), are known. As the method, an ion implantation method or an ion doping method (or an ion shower doping method) can be used, but the ion doping method is suitable for treating a large-area substrate. In the ion doping method, diborane (B ₂ H ₆ ) is used as a source gas and boron (B) is added. The implantation of such an impurity element is not always necessary and may be omitted. However, it is a method preferably used for keeping the threshold voltage of the n-channel TFT within a predetermined range.

The gate insulating film 1109 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, 12
It is formed from a silicon oxynitride film with a thickness of 0 nm. Also,
A silicon oxynitride film formed by adding O ₂ to SiH ₄ and N ₂ O is a preferable material for this application because the fixed charge density in the film is reduced. In addition, SiH
_A silicon oxynitride film formed of ₄ , N ₂ O, and H ₂ is preferable because the density of interface defects with the gate insulating film can be reduced. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, a plasma CVD method is used.
TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed, the reaction pressure is 40 Pa, the substrate temperature is 300-400 ° C.,
High frequency (13.56 MHz) power density 0.5 to 0.8 W / cm ²
And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Then, as shown in FIG.
A heat-resistant conductive layer 1111 for forming a gate electrode is formed with a thickness of 200 to 400 nm (preferably, 250 to 350 nm) on the gate insulating film 1109 having the above shape. The heat-resistant conductive layer may be formed as a single layer, or may have a laminated structure including a plurality of layers such as two layers or three layers as necessary. The heat-resistant conductive layer referred to in this specification includes Ta, Ti, W
And alloys containing the above elements or alloy films combining the above elements are included. These heat-resistant conductive layers are formed by a sputtering method or a CVD method, and it is preferable to reduce the concentration of impurities contained in order to reduce the resistance.
It is good to be 0 ppm or less. In this embodiment, the W film is 300
It is formed with a thickness of nm. The W film may be formed by sputtering using W as a target, or tungsten hexafluoride (W
It can also be formed by a thermal CVD method using F ₆ ). In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistance is increased. From this, when the sputtering method is used, the purity is 99.
By using a 9999% W target and forming the W film with sufficient care so as not to mix impurities from the gas phase during film formation, a resistivity of 9 to 20 μΩcm can be realized.

On the other hand, when a Ta film is used for the heat-resistant conductive layer 1111, it can be similarly formed by a sputtering method. The Ta film uses Ar as a sputtering gas. Also,
When an appropriate amount of Xe or Kr is added to the gas at the time of sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for a gate electrode. Since the TaN film has a crystal structure close to the α phase, if the TaN film is formed under the Ta film,
A phase Ta film is easily obtained. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the heat-resistant conductive layer 1111. Thereby, the adhesion of the conductive film formed thereon is improved and the oxidation is prevented, and at the same time, the heat-resistant conductive layer 11 is formed.
It is possible to prevent a small amount of an alkali metal element contained in 11 from diffusing into the gate insulating film 1109 having the first shape. In any case, the heat-resistant conductive layer 1111 preferably has a resistivity in the range of 10 to 50 μΩcm.

Next, using a second photomask, resist masks 1112 to 1116 are formed by photolithography. Then, a first etching process (dry etching) is performed. In this embodiment, I
Using a CP etching apparatus, Cl ₂ was used as an etching gas.
And CF ₄ at a pressure of 1 Pa and an RF of 3.2 W / cm ² (13.5
6MHz) Power is applied to form plasma. 224mW / cm ² RF (13.56MHz) on substrate side (sample stage)
Power is applied, thereby applying a substantially negative self-bias voltage. Under these conditions, the etching rate of the W film is about 100 nm / min. In the first etching process, the time when the W film was just etched was estimated based on this etching rate, and the time obtained by increasing the etching time by 20% was set as the etching time.

As shown in FIG. 17B, the conductive layer 11 having the first tapered shape is formed by the first etching process.
17 to 1121 are formed. As in FIG. 19A, the angle of the tapered portion is formed at 15 to 30 degrees. In order to perform etching without leaving a residue, over-etching is performed to increase the etching time at a rate of about 10 to 20%. The selectivity ratio of the silicon oxynitride film (the first shape gate insulating film 1109) to the W film is 2
4 (typically 3), the surface of the silicon oxynitride film exposed by the over-etching process is 20 to 5
The second-layer gate insulating film 1133 is etched by about 0 nm, becomes thinner than the portion where the gate electrode is formed, and has a tapered shape along the tapered shape of the first conductive layer.

Then, a first doping process is performed to add an impurity element of one conductivity type to the island-shaped semiconductor layer. Here, a step of adding an n-type impurity element is performed. First
The conductive layers 11 having the first tapered shape are left as they are, leaving the masks 1112 to 1116 on which the conductive layers having the shapes shown in FIGS.
Using 17 to 1121 as a mask, an impurity element imparting n-type in a self-aligned manner is added by an ion doping method. A dose of 1 × 10 ¹³ is added so that an impurity element imparting n-type is added through the tapered portion at the end of the gate electrode and the gate insulating film so as to reach the semiconductor layer located thereunder.
Up to 5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 80 to 160
Performed as keV. 1 as an impurity element imparting n-type
An element belonging to Group V, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) was used. The first impurity region 112 is formed by such an ion doping method.
To 3 to 1127, an impurity element imparting n-type is added in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , and the second impurity region (A) 11 formed below the tapered portion is added.
To 28 to 1132, an impurity element imparting n-type is added in a concentration range of 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm ³ , although not necessarily uniform in the same region. Note that 1127b is a region (semiconductor layer 1108) to be a lower electrode of a storage capacitor later.
(A second area). Since the impurity element is added to the entire surface of the region to be the lower electrode, the conductivity of the lower electrode of the storage capacitor can be increased without increasing the number of steps.

In this step, in the second impurity regions (A) 1128 to 1132, the change in the concentration of the impurity element imparting n-type contained in at least the portion overlapping the first shape conductive layers 1117 to 1121 is as follows: This reflects the change in the thickness of the tapered portion. That is, the concentration of phosphorus (P) added to the second impurity regions (A) 1128 to 1132 gradually increases from the end of the conductive layer toward the inside in a region overlapping with the first shape conductive layer. The concentration will be lower.
This is because the concentration of phosphorus (P) reaching the semiconductor layer changes depending on the difference in the thickness of the tapered portion, and the change in the concentration is as shown in FIG. 19A-2.

Next, as shown in FIG. 17B, a second etching process (dry etching) is performed. The etching process is also performed by an ICP etching apparatus, using a mixed gas of CF ₄ and Cl ₂ as an etching gas, an RF power of 3.2 W / cm ² (13.56 MHz), and a bias power of 45 mW / cm ² (1
Etching is performed at a pressure of 1.0 Pa at 3.56 MHz. Conductive layers 1139-1 having the second shape formed under these conditions
143 are formed. A tapered portion is formed at the end, and the tapered shape gradually increases inward from the end. As compared with the first etching process, the proportion of the isotropic etching is increased due to the lower bias power applied to the substrate side, and the angle of the tapered portion is 30 to 6
0 °. In addition, the second shape gate insulating film 1133
Is etched by about 40 nm, and a third-shaped gate insulating film 1144 is newly formed. Note that the thinned gate insulating film 1144 includes a region serving as a dielectric of a storage capacitor, so that a storage capacitor with a large capacitance can be manufactured without increasing the number of steps.

Then, an impurity element imparting n-type is doped under the condition of a high acceleration voltage with a lower dose than in the first doping process. For example, when the accelerating voltage is 70 to 120
KeV, and a dose of 1 × 10 ¹³ / cm ² , so that the impurity concentration in a region overlapping with the conductive layers 1139 to 1143 having the second shape is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^3. To Thus, the second impurity region (B)
1145 to 1149 are formed. As shown in FIG. 19 (B-1), the taper angle θ2 is larger than θ1 in the second etching process because the etching focuses on shortening the width in the channel length direction. In addition, FIG.
As shown in 2), in the second doping treatment, the effect of the first impurity region can be neglected because the amount of added impurities is low.

Then, impurity regions 1156 and 1157 having a conductivity type opposite to one conductivity type are formed in the island-shaped semiconductor layers 1104 and 1106 forming the p-channel TFT. Also in this case, an impurity element imparting p-type conductivity is added using the second shape conductive layers 1139 and 1141 as a mask to form an impurity region in a self-aligned manner. At this time, the n-channel TFT
Island-shaped semiconductor layers 1105, 1107, 1108 forming
Is a resist mask 11 using a third photomask.
50 to 1152 are formed and the entire surface is covered. The impurity regions 1156 and 1157 formed here are formed of diborane (B
It is formed by an ion doping method using ₂ H ₆ ). The concentration of the impurity element imparting p-type in the impurity regions 1156 and 1157 is set to 2 × 10 ²⁰ to 2 × 10 ²¹ atoms / cm ³ .

However, this impurity region 1156,
1157 can be seen in detail divided into three regions containing an impurity element imparting n-type. The third impurity regions 1156a and 1157a are 1 × 10 ²⁰ to 1 × 10 ^21.
including an impurity element imparting n-type at a concentration of atoms / cm ³ ,
The fourth impurity regions (A) 1156b and 1157b are 1 ×
A fourth impurity region (B) 1156 containing an impurity element imparting n-type at a concentration of 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm ³ ;
c and 1157c contain an impurity element imparting n-type at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ . However, these impurity regions 1156b, 1156c, 11
The concentration of the p-type impurity element of 57b and 1157c is set to 1 × 10 ¹⁹ atoms / cm ³ or more, and the concentration of the p-type impurity element in the third impurity regions 1156a and 1157a is 1 By increasing the value from 0.5 to 3 times, the p-channel type TF
There is no problem because it functions as the source and drain regions of T. Further, a fourth impurity region (B)
The conductive layers 1156c and 1157c partially overlap the conductive layer 1139 or 1141 having the second tapered shape.

Next, a step of activating the n-type or p-type impurity element added at each concentration is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less,
Preferably in a nitrogen atmosphere of 0.1 ppm or less 400 ~
The heat treatment is performed at 700 ° C., typically 500 to 600 ° C. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours.
In the case where a plastic substrate having a low heat-resistant temperature is used as the substrate 1101, a laser annealing method is preferably used.

Subsequent to the activation step, the atmosphere gas is changed to 300 to
Heat treatment is performed at 450 ° C. for 1 to 12 hours to hydrogenate the island-shaped semiconductor layer. In this step, dangling bonds of 10 ¹⁶ to 10 ¹⁸ / cm ^{3 in} the island-like semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. In any case,
The defect density in the island-like semiconductor layers 1104 to 1108 is 10 ¹⁶
/ cm ³ or less.
What is necessary is just to give about 01-0.1 atomic%.

Next, a material 1155a containing aluminum (Al) as a main component is formed to form a storage capacitor, and a capacitor wiring 1155 serving as an upper electrode of the storage capacitor is formed as shown in FIG. . After that, a first interlayer insulating film 1158 is formed over the gate electrode and the gate insulating film. The first interlayer insulating film may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film combining these. In any case, the first interlayer insulating film 1158 is formed from an inorganic insulating material. The thickness of the first interlayer insulating film 1158 is 100 to 200 nm. Here, when a silicon oxide film is used, plasma CV
TEOS and O ₂ are mixed by the method D, the reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) is used.
z) It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . In the case of using a silicon oxynitride film, a silicon oxynitride film formed from SiH ₄ , N ₂ O, and NH ₃ by a plasma CVD method, or SiH ₄ , N ₂ O
May be formed using a silicon oxynitride film formed from the above.
The manufacturing conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² . Also,
A silicon oxynitride hydride film formed from SiH ₄ , N ₂ O, and H ₂ may be used. Similarly, a silicon nitride film can be formed from SiH ₄ and NH ₃ by a plasma CVD method.

By forming the second interlayer insulating film 1159 with an organic insulating material, the surface can be satisfactorily flattened. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. However, since it is hygroscopic and is not suitable as a protective film, it is preferable to use it in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the first interlayer insulating film 1158 as in this embodiment. .

After that, using a fourth photomask, a resist mask having a predetermined pattern is formed, and a contact hole formed in each island-shaped semiconductor layer and reaching an impurity region serving as a source region or a drain region is formed. The contact hole is formed by a dry etching method. In this case, the second interlayer insulating film 1159 made of an organic resin material is first etched by using a mixed gas of CF ₄ , O ₂ , and He as an etching gas.
The first interlayer insulating film 1158 is etched as F ₄ and O ₂ . Further, in order to increase the selectivity with respect to the island-shaped semiconductor layer, a contact hole can be formed by switching the etching gas to CHF ₃ and etching the third shape gate insulating film 1144.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, a resist mask pattern is formed by a fifth photomask, and source lines 1160 to 1164 and drain lines 1165 to 1168 are formed by etching. . The pixel electrode 1169 is formed together with the drain line. A pixel electrode 1171 represents a pixel electrode belonging to an adjacent pixel. Although not shown, in this embodiment, this wiring is formed by forming a Ti film with a thickness of 50 to 150 nm, forming a contact with an impurity region forming a source or drain region of the island-shaped semiconductor layer, and forming the Ti film. Aluminum (Al) is formed to have a thickness of 300 to 400 nm on top (shown as 1160a to 1169a in FIG. 18C).
Further, a transparent conductive film is formed thereon with a thickness of 80 to 120 nm (1160b to 1169b in FIG. 18C).
). Indium oxide zinc oxide alloy (In ₂ O ₃ —ZnO) and zinc oxide (ZnO) are also suitable materials for the transparent conductive film, and gallium (Ga) is added to increase the transmittance and conductivity of visible light. Zinc oxide (ZnO:
Ga) and the like can be suitably used.

Thus, the TFTs of the driving circuit 1300 and the pixel portions 130
A substrate having one pixel TFT can be completed. The driving circuit 1300 includes a first p-channel TFT 1
200, a first n-channel TFT 1201, a second p-type TFT
Channel type TFT 1202, second n-channel type TFT
A pixel TFT 1204 and a storage capacitor 1205 are formed in the pixel portion 1301 and the pixel portion 1301. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

First p-channel type T of drive circuit 1300
In the FT 1200, a conductive layer having a second tapered shape has a function as a gate electrode 1220, and a third impurity region 12 functioning as a channel formation region 1206, a source region or a drain region is formed in the island-shaped semiconductor layer 1104.
07a, a fourth impurity region (A) 1207b forming an LDD region not overlapping with the gate electrode 1220, and a fourth impurity region (B) 1207c partially forming an LDD region overlapping with the gate electrode 1220. ing.

The first n-channel TFT 1201 has:
The conductive layer having the second tapered shape is the gate electrode 122.
A first impurity region 1209 a functioning as a channel formation region 1208, a source region or a drain region in the island-shaped semiconductor layer 1105, and a second impurity region forming an LDD region which does not overlap with the gate electrode 1221. (A) 1209b, a second impurity region (B) 1 forming an LDD region partly overlapping with the gate electrode 1221
209c. Channel length 2-7
The length (Lov) of the portion where the second impurity region (B) 1209c overlaps with the gate electrode 1221 is 0.1 μm.
０．３0.3 μm. The length of this Lov is the gate electrode 12.
The thickness is controlled by the thickness of 21 and the angle of the tapered portion. By forming such an LDD region in an n-channel TFT, a high electric field generated in the vicinity of the drain region can be relaxed, hot carriers can be prevented from being generated, and deterioration of the TFT can be prevented.

Second p-channel type T of drive circuit 1300
Similarly, in the FT 1202, a conductive layer having a second tapered shape has a function as a gate electrode 1222, and a third impurity region 1211a functioning as a channel formation region 1210 and a source or drain region is formed in the island-shaped semiconductor layer 1106. And a fourth impurity region (A) 1211b forming an LDD region not overlapping with the gate electrode 1222, and a fourth impurity region (B) 1211c forming an LDD region partially overlapping the gate electrode 1222. I have.

Second n-channel T of drive circuit 1300
In the FT 1203, a conductive layer having a second tapered shape has a function as a gate electrode 1223, and the island-shaped semiconductor layer 1107 has a first impurity region 1212 functioning as a channel formation region 1212 and a source or drain region.
13a, a second impurity region (A) 1213b forming an LDD region not overlapping the gate electrode 1223, and a second impurity region (B) 1213c forming an LDD region partially overlapping the gate electrode 1223. ing. Like the second n-channel TFT 1201, the length of the portion where the second impurity region (B) 1213c overlaps with the gate electrode 1223 is 0.1 to 0.3 μm.

The drive circuit is formed by a logic circuit such as a shift register circuit or a buffer circuit, or a sampling circuit formed by analog switches. In FIG. 16B, the TFTs forming them have a single gate structure in which one gate electrode is provided between a pair of sources and drains. A gate structure may be used.

In the pixel TFT 1204, a conductive layer having a second tapered shape has a function as a gate electrode 1224, and the island-shaped semiconductor layer 1108 has a channel forming region 1212.
14a and 1214b, first impurity regions 1215a and 1217 functioning as a source region or a drain region,
The structure has a second impurity region (A) 1215b which forms an LDD region which does not overlap with the gate electrode 1224, and a second impurity region (B) 1215c which partially forms an LDD region which overlaps with the gate electrode 1224. . The length of the portion where the second impurity region (B) 1213c overlaps with the gate electrode 1224 is set to 0.1 to 0.3 μm. A region 1218 extending from the first impurity region 1217;
A storage capacitor 1205 is formed from an insulating layer formed in the same layer as the gate insulating film having the third shape and a capacitor wiring 1225 made of a material containing aluminum as a main component.

The storage capacitor 1205 has a small area and a large capacity because an impurity is added to the semiconductor layer 1218 and the insulating film 1144 having the third shape is thinner than other regions. The storage capacity.

The above configuration enables the structure of the TFT constituting each circuit to be optimized according to the specifications required by the pixel TFT and the driving circuit, thereby improving the operation performance and reliability of the semiconductor device. . Further, the activation of the LDD region, the source region, and the drain region is facilitated by forming the gate electrode with a conductive material having heat resistance. Further, when forming the LDD region overlapping with the gate electrode via the gate insulating film, the LDD region is formed by giving a concentration gradient to the impurity element added for the purpose of controlling the conductivity type, particularly in the vicinity of the drain region. Can be expected to increase the electric field relaxation effect.

In the case of an active matrix type liquid crystal display device, the first p-channel TFT 1200 and the first n-channel TFT 1201 are used for forming a shift register circuit, a buffer circuit, a level shifter circuit, etc. which emphasize high-speed operation. . FIG. 18B illustrates these circuits as a logic circuit portion 1302. Second impurity region (B) 120 of first n-channel type TFT 1201
9c has a structure emphasizing hot carrier measures. Further, in order to increase the breakdown voltage and stabilize the operation, as shown in FIG. 21A, the TFT of the logic circuit portion 1302 is connected to the first p-channel TFT 1280 and the first n
A channel type TFT 1281 may be used. This TF
T has a double gate structure in which two gate electrodes are provided between a pair of source and drain, and such a TFT can be similarly manufactured using the steps of this embodiment. In the first p-channel TFT 1280, channel formation regions 1236a and 1236b and third impurity regions 1238a and 1238 functioning as source or drain regions are formed in the island-shaped semiconductor layer.
39a, 1240a, fourth impurity regions (A) 1238b, 1239b, 1240b serving as LDD regions and fourth impurity regions (B) 1238c, 1239c, 1240c which partially overlap the gate electrode 1237 and serve as LDD regions.
The structure has. First n-channel TFT
1281 includes a channel formation region 124 in the island-shaped semiconductor layer.
1a, 1241b, first impurity regions 1243a, 1244a, 12 functioning as source or drain regions.
45a and a second impurity region (A) 12 to be an LDD region
43b, 1244b, 1245b and gate electrode 124
2 and second impurity regions (B) 1243c, 1244c, and 1245c that partially overlap with each other and serve as LDD regions. The channel length is 3 to 7 μm, the LDD region overlapping with the gate electrode is Lov, and the length in the channel length direction is 0.1 to 0.3 μm.

The sampling circuit 1303 composed of an analog switch has a second p
Channel type TFT 1202 and second n-channel type TFT
1203 can be applied. Since the sampling circuit places emphasis on measures against hot carriers and low off-current operation, as shown in FIG.
P-channel TFT 1282 and second n-channel TFT
It may be formed of FT1283. This second p-channel type TFT 1282 has a triple gate structure in which three gate electrodes are provided between a pair of source and drain, and such a TFT can be manufactured in the same manner by using the steps of this embodiment. In the second p-channel TFT 1282, channel formation regions 1246a, 1246b, 1212 are formed in the island-shaped semiconductor layer.
46c Third impurity regions 1249a, 1250a, 1251a, and 12 functioning as source or drain regions.
52a, fourth impurity region (A) 12 to be an LDD region
49b, 1250b, 1251b, 1252b and a fourth impurity region (B) 1249c, 1250c, 1251 which partially overlaps with the gate electrode 1247 and becomes an LDD region.
c, 1252c. In the second n-channel TFT 1283, the island-shaped semiconductor layer includes channel formation regions 1253a and 1253b, first impurity regions 1255a and 1255 functioning as source or drain regions.
The second impurity regions (A) 1255b, 1256b, 1257b serving as LDD regions and the second impurity regions (256A, 1257a) and the gate electrode 1254 partially overlap and serve as LDD regions.
Impurity regions (B) 1255c, 1256c, 1257
c. The channel length is 3 to 7 μm, the LDD region overlapping with the gate electrode is Lov, and the length in the channel length direction is 0.1 to 0.3 μm.

As described above, whether the structure of the gate electrode of the TFT is a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided between a pair of source and drain is determined according to the characteristics of the circuit. It is only necessary for the person to choose appropriately. According to this embodiment, an active matrix liquid crystal display device as shown in Embodiment 3 and a reflection type liquid crystal display device can be manufactured.

[Embodiment 7] The active matrix substrate manufactured in Embodiment 6 can be applied to a reflection type display device as it is. On the other hand, in the case of a transmissive liquid crystal display device, a pixel electrode provided for each pixel in the pixel portion may be formed of a transparent electrode. In this embodiment, a method for manufacturing an active matrix substrate corresponding to a transmission type liquid crystal display device will be described with reference to FIGS.
2 will be described.

The active matrix substrate is manufactured in the same manner as in the sixth embodiment. In FIG. 22A, a conductive metal film is formed for a source wiring and a drain wiring by a sputtering method or a vacuum evaporation method. This configuration is shown in FIG.
2 (B), the Ti film 1256a is
It is formed to a thickness of about 150 nm, and a contact is formed with a semiconductor film forming a source or drain region of the island-shaped semiconductor layer. An Al film 1256 is superimposed on the Ti film 1256a.
b is formed to a thickness of 300 to 400 nm, and a Ti film 1
256c or titanium nitride (TiN) film of 100 to 20
It is formed with a thickness of 0 nm to form a three-layer structure. After that, a transparent conductive film is formed over the entire surface, and a pixel electrode 1257 is formed by patterning and etching using a photomask. The pixel electrode 1257 is formed on a second interlayer insulating film made of an organic resin material, and has a portion overlapping with the drain line 1256 of the pixel TFT 1204 without through a contact hole to form an electrical connection.

In FIG. 22C, first, a transparent conductive film is formed over the second interlayer insulating film, patterning and etching are performed to form a pixel electrode 1258, and then the drain line 1259 is connected to the pixel electrode 1258. This is an example in which a connection portion is formed without a contact hole. Drain line 12
59, a Ti film 1259a is formed to a thickness of 50 to 150 nm as shown in FIG. 22D, and a contact is formed with the semiconductor film forming the source or drain region of the island-shaped semiconductor layer. Al film 125 overlaid on top
9b is provided in a thickness of 300 to 400 nm. With this structure, the pixel electrode 1258 is connected to the drain wiring 125
9 comes into contact with only the Ti film 1259a. As a result, it is possible to reliably prevent the transparent conductive film material from directly reacting with Al.

The material of the transparent conductive film is indium oxide (I
n ₂ O ₃ ) and indium tin oxide alloy (In ₂ O ₃ —S
nO ₂ ; ITO) or the like can be formed by a sputtering method, a vacuum evaporation method, or the like. The etching of such a material is performed using a hydrochloric acid-based solution. However, in particular, since etching of ITO easily generates residues, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used in order to improve the etching processability. Since the indium oxide zinc oxide alloy has excellent surface smoothness and excellent thermal stability with respect to ITO, in the configuration shown in FIGS. 22A and 22B, the aluminum film 1
It is possible to prevent the corrosion reaction of 256b from coming into contact with the pixel electrode 1257. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO :) to which gallium (Ga) is added to increase the transmittance and conductivity of visible light.
Ga) can be used.

In Example 6, an active matrix substrate capable of manufacturing a reflection type liquid crystal display device was manufactured using five photomasks. However, by adding one more photomask (total of six), a transmission type liquid crystal display device was manufactured. An active matrix substrate corresponding to the device can be completed.

[Embodiment 8] In this embodiment, Embodiments 1, 6 and
Another manufacturing method of the crystalline semiconductor layer for forming the active layer of the TFT of the active matrix substrate indicated by 7 will be described. The crystalline semiconductor layer is formed by crystallizing an amorphous semiconductor layer by a thermal annealing method, a laser annealing method, an RTA method, or the like. In addition, a catalytic element disclosed in JP-A-7-130652 is used. A crystallization method can also be applied. An example in that case will be described with reference to FIG.

As shown in FIG. 23A, a base film 3102a and a base film 3102a are formed on a glass substrate 3101 in the same manner as in the first embodiment.
3102b, a semiconductor layer 3103 having an amorphous structure
It is formed with a thickness of 5 to 80 nm. The amorphous semiconductor layer includes an amorphous silicon (a-Si) film, an amorphous silicon germanium (a-SiGe) film, and an amorphous silicon carbide (a-Si).
C) film, amorphous silicon tin (a-SiSn) film and the like can be applied. These amorphous semiconductor layers contain 0.1% of hydrogen.
It may be formed so as to contain about 40 atomic%. For example, an amorphous silicon film is formed with a thickness of 55 nm. Then, a layer 3104 containing a catalyst element is formed by a spin coating method in which an aqueous solution containing a catalyst element of 10 ppm by weight is applied by rotating the substrate with a spinner. The catalytic elements include nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), and lead (P
b), cobalt (Co), platinum (Pt), copper (Cu),
Gold (Au) or the like. Layer 31 containing this catalytic element
In 04, the catalyst element layer may be formed to a thickness of 1 to 5 nm by a printing method, a spray method, a bar coater method, a sputtering method or a vacuum evaporation method other than the spin coating method.

In the crystallization step shown in FIG. 23B, a heat treatment is first performed at 400 to 500 ° C. for about 1 hour to reduce the hydrogen content of the amorphous silicon film to 5 atom% or less. If the hydrogen content of the amorphous silicon film has this value from the beginning after film formation, this heat treatment is not always necessary. Then, thermal annealing is performed in a nitrogen atmosphere at 550 to 600 ° C. for 1 to 8 hours using a furnace annealing furnace. Through the above steps, a crystalline semiconductor layer 3105 made of a crystalline silicon film can be obtained (FIG. 23).
(C)). However, when the crystalline semiconductor layer 3105 formed by this thermal annealing is macroscopically observed with an optical microscope, an amorphous region may be locally observed to remain locally. Similarly, in Raman spectroscopy, an amorphous component having a broad peak at 480 cm ^-1 is observed. Therefore, increasing the crystallinity by treating the crystalline semiconductor layer 3105 by the laser annealing method described in Embodiment 1 after the thermal annealing can be applied as an effective means.

FIG. 24 shows an embodiment of a crystallization method using a catalytic element, in which a layer containing the catalytic element is formed by sputtering. First, a base film 3202a and 3202b and a semiconductor layer 3203 having an amorphous structure are formed over a glass substrate 3201 to a thickness of 25 to 80 nm. Then, an oxide film (not shown) of about 0.5 to 5 nm is formed on the surface of the semiconductor layer 3203 having an amorphous structure. For the oxide film having such a thickness, a corresponding film may be positively formed by a plasma CVD method, a sputtering method, or the like.
The surface of the semiconductor layer 3203 having an amorphous structure may be exposed in an oxygen atmosphere in which the substrate is heated to 00 to 300 ° C. and turned into a plasma, or may be exposed to a solution containing aqueous hydrogen peroxide (H ₂ O ₂ ). The surface of the semiconductor layer 3203 having a crystalline structure may be formed by exposing the surface. Alternatively, it can be formed by irradiating ultraviolet light in an atmosphere containing oxygen to generate ozone, and exposing the semiconductor layer 3203 having an amorphous structure in the ozone atmosphere.

As described above, the layer 3204 containing the catalyst element is formed by the sputtering method on the semiconductor layer 3203 having an amorphous structure having a thin oxide film on the surface. The thickness of this layer is not limited, but may be about 10 to 100 nm. For example, with Ni as a target, Ni
Forming a film is an effective method. In the sputtering method, part of the high-energy particles composed of the catalyst element accelerated by an electric field also fly to the substrate side, and the oxide layer formed on or near the surface of the semiconductor layer 3203 having an amorphous structure is formed. Driven into the film. Although the ratio varies depending on the plasma generation conditions and the bias state of the substrate, preferably, the amount of the catalytic element implanted into the vicinity of the surface of the semiconductor layer 3203 having an amorphous structure or the oxide film is set to 1
It is preferable that the density be about 10 ¹¹ to 1 10 ¹⁴ atoms / cm ³ .

After that, the layer 3204 containing the catalyst element is selectively removed. For example, when this layer is formed of a Ni film, it can be removed with a solution such as nitric acid, or can be treated with an aqueous solution containing hydrofluoric acid to obtain a Ni film.
The oxide film formed over the film and the semiconductor layer 3203 having an amorphous structure can be removed at the same time. In any case, the amount of the catalyst element in the vicinity of the surface of the semiconductor layer 3203 having an amorphous structure is set to be about 1 × 10 ¹¹ to 1 × 10 ¹⁴ atoms / cm ³ . Then, as shown in FIG.
The crystallization step by thermal annealing is performed in the same manner as in FIG. 23B, whereby a crystalline semiconductor layer 3205 can be obtained (FIG. 24C).

When an island-shaped semiconductor layer is manufactured from the crystalline semiconductor layers 3105 and 3205 manufactured in FIG. 23 or FIG. 24, an active matrix substrate can be completed in the same manner as in the first and sixth embodiments. However, when a catalyst element that promotes silicon crystallization is used in the crystallization step, a very small amount (1 × 10 ¹⁷ to 1 × 10 ¹⁷⁾ is contained in the island-shaped semiconductor layer.
^{About 19} atoms / cm ³ ). Of course, the TFT can be completed in such a state, but it is more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing the catalytic element is a means utilizing a gettering action by phosphorus (P).

The gettering treatment with phosphorus (P) for this purpose can be performed in the same step as the step of activating the impurity element. This situation will be described with reference to FIG. The concentration of phosphorus (P) necessary for gettering is high
The impurity concentration may be about the same as the impurity concentration of the p-type impurity region, and the thermal annealing in the activation step transfers the catalyst element from the channel formation region of the n-channel TFT and the p-channel TFT to the impurity region containing phosphorus (P) at that concentration. It can be segregated (in the direction of the arrow shown in FIG. 25). As a result, about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ of a catalytic element segregated in the impurity region. The TFT thus manufactured has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and good characteristics can be achieved.

[Embodiment 9] In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 6 will be described. First, as shown in FIG. 8A, a spacer including a columnar spacer is formed on the active matrix substrate in the state of FIG. 18B. The spacer may be provided by scattering particles of several μm, but here, a method of forming a resin film over the entire surface of the substrate and then patterning the resin film is adopted. Although there is no limitation on the material of such a spacer, for example, NN700 manufactured by JSR Corporation is applied by a spinner and then formed into a predetermined pattern by exposure and development processing. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like. The shape of the spacer manufactured in this manner can be varied depending on the conditions of the exposure and the development processing. When combined, the mechanical strength of the liquid crystal display panel can be secured. The shape is not particularly limited, such as a cone or a pyramid. For example, when the shape is a cone, specifically, the height is 1.2 to 5 μm, the average radius is 5 to 7 μm, the average radius and the radius of the bottom portion. Is set to 1: 1.5. At this time, the taper angle of the side surface is set to ± 15 ° or less.

The arrangement of the spacers may be arbitrarily determined, but preferably, as shown in FIG. 8A, in the pixel portion, the columnar spacer is overlapped with the contact portion 1231 of the pixel electrode 1169 so as to cover the portion. 1406 may be formed. Since the flatness of the contact portion 1231 is impaired and the liquid crystal is not well aligned in this portion, disclination and the like are formed by forming the columnar spacer 1406 in such a manner that the contact portion 1231 is filled with the resin for the spacer. Can be prevented. Further, spacers 1405a to 1405e are also provided on the TFT of the driving circuit.
Is formed. This spacer may be formed over the entire surface of the driver circuit portion, or may be provided so as to cover the source line and the drain line as shown in FIG.

Then, an alignment film 1407 is formed. Usually, a polyimide resin is used for the alignment film of the liquid crystal display element. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. The area not rubbed in the rubbing direction from the end of the columnar spacer 1406 provided in the pixel portion was set to 2 μm or less. In the rubbing process, the generation of static electricity often poses a problem. However, the spacers 1405a to 1405e formed on the TFT of the drive circuit cause the TFT to generate static electricity.
The effect of protecting can be obtained. Although not described in the drawings, a structure in which the alignment film 1407 is formed first and then the spacers 1406 and 1405a to 1405e are formed may be employed.

On the opposite substrate 1401 on the opposite side, the light shielding film 1
402, a transparent conductive film 1403, and an alignment film 1404 are formed. As the light-shielding film 1402, a Ti film, a Cr film, an Al film, or the like is formed with a thickness of 150 to 300 nm. Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached with a sealant 1408. A filler (not shown) is mixed in the sealant 1408,
This filler and spacers 1406, 1405a-140
By 5e, the two substrates are bonded at a uniform interval. After that, a liquid crystal material 1409 is injected between the two substrates. A known liquid crystal material may be used as the liquid crystal material.
For example, in addition to the TN liquid crystal, a thresholdless antiferroelectric mixed liquid crystal exhibiting electro-optical response in which the transmittance continuously changes with respect to an electric field can be used. Some of the thresholdless antiferroelectric mixed liquid crystals exhibit a V-shaped electro-optical response characteristic. Thus, the active matrix liquid crystal display device shown in FIG. 8B is completed.

FIG. 9 is a top view of such an active matrix substrate, and is a top view showing a positional relationship between a pixel portion and a driving circuit, a spacer, and a sealant. Example 1
On the glass substrate 1101 described above, a scanning signal driving circuit 1605 and an image signal driving circuit 1606 are provided as driving circuits around the pixel portion 1604. In addition, other C
A signal processing circuit 1607 such as a PU or a memory may be added. These drive circuits are connected to the connection wiring 16.
03 is connected to the external input / output terminal 1602. In the pixel portion 1604, the gate wiring group 1608 extending from the scanning signal driving circuit 1605 and the image signal driving circuit 16
The source line group 1609 extending from the pixel line 06 intersects in a matrix to form pixels, and each pixel has a pixel TF
T1204 and a storage capacitor 1205 are provided.

In FIG. 8, the columnar spacer 1406 provided in the pixel portion may be provided for all the pixels, but is provided every several to several tens of pixels arranged in a matrix as shown in FIG. May be. That is, the ratio of the number of spacers to the total number of pixels constituting the pixel portion is 20 to 1
It can be set to 00%. Further, the spacers 1405a to 1405e provided in the driver circuit may be provided so as to cover the entire surface, or may be provided in accordance with the positions of the source and drain wirings of each TFT. In FIG. 9, the arrangement of the spacers provided in the drive circuit is indicated by 1610 to 1612. Then, the sealant 1613 illustrated in FIG. 9 includes the pixel portion 1604 on the substrate 1101, the scan signal driver circuit 1605, the image signal driver circuit 1606, and the other signal processing circuits 160.
7 and inside the external input / output terminal 1602.

The liquid crystal display device having such a configuration can be formed by using the active matrix substrates shown in the sixth and seventh embodiments. A reflective liquid crystal display device can be obtained by using the active matrix substrate described in Embodiment 6, and a transmissive liquid crystal display device can be obtained by using the active matrix substrate described in Embodiment 7.

[Embodiment 10] In this embodiment, the T
A semiconductor device (electric device) incorporating an active matrix type liquid crystal display device using an FT circuit will be described.

As such a semiconductor device, a video camera, a digital camera, a digital video disc player, a projector (rear or front type), a head mounted display (goggle type display), a personal computer, a portable information terminal (mobile computer, A mobile phone or an electronic book). Examples of these are shown in FIGS. 26, 27 and 28.

FIG. 26A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.

FIG. 26B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102 and other signal control circuits.

FIG. 26C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other signal control circuits.

FIG. 26D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on. The present invention can be applied to the display portion 2302 and other signal control circuits.

FIG. 26E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.

FIG. 26F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502 and other signal control circuits.

FIG. 27A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other signal control circuits.

FIG. 27B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to the liquid crystal display device 2808 forming a part of the signal control circuit 702 and other signal control circuits.

FIG. 27C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 27A and 27B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 27D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 27C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 27D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 27, a case where a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and an EL display device are not shown.

FIG. 28A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention is applied to the audio output unit 2902 and the audio input unit 2
903, the display portion 2904, and other signal control circuits.

FIG. 28B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003 and other signal circuits.

FIG. 28C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to semiconductor devices in all fields. Further, the semiconductor device of the present embodiment can be realized by using a configuration composed of any combination of the first to ninth embodiments.

[Embodiment 11] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described. The EL display device is a light emitting device or a light emitting diode (Li).
ght emitting diode). Further, the EL device in this specification includes, for example, a triplet light emitting device or a singlet light emitting device.

FIG. 29A is a top view of an EL display device using the present invention. In FIG. 29A, reference numeral 4010 denotes a substrate; 4011, a pixel portion; 4012, a source driver circuit; 4013, a gate driver circuit;
And connected to the external device.

At this time, at least the pixel portion, preferably the drive circuit and the pixel portion are surrounded so as to surround the cover material 600.
0, sealing material (also referred to as housing material) 7000,
A sealing material (a second sealing material) 7001 is provided.

FIG. 29B shows a cross-sectional structure of the EL display device of this embodiment.
A driving circuit TFT 4022 (here, a CMOS circuit combining an n-channel TFT and a p-channel TFT is illustrated) 4022 and a pixel portion TFT 40
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed.

TFT 4022 for driving circuit, TF for pixel portion
When T4023 is completed, a pixel electrode 4027 made of a transparent conductive film electrically connected to the drain of the pixel portion TFT 4023 is formed on an interlayer insulating film (flattening film) 4026 made of a resin material. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.

Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the EL layer 4029, the cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, as the cathode 4030,
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

The cathode 40 in the region indicated by 4031
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

The passivation film 6003 and the filler 600 cover the surface of the EL element thus formed.
4. The cover material 6000 is formed.

Further, a sealing material is provided inside the cover material 6000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

Further, a spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

The wiring 4016 is made of a sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001.

[Embodiment 12] In this embodiment, an example in which an EL display device having a mode different from that of Embodiment 11 is manufactured using the present invention will be described with reference to FIGS. 29A and 29B denote the same parts, and a description thereof will not be repeated.

FIG. 30A is a top view of the EL display device of this embodiment, and FIG. 30B is a cross-sectional view taken along line AA ′ of FIG.

According to the eleventh embodiment, up to the passivation film 6003 is formed to cover the surface of the EL element.

Further, the filling material 6 is formed so as to cover the EL element.
004 is provided. This filler 6004 is used for the cover material 60.
It also functions as an adhesive for bonding 00. As the filler 6004, PVC (polyvinyl chloride),
Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0184] A spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Fiber)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

Next, using the filler 6004, the cover material 6
After bonding 000, the side surface of filler 6004 (exposed surface)
Frame material 6001 is attached so as to cover. The frame material 6001 is a sealing material (functions as an adhesive)
Glued by 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

The wiring 4016 is made of a sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.

[Embodiment 13] FIG. 31 shows a more detailed sectional structure of a pixel portion in an EL display panel, FIG. 32A shows a top view structure, and FIG. 32B shows a circuit diagram. In FIG. 31, FIG. 32 (A) and FIG.

In FIG. 31, a switching TFT 3502 provided on a substrate 3501 is formed using the n-channel TFT of the present invention (see Examples 1 to 9).
In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted.
However, by using a double gate structure, substantially two T
There is an advantage that the FT has a structure in which the FTs are connected in series, and the off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. Further, a p-channel TFT may be used.

The current control TFT 3503 is formed using the n-channel TFT of the present invention (see Examples 1 to 9). At this time, the drain wiring 35 of the switching TFT 3502 is connected to the current controlling TFT by the wiring 36.
Is electrically connected to the gate electrode 37. Also, 3
The wiring indicated by 8 is a gate wiring for electrically connecting the gate electrodes 39a and 39b of the switching TFT 3502.

Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the LDD region is provided on the drain side of the current controlling TFT so as to overlap the gate electrode via the gate insulating film is extremely effective.

However, when the driving voltage is 10 V or less (typically 5 V or less), the above-described problem does not occur. Therefore, as shown in FIG.
A TFT having a structure in which a source region and a drain region are provided with a semiconductor layer 503 and a channel formation region interposed therebetween may be used. Alternatively, as shown in FIG. 35B, a TFT having a structure in which a semiconductor layer includes an LDD region formed so as to sandwich a channel formation region and a source region and a drain region provided outside the LDD region is employed. Is also good.

In this embodiment, the current controlling TFT 35 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 32A, the wiring to be the gate electrode 37 of the current controlling TFT 3503 is 35
In a region indicated by 04, the region overlaps with the drain wiring 40 of the current control TFT 3503 via an insulating film. At this time, 3
In the region indicated by 504, a capacitor is formed. This capacitor 3504 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 3503. The drain wiring 40 is connected to a current supply line (power supply line) 3506, and a constant voltage is constantly applied.

The first passivation film 4 is formed on the switching TFT 3502 and the current control TFT 3503.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the steps due to the TFT using the flattening film 42. Since an EL layer formed later is very thin, light emission failure may occur due to the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
503 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed.

The light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by the banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green),
Light emitting layers corresponding to each color of B (blue) may be separately formed.
As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.

There are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge.
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, "Polymers f
or Light Emitting Diodes ", Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As specific light emitting layers, cyanopolyphenylene vinylene is used for a red light emitting layer, polyphenylene vinylene is used for a green light emitting layer, and polyphenylene vinylene or polyalkylphenylene is used for a blue light emitting layer. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of the organic EL material that can be used as the light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example is shown in which a polymer material is used for the light emitting layer, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
The EL layer has a laminated structure in which a hole injection layer 46 made of (polythiophene) or PAni (polyaniline) is provided. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the EL element 3
505 is completed. Note that the EL element 3505 mentioned here
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in (A), the pixel electrode 43 substantially matches the area of the pixel, and the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 31 and includes a switching TFT having a sufficiently low off-state current value and a current controlling portion having a strong resistance to hot carrier injection. And a TFT. Therefore,
EL with high reliability and good image display
A display panel is obtained.

The structure of this embodiment can be implemented by freely combining with the structures of Embodiments 1 to 9.
Further, it is effective to use the EL display panel of this embodiment as the display unit of the electric device of the tenth embodiment.

[Embodiment 14] In this embodiment, Embodiment 13 will be described.
A structure in which the structure of the EL element 3505 is inverted in the pixel portion shown in FIG. FIG. 33 is used for the description. The structure of FIG. 31 is different from the structure of FIG. 31 only in the EL element and the current controlling TFT.

In FIG. 33, a current control TFT 350
3 is formed using a p-channel TFT. Embodiments 1 to 9 may be referred to for the manufacturing process.

In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

Then, the banks 51a and 51b made of an insulating film are used.
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 3701 is formed.

In the case of this embodiment, the light generated in the light emitting layer 52 is radiated toward the substrate on which the TFT is formed as indicated by the arrow.

Note that the configuration of this embodiment can be implemented by freely combining with the configurations of Embodiments 1 to 9.
Further, it is effective to use the EL display panel of this embodiment as the display unit of the electric device of the tenth embodiment.

[Embodiment 15] In this embodiment, FIG.
FIGS. 34A to 34C illustrate an example in which the pixel has a structure different from that of the circuit diagram illustrated in FIG. In this embodiment, reference numeral 3801 denotes a switching TFT 380.
2 is a source wiring, and 3803 is a switching TFT 38.
02, a gate wiring 3804, a current controlling TFT 38,
05 is a capacitor, 3806 and 3808 are current supply lines,
Reference numeral 3807 denotes an EL element.

FIG. 34A shows an example in which a current supply line 3806 is shared between two pixels. That is, the feature is that two pixels are formed to be line-symmetric with respect to the current supply line 3806. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 34 (B) shows the current supply line 380
8 is provided in parallel with the gate wiring 3803. Note that in FIG. 34B, the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other; however, as long as the wiring is formed in a different layer,
They can be provided so as to overlap with each other via an insulating film. In this case, since the current supply line 3808 and the gate wiring 3803 can share an occupied area, the pixel portion can have higher definition.

In FIG. 34C, a current supply line 3808 is provided in parallel with the gate wiring 3803 in the same manner as in the structure of FIG. 34B, and two pixels are connected to the current supply line 3808.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 3808 so as to overlap with one of the gate wirings 3803. In this case, the number of current supply lines can be reduced, so that the pixel portion can have higher definition.

The structure of this embodiment can be implemented by freely combining with the structures of Embodiments 1 to 9.
Further, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electric device of Embodiment 10.

[Embodiment 16] FIG. 32 shown in Embodiment 13
In FIGS. 7A and 7B, the capacitor 3504 is provided to hold the voltage applied to the gate of the current control TFT 3503; however, the capacitor 3504 can be omitted. In the case of Embodiment 13, the current control TF
N of the present invention as shown in Examples 1 to 9 as T3503
Since a channel type TFT is used, an LDD region is provided so as to overlap with a gate electrode with a gate insulating film interposed therebetween. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region. The present embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 3504.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

Further, FIGS. 34 (A) to 34 (A) to
Similarly, in the structure of (C), the capacitor 3805 can be omitted.

The structure of this embodiment can be implemented by freely combining with the structures of Embodiments 1 to 9.
Further, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electric device of Embodiment 10.

[0224]

According to the present invention, in a semiconductor device in which a plurality of functional circuits are formed on the same substrate (specifically, an electro-optical device in this case), a semiconductor layer serving as a lower electrode of a storage capacitor is formed. Since the impurity element is added, the conductivity of the lower electrode can be increased. Further, since the gate insulating film thinned in the etching step is used as the dielectric of the storage capacitor, a large area can be obtained with a small area without increasing the number of steps. A storage capacitor having capacity can be formed. In addition, the aperture ratio can be increased because the storage capacitor requires a small area.

Further, it is possible to arrange TFTs having appropriate performance according to the specifications required by the functional circuit, and it is possible to greatly improve the operation characteristics.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 6 is a top view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 7 is a top view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 9 is a top view illustrating input / output terminals, wiring, circuit arrangement, spacers, and sealants of a liquid crystal display device.

FIG. 10 is a top view illustrating input / output terminals and a wiring circuit arrangement of a liquid crystal display device.

FIG. 11 is a cross-sectional view illustrating a structure of a liquid crystal display device.

FIG. 12 is a perspective view illustrating a structure of a liquid crystal display device.

FIG. 13 is a top view illustrating a pixel portion.

FIG. 14 is a circuit block diagram of a liquid crystal display device.

FIG. 15 is a diagram showing a positional relationship between a gate electrode and an LDD region.

FIG. 16 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 17 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 18 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 19 illustrates a concentration distribution of an impurity element in an LDD region.

FIG. 20 is a sectional view showing a contact structure between a terminal portion of a connection wiring and an anisotropic conductive film.

FIG. 21 is a cross-sectional view illustrating a TFT of a driver circuit.

FIG. 22 is a cross-sectional view illustrating a configuration of a pixel TFT.

FIG. 23 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor layer.

FIG. 24 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor layer.

FIG. 25 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor layer.

FIG 26 illustrates an example of a semiconductor device.

FIG. 27 illustrates an example of a semiconductor device.

FIG 28 illustrates an example of a semiconductor device.

FIG 29 illustrates a structure of an EL display device.

FIG. 30 illustrates a structure of an EL display device.

FIG. 31 illustrates a structure of an EL display device.

FIG. 32 illustrates a structure of an EL display device.

FIG. 33 illustrates a structure of an EL display device.

FIG. 34 illustrates a structure of an EL display device.

FIG. 35 illustrates a structure of an EL display device.

FIG. 36 is a view showing the shape of a columnar spacer.

FIG. 37 illustrates a manufacturing process of an input terminal portion of a liquid crystal display device.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 29/78 617A 617K

Claims (17)

[Claims] 1. A semiconductor device including a pixel portion having a pixel TFT and a storage capacitor, wherein the pixel TFT includes a channel forming region, a source region, and a drain region provided in a first region of a semiconductor layer. A gate insulating film in contact with the first region and a gate electrode on the gate insulating film, wherein the storage capacitor has a second region of the semiconductor layer, an insulating film in contact with the second region, and the insulating film The second region includes an impurity element imparting n-type or p-type, and a thickness of an insulating film in contact with the second region is in contact with the first region. A semiconductor device having a thickness smaller than a thickness of a gate insulating film. 2. A semiconductor device including a pixel portion having a pixel TFT and a storage capacitor, wherein the pixel TFT includes a channel forming region, a source region, and a drain region provided in a first region of a semiconductor layer. A gate insulating film in contact with the first region and a gate electrode on the gate insulating film, wherein the pixel TFT is an n-channel TFT, and the storage capacitor is a second region of the semiconductor layer; An insulating film in contact with the second region and a capacitor wiring on the insulating film, wherein the second region contains one impurity element imparting one conductivity type;
The concentration is in the range of × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ , and the thickness of the insulating film in contact with the second region is equal to the thickness of the gate insulating film in contact with the first region. A semiconductor device having a thickness smaller than that of the semiconductor device. 3. A semiconductor device having a pixel portion and a driver circuit on the same substrate, wherein the driver circuit has a p-channel TFT and an n-channel TFT, and the n-channel TFT is formed in a semiconductor layer. A channel formation region, a source region and a drain region, an LDD region, a gate insulating film in contact with the semiconductor layer, and a gate electrode over the gate insulating film, wherein the gate electrode has a first conductive layer and a second conductive layer. A semiconductor device having a layer, wherein the second conductive layer is formed so as to overlap the LDD region with the gate insulating film interposed therebetween. 4. A semiconductor device having a pixel portion and a driver circuit on the same substrate, wherein the pixel portion has a pixel TFT and a storage capacitor, and the pixel TFT is provided in a first region of a semiconductor layer. A channel forming region, a source region and a drain region, a gate insulating film in contact with the first region, and a gate electrode on the gate insulating film. The pixel TFT is an n-channel TFT, The capacitor has a second region of the semiconductor layer, an insulating film in contact with the second region, and a capacitor wiring on the insulating film, and the driving circuit has a p-channel TFT and an n-channel TFT The semiconductor layer of the n-channel TFT of the driving circuit includes a channel forming region, a source region and a drain region,
A region, a gate insulating film in contact with the semiconductor layer, and a gate electrode on the gate insulating film, wherein the gate electrode has a first conductive layer and a second conductive layer, and the second conductive layer Is the L through the gate insulating film.
The insulating film is formed so as to overlap the DD region and is made of the same material as the capacitor wiring. The thickness of the insulating film in contact with the second region is smaller than the thickness of the gate insulating film in contact with the first region. A semiconductor device characterized by the above-mentioned. 5. The capacitor according to claim 4, wherein the capacitor wiring forming the storage capacitor and the second conductive layer are formed of aluminum (A).
1) A semiconductor device comprising an element selected from copper or copper (Cu), a compound containing the element, or a compound material combining the elements. 6. The method according to claim 4, wherein the first conductive layer is made of tungsten (W), tantalum (Ta), titanium (T
i), an element selected from molybdenum (Mo), a compound containing the element, a compound combining the elements, a nitride containing the element, or a silicide containing the element as a component. A semiconductor device characterized by being made of a material. 7. A semiconductor device having a pixel portion and a driver circuit over the same substrate, wherein the pixel portion has an n-channel TFT and a storage capacitor, wherein the storage capacitor is a semiconductor layer and a semiconductor layer. An insulating film serving as a dielectric of a storage capacitor that is in contact with the insulating film, and a capacitor wiring formed on the insulating film, wherein the semiconductor layer includes 1 × an impurity element imparting one conductivity type.
The driving circuit includes a p-channel TFT and an n-channel TFT, each having a concentration of 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ^3.
An FT, a p-channel TFT of the driver circuit and an n-channel TFT of the driver circuit each include a semiconductor layer, a gate insulating film in contact with the semiconductor layer, and a gate electrode over the gate insulating film; The semiconductor device, wherein the gate electrode has a shape having a tapered portion, and a thickness of the insulating film is smaller than a region where the n-channel TFT is formed. 8. A semiconductor device having a pixel portion and a driver circuit on the same substrate, wherein the pixel portion has an n-channel TFT and a storage capacitor, and the n-channel TFT of the pixel portion has a channel forming region. A semiconductor layer having an LDD region outside the channel formation region, a source region or a drain region outside the LDD region, a gate insulating film in contact with the semiconductor layer, and a gate electrode on the gate insulating film. The driving circuit includes a p-channel TFT and an n-channel TFT
An n-channel TFT of the driver circuit, the semiconductor layer including a channel formation region, an LDD region outside the channel formation region, and a source region or a drain region outside the LDD region; A gate insulating film in contact with the semiconductor layer; and a gate electrode on the gate insulating film. The gate electrode of the n-channel TFT in the pixel portion and the gate electrode of the n-channel TFT in the driving circuit are tapered. And an insulating film that is formed so as to partially overlap the LDD region and that is a dielectric of the storage capacitor formed continuously from the gate insulating film has a thickness greater than that of other regions. A semiconductor device characterized by being thin. 9. The method of claim 1, claim 2, claim 4, or claim 7.
In any one of the above, the capacitance wiring forming the storage capacitor is made of an element selected from aluminum (Al) or copper (Cu), a compound containing the element, or a compound material combining the elements. A semiconductor device characterized by the above-mentioned. 10. A first step of forming an amorphous semiconductor film on a substrate having an insulating surface, and crystallizing the amorphous semiconductor film to form a crystalline semiconductor film and thereafter forming an amorphous semiconductor film in an island-like semiconductor layer. A second step of forming an insulating film so as to be in contact with the island-shaped semiconductor layer; a fourth step of forming a first conductive layer on the insulating film; A fifth step of dry-etching the conductive layer to form a gate electrode, a sixth step of adding an impurity element to the island-shaped semiconductor layer using the gate electrode as a mask, A seventh step of forming a conductive layer of: a. A part of the first conductive layer and a part of the LDD region in the n-channel TFT forming the drive circuit; Capacitor wiring is formed on the insulating film provided by The method for manufacturing a semiconductor device characterized by having, an eighth step of etching the second conductive layer. 11. The first conductive layer according to claim 10, wherein the first conductive layer is made of an element selected from tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo), or contains the element as a component. A compound, or a compound in which the above elements are combined, or a nitride containing the above elements,
A method for manufacturing a semiconductor device, which is formed using a material selected from silicides containing the above elements. 12. The semiconductor device according to claim 10, wherein said second conductive layer and said capacitor wiring are made of aluminum (Al), copper (C
A method for manufacturing a semiconductor device, which is formed using an element selected from u), a compound including the element, or a compound material in which the element is combined. 13. The method for manufacturing a semiconductor device according to claim 10, wherein the second conductive layer and the capacitor wiring are formed of the same material. 14. A first step of forming an insulating film on a substrate having an insulating surface, a second step of forming an amorphous semiconductor film on the insulating film, and crystallizing the amorphous semiconductor film. Forming a crystalline semiconductor film to form an island-shaped semiconductor layer, a fourth step of forming an insulating film so as to be in contact with the semiconductor layer, and a conductive layer on the insulating film. A sixth step of selectively etching the conductive film to form a conductive layer having a first tapered shape; and doping the semiconductor layer with an impurity element of one conductivity type. A seventh step, an eighth step of etching the first tapered conductive layer to form a second tapered conductive layer, and a lower concentration of the semiconductor layer than the seventh step. Ninth which is doped with an impurity element of one conductivity type Process and method for manufacturing a semiconductor device, characterized in that it comprises a tenth step, the forming a capacitor wiring on an insulating film provided in contact with the semiconductor layer of the pixel portion. 15. The capacitance wiring according to claim 14, wherein:
A method for manufacturing a semiconductor device, which is formed using an element selected from aluminum (Al) and titanium (Ti), a compound including the element, or a compound material in which the element is combined. 16. The method according to claim 14, wherein the second tapered conductive layer has an angle of 30 ° to 60 °. 17. The semiconductor device according to claim 10, wherein the semiconductor device is a personal computer, a video camera, a portable information terminal, a digital camera,
A method for manufacturing a semiconductor device, which is a digital video disk player or a projector.