JP2001285268A - Clock generator using srts method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the jitter characteristics of a generated clock. SOLUTION: A digital PLL (DPLL) 51f controls the phase of a receiving user clock CRU1 so that the difference between local timing information (local RTS information) generated on the basis of the first received user clock CRU1 and received timing information (received RTS information) received from a network is zero. Furthermore, an analog PLL (APLL) 53 generates a second receiving user clock CRU2 phase-synchronously with a clock (phase comparison clock) resulting from frequency-dividing the first receiving user clock CRU1. User data are written into a data transfer FIFO buffer 55 by using the first received user clock CRU1 out of the first and second receiving user clocks and the user data are read from the FIFO buffer by using the second receiving user clock CRU2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SRTS (Synchronous
(Residual Time Stamp) method, especially in wideband ISDN (B-ISDN) using ATM.
The transmission user clock timing information (transmission
RTS information), the transmission RTS information is cellized together with user data and transmitted, and the reception side sets the reception user clock to the same timing as the transmission user clock based on the transmission RTS information (referred to as reception RTS information). The present invention relates to a clock generator of an interface device that outputs user data in synchronization with a user clock.

[0002]

2. Description of the Related Art As a means for realizing broadband communication, an asynchronous transfer mode (AsynchronousTransfer Mode: A) is used.
There is a B-ISDN (Broadband-ISDN) exchange technology based on TM). Such B-ISDN has a service for transmitting user data at a constant speed, that is, a CBR service (Constant Bi
t Rate Service). In the CBR service, the timing of the clock on the receiving side (the receiving user clock) must match the timing of the user clock on the transmitting side. When the transmitting user clock is synchronized with the network clock (network clock), the receiving user clock is generated from the network clock on the receiving side, so that the timings of the transmitting and receiving clocks can be matched. .

However, the transmission user clock (64 kb of audio)
ps, DS1 standardized in ITU-DS recommendation G700 series, etc.
(1.544 Mbps of DS3, 44.736 Mbps of DS3, etc.) may not be synchronized with the timing of the network clock on the network side. In such a case, even if the nominal value (Nominal Value) of the frequency of the transmitting user clock is known and the receiving side divides the network clock (e.g., 155.56 MHz) to generate the receiving user clock having the same nominal value, A timing error occurs between the user clock and the transmission user clock, and a faithful CBR service cannot be performed.

[0004] As described above, as a method of synchronizing the reception user clock with the transmission user clock, SRTS (Synchronous
Residual Time Stamp) method has been proposed. This SRTS
In the method, the transmitting side includes timing information of the transmitting user clock in the ATM cell, the receiving side extracts the timing information of the transmitting user clock, and synchronizes the receiving user clock with the transmitting user clock based on the timing information. . For transmission of the transmission user clock timing information, AAL-1 (ATM Adaptation Layer-1) standardized by ITU-DS Recommendation I363 or the like is used as an ATM cell.

FIG. 12 is a diagram for explaining the format of an AAL type 1 (AAL-1) ATM cell. FIG. 13 is a diagram showing a 1-byte SAR-PD.
FIG. 4 is an explanatory diagram of a format of a U header. In AAL-1,
The 48-byte information field includes a 47-byte SAR-PDU payload and a 1-byte SAR-PDU (PDU: Protocol Data U
nit) and a header. 47 bytes long
The SAR-PDU payload is used to transfer user data, and the 1-byte SAR-PDU header has a 4-bit SN.
(Sequence Number) field and 4-bit SNP (Sequence
nce Number Protection) feed. SN
The field consists of two subfields, CSI (Convergence
SublayerIdentifier) and SC (Sequence Count), and the SNP field has two subfields, CRC (Cycl
ic Redundancy Check) and EPB (Even Parity Bit). The SC divides the cell from 1 to 8 (1,2, ..., 8,1,2, ...)
., 8, 1,...), And the order of cells can be monitored by this SC. Error detection and correction of SN are performed by CRC and EPB. The CRC is a polynomial (G
(X) = X ³ + X + 1), and EPB is an even parity bit of the SAR-PDU header. CSI bit is AAL-1 CS
(Convergence Sublayer), which is used for transmission and reproduction of user clock timing information as described below.

In the SRTS method, user clock timing information is composed of 4-bit information (RTS4, RTS3, RTS2, RTS1) called RTS (Residual TimeStamp). This RTS information is transferred by the CSI bit which is a CS function of AAL-1. FIG. 14 is an explanatory diagram of the configuration of the RTS information format. The RTS information format has a multi-frame configuration of eight ATM cells. User data is
Since the data is transferred using the SAR-PDU payload, the number of bits of the user data in the eight ATM cells is 3008 bits (8 cells × 47 bytes × 8 bits). The CSI bit is SC (Sequenc
e Count) 8-bit configuration (CSI ₀ -CS
I ₇ ), and the C value of the ATM cell with SC value = 1, 3, 5, 7
Four bits of RTS information are transmitted by SI bits (CSI ₁ , CSI ₃ , CSI ₅ , CSI ₇ ). That is, RTS4 is an ATM with SC = 1
Depending on the cell, RTS3 is determined by the ATM cell with SC = 3;
Is transferred by an ATM cell with SC = 5, and RTS1 is transferred by an ATM cell with SC = 7.

FIG. 15 is an explanatory diagram of a generation cycle of RTS information. In the CBR service, the transmission user data D _TU is data at a constant speed, and a clock synchronized with the data is a transmission user clock C _TU in the figure. In the ATM cell, the information of the transmission user data _DTU is
The transmission is performed using the AR-PDU payload, and the RTS information that is the timing information of the transmission user clock _CTU is transmitted using the CSI bit.
Therefore, if the frequency of the transmission user clock is f _TU and the time for one bit of user data is T _TU = 1 / f _TU , then RT
Generation period of the S information T _TS = T a _TU × 3008. When a clock for the generation of RTS data transmission RTS sampling timing clock C _TS, RTS information the clock C _TS
Is generated at the rise, the transmission RTS sampling timing clock C _TS is obtained by the data transmission clock C _TU and peripheral 1/3008 bisection.

In SRTS, the network timing
Network clock frequency f synchronized with_N(Example: 15
(5.56MHz)_NX(Around
Wave number f_NX= F_N/ 2^N, 1/2^N= Frequency division ratio).
Dividing ratio 1/2^NIs the network divided clock frequency f_NX
And the nominal value of the user clock frequency (Nominal Value) f_NO
MIs 1 ≦ (f_NX/ F_NOM) <2
Decide. Next, the network divided clock frequency f_NX
Is divided by a 4-bit binary counter, and f_NX/ 2¹, F
_NX/ 2^Two, F_NX/ 2^Three, F_NX/ 2^FourFrequency network
Timing information Q₁, Q_Two, Q_Three, Q_FourGenerate Net
Network timing information Q₁, Q_Two, Q_Three, Q_FourSend sun
Pulling clock C_TSThe value sampled at the rise of
RTS1, RTS2, RTS3, RTS4 respectively, and RTS information
You. RTS information generation and its transmission format
Therefore, the International Recommendations stipulate
You.

FIG. 16 shows the transmission RTS information according to the international recommendation.
In the configuration diagram of the RTS generation and transmission unit when creating and transmitting
is there. The ATM cell disassembly unit 10 is an ATM cell received from the ATM network.
Network clock C included in RATM_N(frequency
f_N: For example, 155.56MHz) to PLL (Phase Locked Loop)
Extract and output. Network clock divider 1
1 is a network synchronized with the line timing of this network
Clock C_NAnd the network frequency divided clock C_{N X}
Is output. In this case, the network clock divider 1
1 is the network divided clock f_NXAnd user clock cycle
Nominal wave number f_NOMIs 1 ≦ (f_NX/ F_NOM) <2
1/2 so that^N(N is an integer). example
For example, in DS1 transmission, the nominal value f of the transmission user clock frequency is
_NOMIs 1.544MHz, so the network clock frequency
Number f_NIs 155.56 MHz, N = 6 and the network
The divided clock frequency is f_NX= 155.56MHz / 2⁶= 2.43MHz
Becomes Similarly, in DS3 transmission, N = 1 and f_NX= 15
5.56MHz / 2 = 77.78MHz.

Next, the 4-bit binary counter section 12
Counts the network divided clock C _NX, f _NX / 2 ¹ frequency from each stage of the ^{_{four-stage, f NX / 2 2, f}} NX /
2 ^3, f network timing information to Q _{1 NX} / 2 ^4,
Q ₂ , Q ₃ and Q ₄ are output. On the other hand, the transmission division counter unit 13 _divides the transmission user clock C _TU (frequency f _TU ) synchronized with the transmission user data D _TU by 3008 to generate the transmission RTS sampling clock C _TS (frequency f _TS = f _TU / 3008). Output.

[0011] transmission RTS generator 14 network timing information _{Q 1, Q 2, Q 3} , transmits the Q ₄ RTS sampling clock C sends sampled at the rising edge of _TS RTS information T
Output as RTS1, TRTS2, TRTS3, TRTS4. When the frequency f _TU of data transmission clock C _TU fluctuates, because the rise time of the transmission RTS sampling clock C _TS varies,
The values of the transmission RTS information TRST1 to TRST4 also change. In other words, the transmission RTS information includes the timing information of the transmission user clock _CTU .

The ATM cell assembling unit 15 transmits the transmission user data D
_TUAnd the transmission user clock C synchronized with it_TUAnd send RTS
Using the transmission RTS information input from the generation unit 14, 3008
× T_TUAssemble eight ATM cells TATM for each ATM cell
To the network clock C_N(F _N= 155.56MHz)
And sends it to the ATM network.

FIG. 17 is a block diagram of a receiving unit for generating a receiving user clock (receiving clock) synchronized with the transmitting user clock using the RTS information. In the figure, 20 is reception clock generator 21 generates a local RTS an information generating unit, received RTS information clock C _RCK in synchronization therewith and local RTS information LRTS1~LRTS4 a timing information reception clock C _RU . Local RTS information generator 2
1, network clock divider unit 21 which the network clock C _N by dividing outputs the divided clock C _NX
a, a 4-bit binary counter 21b for counting the frequency-divided clock C _NX , and the reception user clock C _RU being 1/3008
A local RTS timing generator 21 that _{divides the} frequency to generate a timing signal for generating local RTS information and outputs the timing signal as a received RTS information clock C _RCK
c. The contents (4-bit data) of the 4-bit binary counter at the time of generation of the timing signal are stored in the local RTS information LRT.
It has a local RTS generation circuit 21d that outputs as S1 to LRTS4.

Reference numeral 22 denotes a reception RTS information register for storing the RTS information (referred to as reception RTS information) RRTS1 to RRTS4 contained in the ATM cell transmitted from the transmission side in synchronization with the clock C _RCK. Reference numeral 23 denotes the reception RTS information RRTS1 to RRTS1. RRTS4 and local RTS information
Comparator for outputting a difference between LRTS1~LRTS4, 24 is a digital PLL to adjust and output timing (phase) of the data reception clock C _RU so that the difference becomes zero (DPLL), as shown pulse adjustment unit 24a for controlling the phase by increasing or decreasing the number of pulses of the reference clock C _OSC based on the difference, the pulse frequency divider 24b for generating a clock C _a frequency division to the data reception clock C _RU after adjustment It has. 31 is input to the local RTS information generating unit 21 extracts the network clock C _N from the ATM cell received from the ATM network, and outputs the received ATM cell is decomposed in the user data D _RU and RTS information RRTS1~RRTS4 ATM cell disassembly unit.

The local RTS information generating unit 21 generates the reception RTS information clock C _RCK in synchronization therewith and local RTS information LRTS1~LRTS4 a timing information reception clock C _RU by SRTS method. The comparing unit 23 receives the local RTS information LRTS1 to LRTS4 and the received RTS information RR included in the received ATM cell.
And outputs the difference between the TS1~RRTS4, DPLL 24 adjusts the timing of the reception clock C _RU by increasing or decreasing the number of reference clock such difference is zero. As a result,
Timing (frequency, phase) of receive user clock _CRU
With the timing of the transmission user clock _CTU . The ATM cell disassembly unit 31 receives from the ATM network
The network clock C _N is extracted from the ATM cell and output, and the user data D _RU is output in synchronization with the reception user clock C _RU input from the DPLL 24 and received in synchronization with the reception RTS information clock C _RCK. RTS information RRTS1 ~
RRTS4 is output and input to the register 22.

By the way, the method of reproducing the reception user clock by the digital PLL has the following problems. Assuming that the nominal value f _NOM of the user clock frequency is αHz, the output clock of the reference oscillator (reference clock) C _OSC
Frequency f _OSC is _{f OSC = βHz (β = α} × N; N is the division ratio), and the step by step jitter ΔT when correction ΔT
= 1 / β seconds. Further, since the receiving user clock cycle T _RU is T _RU ≒ 1 / α, the ratio of the jitter to the receiving user clock cycle (jitter ratio) UI is UI = ΔT / T _RU ≒ α / β = 1 / N. Therefore, it is necessary to increase N in order to reduce the jitter ratio UI. However, the reference clock C _OSC Reducing the jitter ratio frequency f _OSC is f _OSC = βHz
(Β = α × N) becomes large, and there is a problem that power consumption increases.

The nominal value of the user clock frequency α that can be supported by the SRTS is the network clock frequency f _N.
Therefore, at the network clock frequency f _N = 155.52 MHz of B-ISDN, it is necessary to support up to the nominal value f _NOM of the user clock frequency = 77.76 MHz. For example, when the user clock frequency f _RU = 44.736 MHz as in the DS3 interface, β = 715.776 MHz if N ≧ 16 in order to reduce the jitter ratio to 0.1 or less. Therefore, in the digital PLL system, there is a problem that a very high-speed element is required when the user clock becomes high-speed.

Furthermore, the correction amount for one step at a time correction is [Delta] T = 1 / beta seconds, also the correction cycle of the reception clock is the period of the reception clock and T _RU, T = 3008 × T _RU ≒ 3008 / α. Therefore, the allowable range W of the reproducible deviation of the user clock is W = ΔT / T ≒ (1 / β) × (α / 3008) = 1 / (3008
× N). That is, if N is increased to reduce the jitter ratio, there is a problem that the allowable range of the user clock deviation is reduced.

To solve the above problem, an analog PLL circuit (APLL) 25 is provided as shown in FIG. 18, and the analog PLL circuit is connected to a DPLL via a pulse dividing counter 26.
24 is known.
In the figure, reference numeral 20 denotes a digital reception user clock generator,
31a is a cell buffer. Cell buffer 31a is AT
A network clock provided in the M cell disassembly unit 31
The ATM cell is stored by (ATM clock) and read out in synchronization with the reception user clock _CRU . In the reception user clock generation unit 20, the counter 21 corresponds to the local RTS information generation unit 21 in FIG.
Counted value generation clock (network division clock C _NX), latches the count value every 3008 cycles of the data reception clock C _RU, local RTS information the regimen numerical LRTS1~LRTS4
Output as

The DPLL 24 stores local RTS information LRTS1 to LRTS4.
The counter 26 increases or decreases the number of reference clocks so that the difference between the received RTS information RRTS1 and RRTS4 becomes zero, and the counter 26 divides the frequency of the DPLL output clock to generate a phase comparison clock C _REF of, for example, 8 kHz. The analog PLL circuit (APLL) 25 outputs a reception user clock C _RU synchronized in phase with the phase comparison clock C _REF . That is, the phase difference detection unit 25a outputs the received user clock C _RU which is the output of the phase comparison clock C _REF and the output of the APLL.
Is output, the low-pass filter 25b smoothes the phase difference signal, and outputs a VCO (Voltage Control) signal.
The oscillator 25c outputs a reception user clock _CRU having a frequency corresponding to the phase difference, and the frequency divider 25d divides the frequency of the reception user clock _CRU into an 8 KHz clock and feeds it back to the phase difference detector 25a. As described above, the analog PLL circuit (APLL) 25 receives the reception user clock C _RU.
Is controlled so as to have a phase designated by the DPLL, and the ATM cell disassembly unit 31 outputs user data from the cell buffer 31a in synchronization with the reception user clock _CRU and outputs reception RTS information at a predetermined timing. .

[0021]

[Problems to be Solved by the Invention] The DPLL is connected via a frequency divider.
According to the clock generation device to which the APLL is connected, it is theoretically possible to reduce the jitter and the power consumption, and it is possible to increase the allowable range for the deviation. However, in actuality, the feedback of the analog PLL and the feedback of the DPLL to the RTS interfere with each other, and there is a problem that the jitter characteristic is deteriorated by simply connecting. Further, in the conventional clock generator, the DPLL fixedly increases or decreases the clock by a number proportional to the difference. The relationship between the difference and the number of clocks to increase or decrease may theoretically be linear, but if an analog PLL is present, the linear jitter may not improve the jitter characteristics. In such a case, there is a problem that the conventional clock generator cannot be adjusted to optimize the jitter characteristics.

Further, in the clock generator based on the conventional SRTS method, the phase of the next reception user clock _CRU is controlled using the current reception RTS information. Therefore, the control for one cycle period is delayed. Here, one cycle is a multi-frame cycle of eight cells, which is 3008 cycles of the reception user clock. On the transmission side, on the other hand, the current RTS information is created and transmitted based on the previous transmission user clock frequency.
Therefore, the transmission RTS information is frequency information delayed by one cycle. As described above, in the clock generation apparatus based on the conventional SRTS method, the frequency of the reception user clock is controlled based on the frequency information of the transmission user clock 16 cells before, and accurate synchronization control of the transmission user clock and the reception user clock is performed. There is a problem that can not be.

As described above, a first object of the present invention is to eliminate interference between the feedback of the APLL and the feedback of the DPLL and improve the jitter characteristics. A second object of the present invention is to provide a degree of freedom so that various phase adjustments can be performed, and to optimize the jitter characteristics. A third object of the present invention is to perform accurate synchronization control of a transmission user clock and a reception user clock.

[0024]

According to the first object of the present invention, (1) a first receiving user clock is generated, and local timing information (hereinafter referred to as "local timing information") generated based on the receiving user clock is generated. A digital PLL circuit that controls the phase of the received user clock so that the difference between the local RTS information) and the reception timing information (received RTS information) received from the network becomes zero, (2) a first PLL output from the digital PLL circuit. (3) an analog PLL circuit that receives the phase comparison clock and generates a second reception user clock, (4) a first reception Buffer means for writing user data at the user clock and reading out the user data at the second received user clock; and a clock generator using the SRTS method. It is. By providing the buffer means, it is possible to prevent interference between the feedback of the DPLL to the RTS and the feedback of the analog PLL,
Initial jitter characteristics can be improved.

According to the present invention, the second object is as follows.
Storage means for storing correction data according to the difference between the local RTS information and received RTS information; (2) changing means for changing the correction data stored in the storage means; means for generating a phase control signal based on the correction data Is achieved by a clock generation device having: As described above, since the correction data can be freely changed from the outside, the correction data can be determined so as to optimize the jitter characteristics. The correction data includes a clock phase correction cycle, a phase correction timing, and the number of phase corrections.

According to the present invention, the third object is as follows.
The reference timing is set such that the difference between local timing information (local RTS information) created using a reference clock whose phase is controlled based on the RTS information and reception timing information (received RTS information) received from the network becomes zero. Digital PLL circuit that controls clock timing, (2) Frequency divider circuit that divides reference clock output from digital PLL circuit to generate phase comparison clock, (3) Generates reception user clock synchronized with phase comparison clock Analog PLL
Circuit, (4) buffer for storing cells received from the network in synchronization with the network clock, (5) user data contained in the cells constituting the multiframe one cycle before, contained in the currently received multiframe, and received RTS
This is achieved by a clock generator using the SRTS method, comprising: a data read control unit that reads data from the buffer in synchronization with a reception user clock created using information.
As described above, the user data included in the cell configuring the multiframe one cycle before is read from the buffer in synchronization with the reception user clock included in the current multiframe and created using the reception RTS information. Accurate synchronization control of the transmission user clock and the reception user clock without delay can be performed.

[0027]

(A) First Embodiment FIG. 1 is a block diagram of a clock generator using the SRTS method according to a first embodiment of the present invention. ) FI for data transfer between DPLL circuit and APLL circuit
The difference is that an FO buffer is provided, and (2) a phase control unit is provided to perform phase control so as to optimize jitter characteristics.
The reception user clock generation unit 51 generates the first reception user clock C _RU1 , creates local timing information (local RTS information LRTS1 to LRTS4), and receives the local RTS information LRTS1 to LRTS4 and the reception timing received from the network. Information (received RTS information RRTS1 to RRTS4) and compare the received user clock C so that the difference becomes zero.
_Controls the phase of _RU1 (increase / decrease of clock).

The reference clock counter 52 performs the first reception.
User clock C_RU1Divided by 8KHz phase comparison clock
C_REFOccurs. Analog PLL circuit (APLL) 53 is standard
Phase comparison clock output from clock counter 52
C_REFPLL control to match the phase of the second
User clock C_RU2Occurs. Analog PLL circuit (A
PLL) 53 includes a phase difference detection unit 53a, a low-pass filter 5
3b, voltage controlled oscillator (VCO) 53c, frequency dividing circuit 53d
It is composed of The phase difference detection section 53a is a phase comparison clock.
Cook C_REFUser clock C, which is the output of APLL_RU2
Outputs the phase difference of the divided clock obtained by dividing
The filter 53b smoothes the phase difference signal, and the VCO 53c
Second receiving user clock having a frequency corresponding to the phase difference
C_{RU Two}And the frequency divider 53d outputs the received user clock.
C_RU2Is divided into a clock of 8 KHz, and a phase difference detector 53a
Feedback to

The ATM cell disassembly unit 54 synchronizes the ATM cells with the cell buffer 54 in synchronization with the network clock (ATM clock).
a, and outputs the user data from the cell buffer 54a in synchronization with the first reception user clock C _RU1 output from the reception user clock generation unit 51. At the predetermined timing, the reception RTS information RTS1 to RTS4 is output. Output.
The data transfer FIFO buffer 55 stores the user data read from the cell buffer 54a in synchronization with the first reception user clock C _RU1 , and also stores the second reception user clock C _RU2 output from the analog PLL circuit 53. The oldest ones are read out in synchronization with each other.

In the data reproducing system using the AAL1 format, the cell decomposing unit 54 separates the SAR-PDU header and the payload from the ATM cell. That is, the cell disassembly unit 54
The ATM cell received from the network is stored in the cell buffer 54a in synchronization with the ATM clock, the SAR-PDU header and the payload are separated, and the payload (user data) is synchronized with the first reception user clock _CRU1. Send out. In addition, it analyzes the SAR-PDU header and performs various controls, and extracts received RTS information RTS1 to RTS4. On the other hand, the RTS counter (4-bit binary counter) 51a counts an RTS reference clock (network divided clock) _CNX . Since the RTS information is meaningful with eight ATM cells, the RTS latch circuit 51b latches the received RTS information RRTS1 to RRTS4 at the timing when the eight ATM cells are collected and latches the contents of the RTS counter 51a. To generate a latch signal. The counter latch circuit 51c operates when a latch signal is generated.
The contents (4-bit data) of the RTS counter 51a are latched as local RTS information LRTS1 to LRTS4, and the comparison unit 51d
To enter.

The comparing section 51d compares the latched count value (local RTS information LRTS1 to LRTS4) with the received R from the ATM cell.
The TS values RRTS1 to RRTS4 are compared, the phase control unit 51e obtains correction data based on the comparison result, generates a phase control signal based on the correction data, and the DPLL 51e uses the phase control signal to generate a first reception user clock. It operates by controlling the phase of C _RU1 to match the phase of the transmission user clock. As will be described later, the correction data uses a set value written in advance from the outside.

A data read control unit (not shown) reads user data from the cell buffer 54a in synchronization with the first reception user clock _CRU1 , and stores the user data in the data transfer FIFO buffer 55. Also, a reference clock counter 5
2 generates an 8 KHz phase comparison clock C _REF by dividing the frequency of the first reception user clock C _RU1 ,
Generates a second reception user clock C _RU2 by analog PLL control. The data transfer FIFO buffer 55 synchronizes with the second reception user clock C _RU2 from the oldest one to f.
Send user data in irst in / first out format.
As described above, according to the first embodiment, by providing the data transfer FIFO buffer, interference between the feedback of the analog PLL and the feedback of the DPLL to the RTS can be eliminated, and the jitter characteristics can be improved.

(B) Second Embodiment FIG. 2 is a block diagram of a clock generator using an SRTS method according to a second embodiment of the present invention. The same reference numerals as in the first embodiment of FIG. 1 denote the same parts. It is attached. The difference is that (1) the data transfer FIFO buffer 55 of the first embodiment is deleted, and (2) the RTS latch timing control unit 5 for generating the RTS latch timing signal LTS in the reception user clock generation unit 51.
(3) RTS latch timing control unit 51
g is a point that generates the RTS latch timing signal LTS clock signals output from the DPLL section 51f divides every 3008 cycles of the data reception clock C _RU, (3) the received RTS information extracted from the ATM cells RRTS1~RRTS4 (4) The 4-bit received RTS information RRTS1 to RRTS4 stored in the RTS FIFO buffer 51h are latched in the received RTS latch unit 51b by the RTS latch timing signal LTS. (5) analog PLL, wherein the contents (4-bit data) of the RTS counter 51a are latched in the counter latch unit 51c as local RTS information LRTS1 to LRTS4.
User data is read from the cell buffer 54a and output in synchronization with the reception user clock _CRU output from the circuit 53.

According to the second embodiment, since the DPLL only feeds back the RTS latch timing, there is no interference between the DPLL and the APLL, and the data transfer FIFO buffer 55 of the first embodiment can be omitted. In addition, user data with good jitter characteristics can be read from the cell buffer 54a and output.

(C) Third Embodiment FIG. 3 is a block diagram of a clock generator using the SRTS method according to a third embodiment of the present invention. It is attached. The differences are (1) in the cell disassembly unit 54, a data write control unit 54b that writes cells to the cell buffer 54a in synchronization with the ATM clock, and user data from the cell buffer 54a in synchronization with the reception user clock _CRU. (2) The cell buffer 54a has at least the latest 16
(3) The data read control unit 54c determines whether the user data included in the eight cells received in the previous multiframe is included in the currently received multiframe and the received RTS information The cell buffer 54 is synchronized with the reception user clock _CRU created by using
a from the point a.

In the second embodiment shown in FIG. 2, the phase of the next reception user clock _CRU is controlled using the current reception RTS information. Therefore, one-cycle control is delayed. Where 1
The cycle is a multi-frame cycle of 8 cells, and is 3008 cycles of the reception user clock. On the sending side,
The current transmission RTS information is created and transmitted based on the transmission user clock frequency one cycle before. Therefore, send R
The TS information is frequency information delayed by one cycle. According to the third embodiment, saves the user data of the latest 16 cells in the cell buffer 54a, the data read control unit 54c sequentially from the user data of the old cell before 16 cell in synchronism with the reception clock C _RU read Output. Therefore, the phase / frequency of the reception user clock is controlled based on the frequency information of the transmission user clock 16 cells before, and the user data 16 cells before can be read in synchronization with the reception user clock, and there is no delay. Accurate synchronous control of the transmission user clock and the reception user clock can be performed.

(D) Phase Control Unit FIG. 4 is a block diagram of the phase control unit 51e in the first to third embodiments. Since the RTS information is 4 bits, the comparator 5
Difference output from 1d (= Received RTS information-Local RTS information)
Takes 16 values, for example, +7 to -8. Therefore, the phase control unit 51e stores the correction data (correction data + 7 to correction data-8) corresponding to each difference in the register 6
11 _{1 to} 61 ₁₆ , AND gates 62 _{1 to} 62 ₁₆ for outputting correction data according to the difference output from the comparator, OR gate 63 for outputting correction data to be output from the AND gate according to the difference, correction data And a change unit 65 that changes the correction data by performing a phase correction control based on the DPLL control trigger and outputting a DPLL control trigger (phase control signal) for advance / delay to the DPLL unit 51f. The user can freely change the value of the correction data set in the register by the changing unit 65 so that the jitter characteristic is optimized. The DPLL unit 51f adds a pulse when advancing is instructed by the DPLL control trigger to advance the phase of the reference clock, and when a lag is instructed, drops the pulse to delay the phase of the reference clock.

(A) First Example of Correction Data FIG. 5 shows a first example of correction data of the present invention, in which a correction cycle is set as correction data. Figure, the correction position determined by the corresponding and corrected period of the difference D in one cycle (= 3008 clock cycles) (= + 7-8) and the correction period (= T ₇ through T _-8) are shown. The correction cycle corresponding to the difference D can be changed, and can be freely changed so as to improve the jitter characteristics. If it is not necessary to perform correction when the difference D = 0, the correction period T ₀ is set to a value larger than one cycle period. Also, the difference D (= received RTS information-local RTS
If (information) is plus, the delay is controlled at each correction point because the reception user clock is ahead of the transmission user clock, and if minus, the correction is because the reception user clock is behind the transmission user clock. Advance control with points.

(B) Second Example of Correction Data FIG. 6 shows a second example of correction data of the present invention, in which the number of corrections is set as correction data. The figure shows the correspondence between the difference D (= + 7 to -8) and the number of corrections in one cycle (= 3008 clock cycle). The relationship between the number of corrections and the correction point in one cycle is set in advance, and the correction positions of the number of corrections 10 and the number of corrections 3 are shown. Difference D
Can be changed, and can be freely changed so as to improve the jitter characteristic. Also, the difference D
If (= Received RTS information-Local RTS information) is positive, the receive user clock is delayed from the transmit user clock because the phase is ahead of the transmit user clock, and if negative, the receive user clock is less than the transmit user clock. Since the phase is late, advance control is performed at the correction point.

(C) Third Example of Correction Data FIG. 7 shows a third example of correction data of the present invention, in which a correction timing (correction point) is set as correction data. The figure shows the correspondence between the difference D (= + 7 to -8) in one cycle (= 3008 clock cycle) and the correction timing. The correction timing corresponding to the difference D can be changed, and can be freely changed so as to improve the jitter characteristics. If the difference D (= received RTS information-local RTS information) is plus, the receiving user clock is delayed in correction timing because the phase is ahead of the sending user clock. Since the phase is behind the transmission user clock, advance control is performed at the correction timing.

(D) Configuration of Correction Unit FIG. 8 is an explanatory diagram of DPLL control trigger generation control of the correction unit 64 (see FIG. 4) in the phase control unit 51e, where (a) is an addition type and (b) is a subtraction type. (C) is an example of the principle configuration of the leaky packet type. In the addition type shown in FIG. 8A, when the correction period p is input as the correction data, the up counter 64
a ₁ counts up the subsequent reception clock C _RU. When comparing section 64a ₂ is the counted value is checked whether becomes equal to the correction period p, is equal, DPLL control trigger DC
To reset the count value of the counter 64a ₁ as well as generating T. In subtractive in FIG. 8 (b), when the correction period p is inputted as the correction data, the correction period p is preset to the down counter 64b _1. Thereafter, the down counter 64b ₁ counts down the data reception clock C _RU. Comparing unit 64b ₂ checks whether becomes equal to the count value is 0, when it becomes equal to 0, it resets the counter 64b ₁ along with generating a DPLL control trigger DCT.

The leaky packet type shown in FIG. 8C is an effective configuration when it is set with a correction period (for example, 600.5) including a value after the decimal point. Correction cycle p as correction data
When (including decimal values) is inputted, thereafter, the up-counter 64c ₁ counts up a data reception clock C _RU. The adder 64c ₂ adds the output count value and the latch circuit 64c ₃ of the counter (initial value is zero). Comparing unit 64c ₄ is the addition result B correction period A (= p) or becomes more than (A ≦ B) checks, when it is above, resets the counter with generates DPLL control trigger DCT. Further, the subtracter 64c ₅ calculates a B-A, latches the calculated result to the latch 64c _3. Thereafter, the above operation is repeated by inputting the next correction cycle p.

(E) Correction Process (e-1) Addition Type FIG. 9 is a flowchart of an addition type phase lead / lag control process.
When a difference D (= received RTS information−local RTS information) is input from the comparator 51d (FIG. 4) (step 101), a set value (correction data) corresponding to the difference is obtained from a table (step 102), and i = 0, n = 0 (step 103). Next, every time the reception user clock is generated, i and n are incremented (step 104), and it is checked whether n> 3008 is satisfied (step 105). If n ≦ 3008, it is checked whether i = set value (step 10).
6). If i is not the set value, the processing after step 104 is repeated. If i is a set value, the sign of the difference D is determined (step 107). If the sign of the difference D is plus, a DPLL control trigger DCT for instructing lag phase control is output to perform lag phase control (step 108). If the sign of the difference D is minus, the leading phase control is instructed.
The DPLL control trigger DCT is output to perform advance phase control (step 109). If the difference D = 0, the advance /
Maintain the current state without delay phase control (step 11
0). After executing the processing of steps 108 to 110, i = 0 (step 111), and thereafter, the processing of step 104 and thereafter is repeated until n> 3008.

(E-2) Subtraction type FIG. 10 is a flowchart of the phase advance / delay control process of the subtraction type. From the comparator 51d (FIG. 4), the difference D (= received RTS information−
When the local RTS information is input (step 201), a set value (correction data) corresponding to the difference is obtained from a table (step 202), and i = set value and n = 0 (step 203). Next, every time the reception user clock is generated, i is decremented and n is incremented (step 204), and it is checked whether n> 3008 (step 205). If n ≦ 3008, it is checked whether i = 0 (step 206). If i is not 0, the processing after step 204 is repeated. If i is 0, the sign of the difference D is determined (step 207). If the sign of the difference D is positive, a DPLL control trigger DCT for instructing lag phase control is output to perform lag phase control (step 208). If the sign of the difference D is minus, a DPLL control trigger DCT for instructing advance phase control is output to perform advance phase control (step 209). If the difference D = 0, the current state is maintained without performing the leading / lagging phase control (step 210). After executing the processing of steps 208 to 210, i = set value (step 211), and thereafter, n> 30
The process from step 204 is repeated until 08 is reached.

(E-3) Leaky Packet Type FIG. 11 is a flow chart of a leaky packet type phase lead / lag control process. When the difference D (= received RTS information−local RTS information) is input from the comparator 51d (FIG. 4) (Step 3)
01), a set value (correction data) corresponding to the difference is obtained from a table (step 302), and i = 0, n = 0 (step 303). Next, i and n are incremented each time the receiving user clock is generated (step 30).
4) Check if n> 3008 (step 30)
5). If n ≦ 3008, it is checked whether i ≧ set value (step 306). If i <set value, the processing after step 304 is repeated. If i ≧ set value,
The sign of the difference D is determined (step 307). If the sign of the difference D is positive, a DPLL control trigger DCT for instructing delay phase control is output to perform delay phase control (step 308). If the sign of the difference D is minus, the DPLL control trigger DCT for instructing the advance phase control is output to perform the advance phase control (step 309). If the difference D = 0, the current state is maintained without performing the leading / lagging phase control (step 310). After executing the processing of steps 308 to 310, i = (i−set value) (step 311), and thereafter, the processing of step 304 and thereafter is repeated until n> 3008. As described above, the present invention has been described with reference to the embodiments. However, the present invention can be variously modified in accordance with the gist of the present invention described in the claims, and the present invention does not exclude these.

[0046]

As described above, according to the present invention, the user data read from the cell buffer is stored in the buffer means in synchronization with the first reception user clock generated in the DPLL, and the stored data is stored in the buffer in the order from the oldest to the oldest. Since the reading is performed in synchronization with the second reception user clock generated by the PLL, the feedback of the DPLL and the analog PLL
Can be prevented from interfering with each other, and the jitter characteristic can be improved.

Further, according to the present invention, correction data (phase correction cycle of clock, timing of phase correction, number of times of phase correction) corresponding to the difference between the local RTS information and the received RTS information is stored, and the correction amount is stored in an external device. Since the change can be made more freely, a clock can be generated by determining the correction amount so that the jitter characteristic is optimized. Further, according to the present invention, user data included in a cell constituting a multiframe received one cycle before is buffered in synchronization with a reception user clock generated using the received RTS information included in the currently received multiframe. Since the data is read out from the clock, accurate synchronization control of the transmission user clock and the reception user clock without delay can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a clock generator of a first embodiment.

FIG. 2 is a configuration diagram of a clock generator of a second embodiment.

FIG. 3 is a configuration diagram of a clock generator of a third embodiment.

FIG. 4 is a configuration diagram of a phase control unit.

FIG. 5 is a first explanatory diagram of correction data.

FIG. 6 is a second explanatory diagram of correction data.

FIG. 7 is a third explanatory diagram of correction data.

FIG. 8 is an explanatory diagram of generation of a DPLL control trigger when a correction cycle is passed to a correction unit.

FIG. 9 is a flowchart of an addition-type phase lead / lag control process.

FIG. 10 is a flowchart of a subtraction type phase lead / lag control process.

FIG. 11 is a flowchart of a phase lead / lag control process in the leaky packet method.

FIG. 12 is a structural explanatory view of AAL type 1;

FIG. 13 is a diagram illustrating the structure of a SAR-PDU header.

FIG. 14 is an explanatory diagram of a configuration of an RTS information format.

FIG. 15 is a generation cycle of RTS information.

FIG. 16 is a configuration diagram of a conventional RTS generation and transmission unit.

FIG. 17 is a configuration diagram of a receiving unit that generates a receiving user clock synchronized with a transmitting user clock.

FIG. 18 is a configuration diagram of a conventional clock generator in which a DPLL and an APLL are combined.

[Explanation of symbols]

 51d ··· Comparison unit 51e ··· Phase control unit 51f ··· DPLL 52 ··· Reference clock counter (division circuit) 53 ··· APLL 55 ··· Data transfer FIFO

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04L 12/28 H04L 11/20 D (72) Inventor Makoto Adachi 2-3-3 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa No. 9 Fujitsu Digital Technology Co., Ltd. In-house (72) Inventor Hiroko Yoshino 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture In-house Fujitsu Digital Technology Co., Ltd. (72) Inventor Masaaki Suzuki Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa 2-3-9 Fujitsu Digital Technology Corporation In-house F-term (reference) 5J106 AA04 BB02 CC01 CC21 CC38 CC41 CC52 DD13 DD17 DD19 DD42 DD44 FF06 FF09 GG18 HH02 KK25 5K028 AA03 MM12 MM16 NN22 NN23 NN32 NN03 RR03 SS03 5030 KA22 LA15 5K047 AA06 BB16 BB17 CC02 GG16 GG22 GG44 GG45 HH55 MM24 MM46 M M48 MM55 MM63 9A001 BB04 CC02 KK56

Claims (8)

[Claims] 1. A clock generator using an SRTS method for generating a reception clock synchronized with a transmission clock on a cell transmission side on a cell reception side, wherein the first reception clock is generated and created based on the reception clock. Digital PLL circuit that controls the phase of the received clock so that the difference between the received local timing information (local RTS information) and the received timing information (received RTS information) received from the network becomes zero, output from the digital PLL circuit A frequency divider that generates a phase comparison clock by dividing a first reception clock to be generated, an analog PLL circuit that generates a second reception clock that is phase-synchronized with the phase comparison clock, Written, second
And a buffer means for reading user data with the received clock of (c). 2. A digital PLL circuit comprising: comparing means for comparing local RTS information and received RTS information; and a phase control unit for generating a phase control signal based on a difference between the local RTS information and received RTS information. 2. The clock generator according to claim 1, wherein the phase of the first received clock is controlled based on the signal. 3. The phase control unit includes: a storage unit that stores correction data corresponding to a difference between the local RTS information and the received RTS information; and a unit that generates a phase control signal based on the correction data. 3. The clock generator according to claim 2, wherein 4. A clock generator using an SRTS method that generates a reception clock synchronized with a transmission clock on a cell transmission side on a cell reception side, wherein the clock is generated using a reference clock whose phase is controlled based on RTS information. A digital PLL circuit that controls the phase of the reference clock so that the difference between the local timing information (local RTS information) and the reception timing information (received RTS information) received from the network becomes zero, a reference output from the digital PLL circuit A frequency divider that divides the clock to generate a phase comparison clock, an analog PLL circuit that generates a reception clock synchronized with the phase comparison clock, a buffer that stores cells received from the network in synchronization with the network clock, 1 cycle This time, the user data included in the cells constituting the Were in synchronism with the reception clock created using the received RTS information contained in the multi-frame, the data read control unit for reading from the buffer, clock generator using the SRTS method characterized by comprising a. 5. A digital PLL circuit comprising: comparing means for comparing local RTS information and received RTS information; and a phase control unit for generating a phase control signal based on a difference between the local RTS information and received RTS information. The clock generator according to claim 4, wherein the phase of the reference clock is controlled based on the signal. 6. A phase control unit comprising: a storage unit that stores correction data corresponding to a difference between local RTS information and reception RTS information; and a unit that generates a phase control signal based on the correction data. The clock generator according to claim 5, wherein 7. A clock generation device using an SRTS method that generates a reception clock synchronized with a transmission clock on a cell transmission side on a cell reception side, wherein the reception clock is generated using a reference clock whose phase is controlled based on RTS information. Comparison means for comparing local timing information (local RTS information) with reception timing information (received RTS information) received from the network, a phase control unit for generating a phase control signal based on a difference between the local RTS information and the received RTS information, A digital PLL circuit that controls the phase of the reference clock based on a phase control signal, a frequency divider that divides a reference clock output from the digital PLL circuit to generate a phase comparison clock, a reception clock that is phase-synchronized with the phase comparison clock An analog PLL circuit that generates the correction signal according to the difference between the local RTS information and the received RTS information. A clock generator comprising: a storage unit for storing data; and a unit for generating a phase control signal based on correction data. 8. The clock control device according to claim 3, wherein the correction data includes at least one of a phase correction synchronization, a phase correction timing, and a phase control count.