JP2001273274A - Semiconductor integrated circuit and test mode setting circuit therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a single chip microcomputer or the like, which omits a dedicated terminal for test mode setting for switching and designating a test mode/other operation mode. SOLUTION: This circuit is provided with an internal circuit 80 having a prescribed function, a power-on reset circuit 10 for generating a reset signal when turning on a power source, and a mode deciding circuit 20 for performing logic processing of the output potential of the power-on reset circuit and the potential of another signal line 13 and selectively designating one of at least two modes of the test mode and the other operation mode to the internal circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (LSI) such as a microcomputer, and more particularly to a mode switching circuit for switching and setting an operation mode of a semiconductor integrated circuit. The microcomputer system is used to set switching between a shipping test mode and a user mode (normal operation mode).

[0002]

2. Description of the Related Art Generally, a single-chip microcomputer operates in accordance with a user mode which normally operates in accordance with a user program command stored in a built-in ROM, and operates in accordance with a command externally supplied by an LSI supplier for a shipping test. Need a test mode.

In order to control these two modes, a conventional single-chip microcomputer is provided with one test mode setting terminal, and the test mode setting terminal is set to different potential states depending on the test mode / user mode. You have set.

FIG. 9 schematically shows the block configuration of a conventional single-chip microcomputer and the relationship between external terminals (pins) and control signal lines.

The external terminals include a power supply terminal 91 supplied with a power supply potential VDD, and a ground terminal 9 supplied with a ground potential VSS.
2. A clock input terminal 93, an input / output signal terminal 94, a forced reset terminal 95, a test mode setting terminal 96, and the like are provided.

The internal circuit 80 includes a program memory consisting of a ROM storing a user program, a CPU, an RA
M, peripheral circuits, an internal bus, an input / output (I / O) interface, and a test mode control circuit for detecting the potential of the test mode setting terminal 96 to set a test mode / normal operation mode. I have. The test mode control circuit receives the test mode setting signal TEST and the reset signal / RESET from the test mode setting terminal 96 and the forced reset terminal 95, and performs mode control.

A clock signal is supplied from an external oscillation circuit 98 to a clock input terminal 93 as an external control signal required for the normal operation of the microcomputer, and an external reset circuit 99
, The reset signal / RESET is supplied to the forced reset terminal 95. The reset circuit 99 generates a power-on reset signal when power is turned on, and generates a forced reset signal when a forced reset is required, for example, by operating a reset switch (not shown). In the test mode of the microcomputer, a test input signal and a test output signal are exchanged between the input / output signal terminal 94 and the LSI tester.

Next, the mode setting operation when the test mode setting terminal 96 of the microcomputer of FIG. 9 is active High ("H") will be described with reference to timing waveform diagrams shown in FIGS. 10 (a) and 10 (b). I will explain it.

As shown in FIG. 10A, when the power is turned on while the test mode setting terminal 96 is fixed at VSS (= "L"), the power-on reset signal / RESET is set to "L". Normal operation starts after the internal circuit 80 is reset during the period.

On the other hand, as shown in FIG. 10B, the potential of the signal TEST of the test mode setting terminal 96 is VDD
When the power is turned on in the state set to (= “H”), the internal circuit 80 is turned on during the low (“L”) period of the power-on reset signal / RESET.
The test operation starts after is reset.

That is, when the test mode setting terminal 96 is
In the case of gh active, VDD is applied when the test mode is set in the shipment test of the LSI supplier,
VS when using in user mode (normal operation mode)
Fixed to S.

Conversely, when the test mode setting terminal 96 is active low, VSS is applied when setting the test mode, and is fixed to VDD when used in the user mode (normal operation mode). Is done.

As can be seen from the above operation, the conventional test mode setting terminal 96 is indispensable for the LSI supplier to set the test mode at the time of shipping test, but is unnecessary for the user. Met.
That is, when the user uses the single-chip microcomputer in the user mode, the test mode setting terminal 96 is set to a specific state (GND fixed state,
(VDD fixed state or open state) is set on the user system.

[0014]

On the other hand, in an LSI having a small number of external terminals, in particular, a single-chip microcomputer having a number of external terminals of, for example, about 30 pins or less for a 4-bit or 8-bit, a dedicated memory is used for designating a test mode. It is required to omit even one test mode setting terminal 96 and increase the number of other active external terminals.

The present invention has been made in view of the above circumstances, and can realize a single-chip microcomputer or the like in which a dedicated test mode setting terminal for designating switching between a test mode and another operation mode is omitted. And a test mode setting circuit therefor.

[0016]

A first semiconductor integrated circuit according to the present invention comprises an internal circuit having a predetermined function, a power-on reset circuit for generating a reset signal when power is turned on,
Mode designation for performing logical processing of the output potential of the power-on reset circuit and the potential of another signal line, and selectively designating at least two modes of a test mode / other operation modes for the internal circuit. A mode determining circuit for generating a signal.

A second semiconductor integrated circuit according to the present invention includes an internal circuit having a predetermined function, a forced reset terminal for inputting a forced reset signal, a forced reset signal line connected to the forced reset terminal, and Power-on having a pull-up resistance element connected between a reset signal wiring and a power supply node, a capacitor connected between the forced reset signal wiring and a ground node, and a diode connected in parallel to the pull-up resistance element A reset circuit and a mode designation signal for selectively designating a test mode for performing a test operation after reset and a user mode for performing a normal operation after reset based on the potential of the forced reset signal line. And a mode determination circuit that performs the operation.

A test mode setting circuit for a semiconductor integrated circuit according to the present invention includes: an internal circuit having a predetermined function; a forced reset terminal for inputting a forced reset signal; a forced reset signal line connected to the forced reset terminal; A pull-up resistor connected between the forced reset signal line and a power supply node, a diode connected in parallel to the pull-up resistor, and the internal circuit based on the potential of the forced reset signal line. A semiconductor integrated circuit comprising: a mode determination circuit for generating a mode designation signal for selectively designating a test mode for performing a test operation after reset / a user mode for performing normal operation after reset;
A capacitor externally connected to the semiconductor integrated circuit between the forced reset terminal and a ground potential and forming a power-on reset circuit together with the pull-up resistor element and the diode; and a forced reset terminal external to the semiconductor integrated circuit. And a forced reset switch connected between the switch and the ground potential.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 schematically shows a block configuration of a single-chip microcomputer according to a first embodiment of the present invention, and the relationship between external terminals (pins) and control signal lines.

This microcomputer differs from the conventional microcomputer described above with reference to FIG. 9 mainly in that (1) a test mode setting terminal 96 is omitted, and (2) a reset circuit 10 is built in. That is, the pull-up resistance element 11 and the mode determination circuit 20 are added, and the other components are the same, and thus are denoted by the same reference numerals.

That is, in FIG. 1, reference numeral 91 denotes a power supply terminal to which a power supply potential VDD is supplied, 92 denotes a ground terminal to which a ground potential VSS is supplied, 93 denotes a clock input terminal, 94 denotes an input / output signal terminal,
95 is a forced reset terminal.

As the reset circuit 10, for example, a power-on reset circuit that generates a reset signal when power is turned on is provided.

The pull-up resistance element 11 is connected between the power supply line 12 connected to the power supply terminal 91 and the forced reset signal line 13 connected to the forced reset terminal 95.

The mode determination circuit 20 performs logical processing of the potential of the output signal RESOUT of the reset circuit 10 and the potential of the forced reset signal line 13 and selectively switches the internal circuit 80 between a test mode, a user mode, and a forced reset mode. Two types of signals for generating a mode designation signal for designation (conventional test mode setting signal TEST and reset signal / RESET
), And is logically configured to perform the operation described below.

The internal circuit 80 is, like a conventional microcomputer,
It includes a program memory including a ROM storing a user program, a CPU, a RAM, peripheral circuits, an internal bus, an input / output (I / O) interface, a test mode control circuit, and the like. The test mode control circuit receives the test mode setting signal TEST and the reset signal / RESET from the mode determination circuit 20 and performs mode control.

Next, the input (the output potential of the power-on reset circuit 10 and the potential of the forced reset signal line 13) which is the determination condition of the mode determination circuit 20 in FIG. 1 and the output (the test mode signal TEST) which is the mode determination result And reset signal
/ RESET) will be described with reference to timing charts shown in FIGS.

FIG. 2 shows the operation of the microcomputer shown in FIG. 1 when the user mode (mode in which normal operation is performed after reset) is set.

With the forced reset terminal 95 open, VDD
When the power is turned on, the VDD potential rises, and the potential of the forced reset signal wiring 13 passes through the pull-up resistor element 11.
On the other hand, the output signal RESOUT of the power-on reset circuit 10 is "L" for a certain time after the power-on, and becomes "H" after the certain time.

The mode determination circuit 20 outputs "L" as a reset signal / RESET to reset the internal circuit 80 for a certain period of time when the output signal RESOUT of the power-on reset circuit 10 is "L". , Test mode setting signal TE
Outputs "L" as ST.

When the output signal RESOUT of the power-on reset circuit 10 becomes "H" after the predetermined time, if it is determined that the potential of the forced reset signal line 13 is "H", the test mode setting signal TEST "H" as the reset signal / RESET. Thus, the internal circuit 80 starts the normal operation.

FIG. 3 shows the operation of the microcomputer of FIG. 1 when the test mode (test operation after reset) is set.

When the VDD power is turned on with the forced reset terminal 95 set to the ground potential "L", the VDD potential rises, but the potential of the forced reset signal line 13 remains "L". On the other hand, the output signal RESOUT of the power-on reset circuit 10
Is "L" for a certain time after the power is turned on, and becomes "H" after the certain time.

The mode determination circuit 20 outputs "L" as the reset signal / RESET to reset the internal circuit 80 for a certain time during which the output signal RESOUT of the power-on reset circuit 10 is "L". , Test mode setting signal TE
Outputs "L" as ST.

Then, when the output signal RESOUT of the power-on reset circuit 10 becomes "H" after the predetermined time, if it is determined that the potential of the forced reset signal line 13 is "L", the test mode setting signal TEST And outputs "H" as the reset signal / RESET. Thus, the internal circuit 80 starts the test operation.

FIG. 4 shows the operation when the microcomputer of FIG. 1 is set in the forced reset mode (mode in which the normal operation is performed again after the forced reset during the user mode), that is, the user mode setting operation shown in FIG. 2 is performed. Then, the operation when the user mode setting is performed again after the forced reset setting operation is performed for some reason.

When the forced reset terminal 95 is temporarily set to the ground potential "L" while operating in the user mode (the output signal RESOUT of the power-on reset circuit 10 is "H"), the mode is determined. The circuit 20 continues to output "L" as the test mode setting signal TEST, but the reset signal / R
After temporarily inverting ESET to "L", it returns to "H" again.

Thus, after the internal circuit 80 is temporarily reset, the normal operation starts again (return to the user mode).

That is, according to the microcomputer of the above embodiment,
Logic processing of the output potential of the power-on reset circuit 10 and another signal potential is performed, and the test mode /
A mode determination circuit for generating a mode designation signal for selectively designating at least two of the other operation modes
Has 20.

In this case, the test mode / user mode and the forced reset mode can be selectively designated by using the potential of the forced reset signal line 13 connected to the forced reset terminal 95 as another signal potential. Becomes possible.

Therefore, compared to the conventional case where one dedicated test mode setting terminal (96 in FIG. 9) unnecessary for the user is required to set the test mode, the test mode setting Terminals can be omitted, and other active external terminals (functional terminals) meaningful to the user can be increased accordingly.

Since the power-on reset circuit 10 is built in, the internal circuit 80 can be initialized by using a reset signal RESOUT automatically generated when the power is turned on. Application to simple systems.

FIG. 5 shows an example of a logic circuit of the mode determination circuit 20 in FIG.

In FIG. 5, the RS flip-flop circuit 50
In this configuration, an output signal RESOUT of a reset circuit is input as a set input, a signal of a forced reset signal line is input as a reset input, and the signal responds to the "L" level. The two-input first AND circuit 51 includes the RS flip-flop circuit
The logical AND of the "H" level of the output signal of the reset circuit 50 and the output signal RESOUT of the reset circuit is used to output the test signal TEST. The two-input second AND circuit 52 calculates the logical AND of the reset circuit output signal RESOUT and the signal of the forced reset signal wiring at the "H" level, and outputs a reset signal / RESET.

In the first embodiment, the power-on reset circuit 10 is provided separately from the forced reset terminal 95.
It is also possible to provide it in a state where it is connected to 95, two examples of which will be described in Embodiments 2 and 3 below.

<Second Embodiment> FIG. 6 shows a part of a single-chip microcomputer according to a second embodiment.

The microcomputer shown in FIG. 6 is different from the microcomputer shown in FIG. 1 in the power-on reset circuit 10a and the mode determination circuit 20a, and the other parts are the same.

In this microcomputer, a forced reset terminal
Power-on reset circuit connected to 95
All the components of 10a are formed inside the microcomputer. That is, the power-on reset circuit 10a is connected between the pull-up resistor element 11 connected between the power supply wiring 12 and the forced reset signal wiring 13, and connected between the forced reset signal wiring 13 and the ground wiring 14. And a diode 16 connected in parallel to the pull-up resistor element 11.

The mode determination circuit 20a outputs the output potential of the power-on reset circuit 10a (forcibly reset signal wiring).
The test mode setting signal TEST and the reset signal / RESET for selectively designating the test mode / reset operation for the microcomputer internal circuit based on the 13 potentials) are generated. It is logically configured to do so.

The operation of the microcomputer shown in FIG. 6 when setting the user mode (mode in which normal operation is performed after reset) is performed according to FIG.

That is, when the VDD power supply is turned on with the forced reset terminal 95 opened, the VDD potential rises. On the other hand, the output signal of the power-on reset circuit 10a is "L" for a certain time after the power is turned on, and "L" after the certain time.
H ".

The mode determination circuit 20a outputs "L" as the reset signal / RESET to reset the internal circuit of the microcomputer for a predetermined time during which the output signal of the power-on reset circuit 10 is "L". Outputs "L" as test mode setting signal TEST.

When it is determined that the output signal of the power-on reset circuit 10a has become "H" after the predetermined time, "L" is continuously output as the test mode setting signal TEST, and "H" is output as the reset signal / RESET. "Is output. Thus, the internal circuit starts normal operation.

On the other hand, the operation of the microcomputer shown in FIG. 6 when the test mode (test operation after reset) is set is performed according to FIG.

That is, the forced reset terminal 95 is set to the ground potential "L".
When the VDD power supply is turned on with the setting of, the VDD potential rises, but the potential of the forced reset signal wiring 13 remains "L", and the output signal of the power-on reset circuit 10a becomes "L".
L ".

When the output signal of the power-on reset circuit 10a is "L", the mode determination circuit 20a outputs "L" as the reset signal / RESET to reset the microcomputer internal circuit, "L" is output as the setting signal TEST.

When the forced reset terminal 95 is opened after a predetermined period of time for setting the test mode and the output signal of the power-on reset circuit 10a becomes "H", the potential of the forced reset signal line 13 becomes "H". If it is determined to be "H", "H" is output as the test mode setting signal TEST and "H" is output as the reset signal / RESET. Thus, the internal circuit starts a test operation.

<Third Embodiment> FIG. 7 shows a test mode setting circuit of a single chip microcomputer according to a third embodiment.

The microcomputer shown in FIG. 7 is different from the microcomputer shown in FIG. 6 in the power-on reset circuit 10b, and the other components are the same, and thus are denoted by the same reference numerals.

In this test mode setting circuit, some of the components of the power-on reset circuit 10b connected to the forced reset terminal 95 are provided inside the microcomputer, and the rest of the components are connected to the microcomputer. Is attached. That is, the power-on reset circuit 10b includes a pull-up resistance element 11 connected between the power supply wiring 12 and the forced reset signal wiring 13, and a pull-up resistance element
It has a diode 16 connected in parallel to 11 and a capacitor 15 connected between the forced reset terminal 95 and the ground potential VSS outside the microcomputer.

The operation of the microcomputer in FIG. 7 when setting the user mode (mode in which normal operation is performed after reset) and the operation in setting the test mode (mode in which test operation is performed after reset) are performed in the same manner as the microcomputer in FIG. .

FIG. 8 shows an example of a logic circuit of the mode determination circuit 20a in FIGS. 6 and 7.

This mode judging circuit is different from the mode judging circuit shown in FIG.
The difference is that an up-counter 53 for counting up upon receiving Cp and for generating a signal corresponding to the output signal RESOUT of the power-on reset circuit 10 by itself is added. The same reference numerals are used.

The up-counter 53 is cleared instantaneously when the power is turned on, and then turned on by the power-on reset circuit shown in FIG.
10a or C of the power-on reset circuit 10b in FIG.
It outputs a signal in the "L" state for a fixed time longer than the R time constant.

When the output of the up counter 53 becomes "H", the potential of the forced reset signal wiring (the potential of the output signal of the power-on reset circuit 10a in FIG. 6 or the power-on reset circuit 10b in FIG. 7). Is "H", "L" is continuously output as the test mode setting signal TEST, and "H" is output as the reset signal / RESET. Thus, the internal circuit starts normal operation.

On the other hand, when the output of the up counter 53 becomes "H", the potential of the forced reset signal line becomes "H".
If it is kept in L "state,
After the forced reset terminal is released and the potential of the forced reset signal wiring becomes "H", the test mode setting signal TEST is set to "H". And outputs "H" as the reset signal / RESET, which starts the internal circuit test operation.

Note that the microcomputer of each of the above-described embodiments operates for a certain period of time (for example, several tens to several hundreds
s) Since a judgment time (for example, several hundred ms) for judging the test mode is required later, it is necessary that the microcomputer activation time is allowed to be equal to or more than the above-mentioned fixed time + judgment time (about 1 second). Condition.

Therefore, for example, a microcomputer for a telephone that requires activation (start of execution) within a very short time immediately after turning on the power, or a gas stove that requires an urgent recovery of operation at the time of a forced reset. The application of the present invention to a microcomputer or the like may be hindered in some cases, but the present invention can be applied to other general microcomputers.

The present invention is not limited to the single-chip microcomputer of each of the above embodiments, but may be applied to an existing LSI having a dedicated test mode setting terminal and a reset terminal to omit the test mode setting terminal. it can.

[0070]

As described above, according to the semiconductor integrated circuit and the test mode setting circuit of the present invention, a single chip omitting a dedicated test mode setting terminal for designating switching between a test mode and another operation mode is omitted. A microcomputer or the like can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a block configuration of a single-chip microcomputer according to a first embodiment of the present invention and a relationship between external terminals and control signal lines.

FIG. 2 is a timing chart showing an operation of the microcomputer of FIG. 1 when a user mode (a mode in which a normal operation is performed after reset) is set.

FIG. 3 is a timing chart showing an operation of the microcomputer shown in FIG. 1 when a test mode (a mode in which a test operation is performed after a reset) is set.

FIG. 4 is a timing chart showing the operation of the microcomputer of FIG. 1 when the forced reset mode (mode in which normal operation is performed again after forced reset during the user mode) is set.

FIG. 5 is a logic circuit diagram showing an example of a mode determination circuit in FIG. 1;

FIG. 6 is a circuit diagram showing a part of a single-chip microcomputer according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a test mode setting circuit of a single-chip microcomputer according to Embodiment 3 of the present invention.

FIG. 8 is a logic circuit diagram showing an example of the mode determination circuit in FIGS. 6 and 7;

FIG. 9 is a diagram schematically showing a block configuration of a conventional single-chip microcomputer and a relationship between external terminals and control signal lines.

FIG. 10 is a diagram illustrating a configuration of a test mode setting terminal of the microcomputer shown in FIG. 9;
8 is a timing chart showing a mode setting operation in the case of High ("H") active.

[Explanation of symbols]

 10: Power-on reset circuit, 11: Pull-up resistor element, 12: Power supply wiring, 13: Forced reset signal wiring, 20: Mode determination circuit, 80: Internal circuit, 91: Power supply terminal, 92: Ground terminal, 93: Clock Input terminal, 94: I / O signal terminal, 95: Force reset terminal.

Claims (7)

[Claims] An internal circuit having a predetermined function; a power-on reset circuit for generating a reset signal when power is turned on; a logic processing of an output potential of the power-on reset circuit and a potential of another signal line; A semiconductor integrated circuit comprising: a mode determination circuit for selectively designating at least two modes of a test mode / another operation mode with respect to the internal circuit. 2. The semiconductor device further comprises: a forced reset terminal; a forced reset signal line connected to the forced reset terminal; and a pull-up resistor connected between the forced reset signal line and a power supply node. 2. The semiconductor integrated circuit according to claim 1, wherein the mode determination circuit calculates a logic between an output potential of the power-on reset circuit and a potential of the forced reset signal line. 3. A forced reset in which a normal operation is performed again in a test mode in which a test operation is performed after resetting the internal circuit, in a user mode in which normal operation is performed after reset, or in a user mode in which the normal operation is performed again. 3. The semiconductor integrated circuit according to claim 2, wherein a mode designation signal for selectively designating a mode is generated. 4. The mode determination circuit resets the internal circuit during a period in which the output potential of the power-on reset circuit is “L”, and then resets the output potential of the power-on reset circuit to “H”. If the potential of the forced reset signal wiring is “L”, a test mode is designated. If the potential of the forced reset signal wiring is “H” when the output potential of the power-on reset circuit becomes “H”, Specify the user mode and change the potential of the forced reset signal line from "L" to "L".
4. The semiconductor integrated circuit according to claim 1, wherein when the output potential of said power-on reset circuit is "H" when inverted to "H", the user mode is designated again. 5. An internal circuit having a predetermined function, a forced reset terminal for inputting a forced reset signal, a forced reset signal line connected to the forced reset terminal, and a connection between the forced reset signal line and a power supply node. A power-on reset circuit having a pull-up resistance element connected to the power supply circuit, a capacitor connected between the forced reset signal wiring and a ground node, and a diode connected in parallel to the pull-up resistance element; And a mode determination circuit for generating a mode designating signal for selectively designating a test mode for performing a test operation after resetting the internal circuit based on the potential of the internal circuit or a user mode for performing a normal operation after resetting. A semiconductor integrated circuit characterized by the above-mentioned. 6. The semiconductor integrated circuit according to claim 1, wherein the internal circuit has a function of a microcomputer. 7. An internal circuit having a function of a microcomputer, a forced reset terminal for inputting a forced reset signal, a forced reset signal line connected to the forced reset terminal, and a connection between the forced reset signal line and a power supply node. A test mode / reset for performing a test operation after resetting the internal circuit based on a potential of the pull-up resistance element connected therebetween, a diode connected in parallel with the pull-up resistance element, and the potential of the forced reset signal line; A semiconductor integrated circuit having a mode determination circuit for generating a mode designation signal for selectively designating a user mode for performing a normal operation later; and between the forced reset terminal and a ground potential external to the semiconductor integrated circuit. And a power-on reset circuit together with the pull-up resistor element and the diode. Capacitor and test mode setting circuit of a semiconductor integrated circuit characterized by comprising a forced reset switch connected between said forced reset pin outside the ground potential to the semiconductor integrated circuit.