JP2001273167A - Hardware break circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a hardware break circuit which is built up inside a processor and can be used as a cache memory after debugging is finished. SOLUTION: A break address and a break instruction are set in an address register 12 and an instruction register 15 respectively from a data bus 4 through selectors 11 and 14 in the case of performing debugging. When an address signal on an address bus 3 coincides with the break address, a comparator 13 controls a buffer 16, and the break instruction is given to a CPU 1 through a data bus 5 for instruction. In the case of a normal operation, the address signal on the bus 3 is held by the register 12 and an instruction code on the bus 5 is held by the register 15, respectively. When the address signal coincides with contents held by the register 12, the instruction code of the address is outputted to the bus 5 not from a main storage device 2 but from the register 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hardware break circuit for generating a break state such as an interrupt to a processor when a preset address is accessed during software debugging.

[0002]

2. Description of the Related Art Conventionally, a hardware break circuit used for software debugging is provided with a plurality of registers in advance or internally of a processor for holding a break target address, and outputs an address signal output from the processor. Is compared with the address held in the register. Then, when the address signal matches the address held in any of the registers, an interrupt signal is output to the processor.

[0003]

However, the conventional hardware break circuit has the following problems. For example, when a hardware break circuit is incorporated in a processor, after the software debug is completed, this circuit is not necessary but remains incorporated in the product. Therefore, compared with a processor in which a hardware break circuit is not incorporated, not only the circuit scale is increased, but also the processing speed is reduced and the power consumption is increased. Therefore, after the completion of the debugging, a method of redesigning the processor from which the hardware break circuit has been removed may be adopted, but it is sometimes difficult in terms of development period and cost.

On the other hand, when a hardware break circuit is provided outside the processor and a cache memory system is incorporated in the processor, the status of a program executed by the processor is externally provided during operation of the cache memory. It may not be output as an address signal. For this reason, there were cases where a complete hardware break function could not be realized. An object of the present invention is to provide a hardware break circuit which solves the problem of the prior art and which can be incorporated in a processor and used as a cache memory after debugging is completed.

[0005]

According to a first aspect of the present invention, an address signal output from a central processing unit (hereinafter referred to as a "CPU") in a debug mode is provided. A hardware break circuit for forcibly shifting the CPU to a predetermined specific state regardless of the instruction code of the program stored in the storage device when the set specific address is reached; Or, an address register holding an address executed by the CPU, break information for shifting the CPU to the specific state,
And an instruction register for holding an instruction code executed by the PU.

Further, this hardware break circuit has
When the address signal matches the content held in the address register, the content held in the instruction register
A comparator that outputs the control information to the PU; and, in the debug mode, the specific address is set in the address register and the break information is set in the instruction register. The address executed by the CPU is written to an address register, and the C register is written to the instruction register.
And a control unit that controls to write the instruction code executed by the PU.

[0007] According to the first invention, since the hardware break circuit is configured as described above, the following operation is performed. In the debug mode, an address signal output from the CPU is compared with a specific address held in an address register by a comparator. If they match, the break information stored in the instruction register is
Is output as a control signal for shifting to a specific state. In the normal operation mode, the address and the instruction code executed by the CPU are written in the address register and the instruction register by the control unit. Thus, when the address held in the address register is specified by the address signal, the instruction code is read not from the storage device but from the instruction register.

[0008] A second aspect of the present invention is a CPU in a debug mode.
A hardware break circuit for providing the CPU with specific data set when the address signal output from the CPU becomes a predetermined specific address, regardless of the data stored in the storage device. An address register holds an address or an address output from the CPU, and a data register holds the specific data to be given to the CPU or the data read from the storage device. The hardware break circuit further includes a comparator for outputting the content held in the data register as data to the CPU when the address signal matches the content held in the address register; The specific address is set and the specific data is set in the data register.In the normal operation mode, the address output from the CPU is written to the address register and the address is read from the storage device to the data register. And a control unit for controlling to write data.

According to the second aspect, the following operation is performed. In the debug mode, the address signal output from the CPU is compared by the comparator with the specific address held in the address register, and when they match, the specific data stored in the data register is given to the CPU. In the normal operation mode, the address specified by the CPU and the data read from the storage device are written into the address register and the data register by the control unit. Thus, when the address held in the address register is specified by the address signal, data is read from the data register instead of the storage device.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a configuration diagram of a hardware break circuit showing a first embodiment of the present invention. This hardware break circuit is
A plurality of break units 10 ₁ to 10 _n , a control unit 21, an n-input NOR gate (hereinafter referred to as “NOR”) 22, and three states are provided between U 1 and the main storage device 2. A buffer (hereinafter simply referred to as “buffer”) 23; An address bus (ABUS) 3 and a data bus (D bus) are provided between the CPU 1 and the main storage device 2.
BUS) 4. Further, the instruction code read from the main storage device 2 is provided to the CPU 1 via the buffer 23 and the instruction data bus (IBUS) 5.

The break sections 10 ₁ to 10 _n have the same configuration. For example the break unit 10 _1, 2
It has an input selector (SEL) 11, and its input terminals A and B are connected to the address bus 3 and the data bus 4, respectively. The selector 11 outputs the mode signal MO
The input terminal A is selected when the normal operation mode is designated by D, and the input terminal B is selected when the debug mode is designated. The output side of the selector 11 is connected to an address register (AREG) 12, and the output side of the address register 12 is a comparator (CMP) 1
3 is connected to the first input side. The second of the comparator 13
Are connected to the address bus 3. The comparator 13 outputs a match signal of level “H” when the signals on the first and second input sides match.

Furthermore, the address comparison unit 10 ₁ has a two-input of the selector 14, the input terminals A, B are connected to each instruction data bus 5 and a data bus 4. The selector 14 is controlled in the same manner as the selector 11 by the mode signal MOD. The output side of the selector 14 is connected to an instruction register (IREG) 15, and the output side of the instruction register 15 is connected to the instruction data bus 5 via a buffer 16. The control terminal of the buffer 16 is connected to the output side of the comparator 13. The conduction of the buffer 16 is controlled so as to be in the on state when the coincidence signal of the comparator 13 is “H” and to be in the high impedance state when it is at the level “L”. The output of the comparator 13 of the break portion ₁₀ 1 to 10 _n is further connected to the input side of the control unit 21 and NOR 22. The output side of the NOR 22 is connected to the control terminal of the buffer 25. The control unit 21
In accordance with the output signal and the mode signal MOD, etc. of the comparators 13 of each break ₁₀ 1 to 10 _n, each break portions ₁₀ 1 to 1
0n to control the address register 12 and the instruction register 15 within _n .

Next, the operation of FIG. 1 will be described by dividing it into (1) an operation in the debug mode and (2) an operation in the normal operation mode. (1) Operation to debugging when debugging mode, when the debug mode is designated by the mode signal MOD, the selector 11 and 14 of each break portions ₁₀ 1 to 10 _n is switched to the all the input terminal B side. Set breakpoints before starting software debugging. That is, the address of the break is written from the data bus 4 to the address register 12 through the selector 11. Further, in order to replace the instruction code of the address to be broken with debug break information such as a stop instruction, an interrupt instruction, or a jump instruction to a specific address, the break information is transmitted from the data bus 4 via the selector 14. Write to the instruction register 15. In this manner, the address register 12 and the instruction register 15 of each break portions ₁₀ 1 to 10 _n, to set different breakpoint respectively.

After setting a plurality of breakpoints, execution of the software to be debugged is started. According to the execution of the software, the CPU 1 transfers the address bus 3
Instruction addresses are sequentially output. The instruction address on the address bus 3 is stored in the comparator _{1 of} each of the break units 10 ₁ to 10 _n.
At 3, the address is compared with the address held in the address register 12. Instruction address, each break 10 _1
If the address does not match the address of the breakpoint set in the address register 12 of each of the comparators
The match signal of No. 3 is "L". Therefore, each break unit 1
The buffers 16 of 0 ₁ to 10 _n enter a high impedance state. On the other hand, the output signal of the NOR 22 becomes “H”, the buffer 23 is turned on, and the instruction code read from the main storage device 2 is supplied to the CPU 1 via the buffer 23 and the instruction data bus 5. This allows
As long as the instruction address does not match the breakpoint, the software to be debugged is sequentially executed without interruption.

Here, when the instruction address on the address bus 3 coincides with the break point, the contents of the address register 12 and the instruction address coincide in any one of the break sections 10 _i (i = 1 to n). Thereby, the coincidence signal of the comparator 13 of the break portion 10 _i is "H"
The break information stored in the instruction register 15 is output to the instruction data bus 5 via the buffer 16. On the other hand, the output signal of the NOR 22 becomes “L”, and the buffer 23 enters a high impedance state. Accordingly, the break information for debugging held in the instruction register 15 is given to the CPU 1, and a debugging operation such as stop, interruption, or specific processing is performed.

(2) Operation in Normal Operation Mode During normal operation, when the normal operation mode is designated by the mode signal MOD, all the selectors 11 and 14 of the break sections 10 ₁ to 10 _n are connected to the input terminal A side. Can be switched. When the normal business software is executed, the CPU 1
, The instruction addresses are sequentially output to the address bus 3. Instruction address on the address bus 3, in the comparator 13 of each break portions 10 ₁ to 10 _n, it is compared with the address held in the address register 12.

[0017] The instruction address, each break section ₁₀ 1 to 1
_If the address does not match the address held in the address register 12 of 0n, the match signal of each comparator 13 is "L". Therefore, the buffer 16 of each break portions ₁₀ 1 to 10 _n becomes high-impedance state. On the other hand, NOR2
2 becomes “H”, the buffer 23 is turned on, and the instruction code read from the main storage device 2 is:
CPU 1 via the buffer 23 and the instruction data bus 5
Given to. Thus, the CPU 1 executes the normal business program according to the instruction code read from the main storage device 2.

Meanwhile, the control unit 21, for one break portion 10 _i address register 12 and the instruction register 15, the control signal for data retention is provided. Thus, the address register 12 and the instruction register 15 store
The instruction address executed by the CPU 1 and its instruction code are stored in correspondence. As described above, when an instruction address that is not held in the instruction register 12 of each of the break units 10 ₁ to 10 _n is specified, the instruction code is read from the main storage device 2 and the instruction address and the instruction code are stored in the break address. the address register 12 and the instruction register 15 parts ₁₀ 1 to 10 _n, it is sequentially held.

Here, the instruction address output from the CPU 1 is
If any of the breaks 10 _iAddress Regis
When the instruction address matches the instruction address held in the
13 coincidence signal becomes “H” and held in the instruction register 15
The instruction code used for the instruction via the buffer 16
Output to the data bus 5. On the other hand, the output signal of NOR22
Signal becomes "L", and the buffer 23 has high impedance.
State. Thus, the CPU 1 has the main storage device 2
Instead, the instruction code is given from the instruction register 15.
You. That is, the break unit 10₁-10_nIs the cache
Works as a moly.

As described above, the hardware break circuit of the first embodiment has a conventional hardware break function using the address register 12 and the comparator 13. Further, since it has an instruction register 15 for rewriting an instruction at a breakpoint, an instruction code for correcting a program is set in the instruction register 15 so that a program for a non-rewritable main storage area such as a ROM can be set. Can be modified. On the other hand, in the normal operation mode, the configuration is such that the address of the instruction accessed in the past in the past in accordance with the execution of the program and the instruction code thereof are stored in the address register 12 and the instruction register 15. As a result, the hardware break circuit can be operated as a cache memory, and the execution speed of the program can be improved.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
FIG. 2 is a configuration diagram of a hardware break circuit according to the first embodiment, in which components common to those in FIG. 1 are denoted by common reference numerals. This hardware breakpoint circuit, instead of the break unit ₁₀ 1 to 10 _n in FIG. 1, provided with a different break portion _10A 1 10 A _n constitutively, has a configuration obtained by adding the cache memory 24. Accordingly, a control unit 21A having a different function is provided in place of the control unit 21.

The break portion _10A 1 10 A _n are all in the same configuration, for example, the break portion 10A ₁ is provided with a selector 17, 18 of the three inputs. The input terminal A of the selector 17 is connected to the address bus 3, the input terminal B is connected to a cache address bus (CBUS) 6 from which address information is output from the cache memory 24, and the input terminal C is connected to the data bus 4. The output side of the selector 17 is connected to the input side of the address register 12.

The input terminal A of the selector 18 is connected to the data output terminal of the cache memory 25, the input terminal B is connected to the instruction data bus 5, and the input terminal C is connected to the data bus 4. The output side of the selector 18 is connected to the input side of the instruction register 15. Selector 17, 1
The control unit 8 controls the switching by the control unit 21A. The output of the comparator 13 of each break portions _10A 1 10 A _n is connected to the control terminal of the buffer 16 respectively, are connected to the control unit 21A. The conduction state of the buffer 23 is controlled by a control signal provided from the control unit 21A.

The cache memory 24 is composed of a small-capacity memory having an access speed higher than that of the main storage device 2. The content of a fixed area including an accessed address is copied from the main storage device 2 and held, and This is to improve the access speed. Cache memory 24
Is an address terminal to which an address signal is applied, a data input terminal to which write data is applied, a data output terminal to output read data, a cache address terminal to output address information of held data, and And a hit output terminal for outputting hit information as to whether or not data corresponding to the given address signal exists. The address terminal of the cache memory 24 is connected to the address bus 1, the data input terminal is connected to the instruction data bus 5,
The data output terminal is connected to the instruction data bus 5 via the buffer 25, the cache address terminal is connected to the cache address bus 6, and the hit output terminal is connected to the control unit 21A. The conduction state of the buffer 25 is controlled by a control signal from the control unit 21A. Other configurations are the same as those in FIG.

Next, the operation of FIG. 2 will be described by dividing it into (1) an operation in the debug mode and (2) an operation in the normal operation mode. (1) Operation in debug mode When the debug mode is specified by the mode signal MOD during debugging,
Each break unit 10A _{1 to} 10A _{n is} controlled by the control unit 21A.
Selectors 17 and 18 are switched to the input terminal C side. First, the address to be broken is written from the data bus 4 to the address register 12 via the selector 17. Further, the debug information is written from the data bus 4 to the instruction register 15 via the selector 18.
In this manner, the break portion _A10 1 10 A _n,
Set different breakpoints for each.

After setting a plurality of breakpoints, execution of the software to be debugged is started. According to the execution of the software, the CPU 1 transfers the address bus 3
Instruction addresses are sequentially output. The instruction address on the address bus 3 is stored in the comparator _{1 of} each of the break units 10 ₁ to 10 _n.
At 3, the address is compared with the address held in the address register 12. Comparison result of the comparator 13 of each break portions _10A 1 10 A _n is given to the control unit 21A and the buffer 16. At the same time, the instruction address on the address bus 3 is given to the cache memory 24, and hit information indicating whether the corresponding address exists in the cache memory 24 is output to the control unit 21A. Instruction address, if match one of the set break points in the address register 12 of each break portions _10A 1 10 A _n, the break portion 10A _i (where, i =. 1 to
The instruction code stored in the instruction register 15 of (n) is output to the instruction data bus 5 via the buffer 16. Thereby, the break information for debugging held in the instruction register 15 is given to the CPU 1,
A debugging operation is performed.

On the other hand, if the instruction address is
To both not match the breakpoints set in A ₁ 10 A _n, if present in the cache memory 24,
The corresponding instruction code from the cache memory 24 is
The data is output to the instruction data bus 5 via the buffer 25. If the instruction address does not exist in the cache memory 24, the instruction code read from the main storage device 2 is supplied to the CPU 1 via the buffer 23 and the instruction data bus 5. Thus, as long as the instruction address does not match the set break point break portion 10A ₁ 10 A _n, debugged software are executed sequentially without interruption.

[0028] (2) during normal operation the normal operation of the operation mode, when the normal operation mode is designated by the mode signal MOD, the control unit 21A, the selector 17, 18 of each break portions _10A 1 10 A _n, input Switch to terminal A or B side. When the software for the normal business is executed, the CPU 1 transfers the software to the address bus 3.
Instruction addresses are sequentially output. Instruction address on the address bus 3, in the comparator 13 of each break portions _10A 1 10 A _n, is compared with the address held in the address register 12. At the same time, the instruction address on the address bus 3 is given to the cache memory 24, and hit information indicating whether the corresponding address exists in the cache memory 24 is output to the control unit 21A.

If the instruction address is in each of the break sections 10A ₁ to 10A _1
If the address matches one of the addresses held in the address register 12 of 10An, the matching break unit 10
Instruction code held in the instruction register 15 of A _i are outputted to the instruction data bus 5 via the buffer 16.
In the CPU 1, according to the instruction on the instruction data bus 5,
A normal business program is executed. At this time, the instruction of the corresponding line in the cache memory 24 and the register 1
5 is exchanged with the instruction code stored in 5. When the instruction address is in each of the break sections 10A _{1 to} 10A _n
If the address does not match the address held in the address register 12 and exists in the cache memory 24, the corresponding instruction code is output from the cache memory 24 to the instruction data bus 5 via the buffer 25.

The instruction address is set to each of the break units 10A ₁ to 10A ₁ to
_If the address does not match the address held in the address register 12 of 10An and does not exist in the cache memory 24, the corresponding instruction code is read from the main storage device 2, and the instruction code is read out via the buffer 23. Output to the data bus 5. At the same time, the address signal on the address bus 3 is held in the address register 12 via the selector 17. The instruction code on the instruction data bus 5 is held in the instruction register 15 via the selector 18. As described above, the hardware break circuit according to the second embodiment adds the cache memory 24 to the hardware break circuit according to the first embodiment. Thereby, in addition to the advantage of the first embodiment, there is an advantage that high-speed processing by the cache memory 24 becomes possible.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
FIG. 3 is a configuration diagram of a hardware break circuit according to the embodiment of the present invention, wherein components common to those in FIG. 2 are denoted by common reference numerals. This hardware breakpoint circuit, instead of the break portion _10A 1 10 A _n in FIG. 2, provided with a different break portion _10B 1 _{~10B n} constitutively, in place of the control unit 21A, a different control unit 21B of function Provided. The break units 10B _{1 to} 10B _n have the same configuration. For example, the break unit 10B ₁ includes a selector 17 with three inputs and a selector 19 with two inputs. The input terminals A, B, and C of the selector 17 are connected to the address bus 3, the cache address bus 6, and the data bus 4, respectively, and the output side of the selector 17 is connected to the address register 12.

The input terminal A of the selector 19 is connected to the data output terminal of the cache memory 25, and the input terminal B is connected to the data bus 4. The output side of the selector 19 is connected to a data register (DREG) 20, and the output side of the data register 20 is connected to the data bus 4 via the buffer 16. Each break part 10B
₁ output of the comparator 13 of ～10B _n is connected to the control unit 21B, a selector 17, 19, and buffer 16,
Switching control is performed by the control unit 21B. Further, a break request signal BRK is output from the control unit 21B to the CPU 1, and the CPU 1
, An access control signal ACS is supplied to the control unit 21B. The data input terminal of the cache memory 24 is connected to the data bus 4, the data output terminal is connected to the input terminal A of the selector 19, the data bus 4 via the buffer 25, and the hit output terminal is connected to the control unit 21B. Other configurations are the same as those in FIG.

Next, the operation of FIG. 3 is described by (1) hardware
Break operation, (2) Debug operation, and (3)
The operation will be described separately for normal operation. (1) Hardware break operation Before starting the hardware break operation, a breakpoint
In order to set points, the control unit 21B
Part 10B₁-10B_nAnd the selector 17 is connected to the input terminal C side.
Outputs a control signal to switch to. And break vs
Address of the elephant from the data bus 4 via the selector 17
To the address register 12. Multiple breakpoints
After setting the point, start software execution.
You. Following the execution of the software, the address from CPU1
Address signals are sequentially output to the bus 3 and each break unit
10B₁-10B_nAddress comparator 13
The address is compared with the address held in the register 12. Each blur
Work part 10B₁-10B _nResult of comparator 13
Is given to the control unit 21B. At the same time, the address bus
3 is given to the cache memory 24.
The hit information is transferred from the cache memory 24 to the control unit.
21B.

The address signal is applied to each of the break units 10B ₁ to 10B ₁ .
When any one of the breakpoints set in 10B _n is matched, the break part 10 _i (where i = 1 to n)
Are sent from the comparator 13 to the control unit 21B, such as address matching and read / write conditions. In the control unit 21B,
The access control signal ACS from the CPU 1 and the comparator 13
Is determined based on the match signal from the CPU 1 and a break request signal BRK is sent to the CPU 1 when the break condition is satisfied. In the CPU 1, a break process is performed according to the break request signal BRK.

On the other hand, the address signals on the address bus 3, to both not match the breakpoints set in the break portion 10B ₁ ~10B _n, if present in the cache memory 24, the cache memory 24 on Is processed as access to the data. If the corresponding address does not exist in the cache memory 24,
The process is performed as data access to the main storage device 2, and a data replacement process of the cache memory 24 is performed by the data accessed to the main storage device 2.

(2) Operation during Debugging Prior to the start of software debugging, conditions such as a target address and read / write are written from the data bus 4 to the address register 12 via the selector 17. Further, specific data for debugging is written from the data bus 4 to the data register 20 via the selector 19. When software debugging is started, the address signal output from the CPU 1 to the address bus 3
By the comparator 13 of 0B ₁ ~10B _n, it is compared with the address held in the address register 12. The address signal on the address bus 3 is transmitted to the cache memory 2.
4 for hit determination and data access.

When the address signal on the address bus 3 matches the address held in the address register 12,
A match signal is sent from comparator 13 to control unit 21B. In the control unit 21B, the access control signal AC
In the case of read access, the buffer 16 is controlled to the ON state on the basis of the coincidence signal from the comparator 13 and S, and the specific data corresponding to the address is output from the data register 20 to the data bus 4. In the case of write access, data on the data bus 4 is written to the data register 20 via the selector 19.

If the address signal on the address bus 3 does not match the content held in the address register 12 and exists in the cache memory 24, the cache memory 24
Treated as access to data in If the address signal on the address bus 3 does not match the content held in the address register 12 and does not exist in the cache memory 24, it is processed as a data access to the main storage device 2. At the same time, data replacement processing to the cache memory 24 is performed by the data accessed to the main storage device 2.

(3) Operation in Normal Operation When the software for normal operation is executed, the address signal output from the CPU 1 to the address bus 3
Is compared with the address held in the address register 12. Further, the address signal on the address bus 3 is given to the cache memory 24, and hit determination and data access are performed. When the address signal on the address bus 3 matches the address held in the address register 12, a match signal is sent from the comparator 13 to the control unit 21B. In the control unit 21B, based on the access control signal ACS from the CPU 1 and the coincidence signal from the comparator 13, in the case of read access, the buffer 16 is controlled to the ON state, and the data register 20
The data corresponding to the address is output. In the case of write access, data on the data bus 4 is written to the data register 20 via the selector 19. At this time, the data of the corresponding line in the cache memory 24 is sent to the data register 20, the address of the corresponding line is sent to the address register 12 via the cache address bus 6 and the selector 17, and the data in the data register 20 is sent to the cache memory 24. , The data on the address on the address bus 3 and the corresponding line in the cache memory 24 are exchanged with each other.

If the address signal on the address bus 3 does not match the content held in the address register 12 and exists in the cache memory 24, the cache memory 24
Treated as access to data in If the address signal on the address bus 3 does not match the content held in the address register 12 and does not exist in the cache memory 24, it is processed as an access to data in the main storage device 2. At the same time, data replacement processing of the data in the address register 12 and the data register 20 and the data in the main storage device 2 is performed.

As described above, the hardware break circuit of the third embodiment has the address register 12 for setting the break target address and the flake condition such as read / write, so that the hardware break circuit is the same as the conventional one. A hardware break function for the CPU 1 can be realized. Further, since the data register 20 which can set specific data for program correction is provided, it is possible to correct the program in the main storage area such as the ROM which cannot be rewritten at the time of debugging or the like. . Furthermore, during normal operation, the break portion 10B ₁ ~10B _n on the cache memory 24 can be operated as a secondary cache memory, the capacity of the cache memory is increased, further improving the execution speed of the program Can be.

[0042]

As described above in detail, according to the first aspect, a specific address for breaking the CPU is set in the debug mode, and the address output from this CPU is written in the normal operation mode. It has an address register and an instruction register in which break data for the CPU is set in the debug mode and an instruction code read from the storage device is written in the normal operation mode. Thus, there is an effect that the hardware break operation is performed in the debug mode and the cache memory can be used in the normal operation mode.

According to the second aspect, in the debug mode, a specific address for breaking the CPU is set. In the normal operation mode, an address register for writing an address output from the CPU, and in the debug mode, a specific address for the CPU is set. It has a data register in which data is set and in which data read from the storage device is written in the normal operation mode. Thus, there is an effect that the hardware break operation is performed in the debug mode and the cache memory can be used in the normal operation mode.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a hardware break circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a hardware break circuit according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a hardware break circuit according to a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Main storage device 3 Address bus 4 Data bus 5 Instruction data bus 6 Cache address bus 10, 10A, 10B Break part 11, 14, 17, 18, 19 Selector 12 Address register 13 Comparator 15 Instruction register 16, 23 , 25 buffers 20 data buffers 21, 21A, 21B control unit 24 cache memory

Claims (2)

[Claims] When an address signal output from a central processing unit in a debug mode reaches a predetermined specific address, the central processing unit is controlled in advance regardless of an instruction code of a program stored in a storage device. A hardware break circuit for forcibly shifting to the set specific state; an address register for holding the specific address or the address executed by the central processing unit; and for shifting the central processing unit to the specific state. An instruction register for holding break information or an instruction code executed by the central processing unit; and controlling the content of the instruction register to the central processing unit when the address signal matches the content of the address register. A comparator that outputs the information; and Address register and the break information in the instruction register. In a normal operation mode other than the debug mode, the address executed by the central processing unit is written into the address register and the instruction is written. A control unit for controlling the instruction code executed by the central processing unit to be written into the register. 2. When the address signal output from the central processing unit in the debug mode becomes a predetermined specific address, regardless of the data stored in the storage device, the specific signal set in the central processing unit is set in advance. A hardware break circuit for providing data, an address register holding the specific address or an address output from the central processing unit; and the specific data to be supplied to the central processing unit or the data read from the storage device. A data register for holding the address register; and a comparator for outputting the held content of the data register as data to the central processing unit when the address signal matches the held content of the address register. Setting the specific address in the register The specific data is set in the data register, and in a normal operation mode other than the debug mode, an address output from the central processing unit is written to the address register and read from the storage device to the data register. A hardware break circuit, comprising: a control unit that controls so as to write data.