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JP2001269862A - Polishing pad, polishing device, and polishing method - Google Patents

Polishing pad, polishing device, and polishing method

Info

Publication number
JP2001269862A
JP2001269862A JP2000086382A JP2000086382A JP2001269862A JP 2001269862 A JP2001269862 A JP 2001269862A JP 2000086382 A JP2000086382 A JP 2000086382A JP 2000086382 A JP2000086382 A JP 2000086382A JP 2001269862 A JP2001269862 A JP 2001269862A
Authority
JP
Japan
Prior art keywords
polishing
conductive
substrate
polished
polishing pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000086382A
Other languages
Japanese (ja)
Inventor
Kenro Nakamura
賢朗 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000086382A priority Critical patent/JP2001269862A/en
Priority to US09/816,169 priority patent/US6620336B2/en
Publication of JP2001269862A publication Critical patent/JP2001269862A/en
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/11Lapping tools
    • B24B37/20Lapping pads for working plane surfaces
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23HWORKING OF METAL BY THE ACTION OF A HIGH CONCENTRATION OF ELECTRIC CURRENT ON A WORKPIECE USING AN ELECTRODE WHICH TAKES THE PLACE OF A TOOL; SUCH WORKING COMBINED WITH OTHER FORMS OF WORKING OF METAL
    • B23H5/00Combined machining
    • B23H5/06Electrochemical machining combined with mechanical working, e.g. grinding or honing
    • B23H5/08Electrolytic grinding
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/046Lapping machines or devices; Accessories designed for working plane surfaces using electric current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PROBLEM TO BE SOLVED: To easily and reliably detect the end point of the polishing of CMP or the like. SOLUTION: This polishing device is provided with a polishing board 101 fitted with a polishing pad 103 having a plurality of conduction parts 109 separated from each other in the planar direction, a hold part 104 holding a substrate to be processed 106 to face its polished face to the polishing board 101 fitted with the polishing pad 103, drive parts 102 and 105 relatively moving the polishing board 101 and the hold part 104, and a detection part 111 detecting the conductive state of the polished face of the substrate to be worked 106 held by the hold part 104 via a plurality of conduction parts 109 provided on the polishing pad 103.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、研磨パッド、研磨
装置及び研磨方法、特に半導体装置の製造に好適な研磨
パッド、研磨装置及び研磨方法に関する。
The present invention relates to a polishing pad, a polishing apparatus, and a polishing method, and more particularly to a polishing pad, a polishing apparatus, and a polishing method suitable for manufacturing a semiconductor device.

【0002】[0002]

【従来の技術】近年、半導体装置の製造分野において、
半導体装置の高密度化及び微細化に伴い、種々の微細加
工技術が研究開発されている。その中で化学的機械的研
磨(CMP)技術は、層間絶縁膜の平坦化、プラグの形
成、埋め込み金属配線の形成、埋め込み素子分離の形成
などを行う際に、欠かすことのできない必須の技術にな
っている。
2. Description of the Related Art In recent years, in the field of manufacturing semiconductor devices,
With the increase in density and miniaturization of semiconductor devices, various microfabrication techniques have been researched and developed. Among them, the chemical mechanical polishing (CMP) technology is an indispensable technology when performing the planarization of the interlayer insulating film, the formation of the plug, the formation of the buried metal wiring, and the formation of the buried element isolation. Has become.

【0003】CMP技術における課題の一つに、終点検
出がある。現在、半導体ウェハ表面と研磨パッドの間の
摩擦を研磨中にモニターする方法が一般的である。この
摩擦力を、研磨定盤或いは研磨ヘッドを回転させるモー
ターの電流値によってモニターし、その変化から終点検
出を行う方法は広く実用化されている。
[0003] One of the problems in the CMP technique is end point detection. At present, it is common to monitor the friction between the semiconductor wafer surface and the polishing pad during polishing. A method of monitoring this frictional force by a current value of a polishing platen or a motor for rotating a polishing head and detecting an end point from the change has been widely used.

【0004】しかしながら、研磨条件或いは被研磨面の
膜構造によっては、この摩擦力の変化が顕著に現れない
場合がある。例えば、研磨時の荷重が小さい場合は、一
般に摩擦力の変化が現れ難い。
However, depending on the polishing conditions or the film structure of the surface to be polished, the change in the frictional force may not appear remarkably. For example, when the load at the time of polishing is small, a change in the frictional force generally hardly appears.

【0005】別の終点検出方法として、光学的にモニタ
ーする方法がある。研磨中の半導体ウェハ表面の膜厚を
光学的に測定したり、ウェハ表面の反射率から膜種の変
化を観たりするものである。
As another end point detection method, there is a method of optically monitoring. This is for optically measuring the film thickness on the surface of the semiconductor wafer during polishing, and for observing the change in the film type from the reflectivity of the wafer surface.

【0006】しかしながら、この方法では、研磨中の半
導体ウェハ表面に何らかの手段によって光を到達させる
必要があり、技術的な困難を伴う。光を直接ウェハ表面
に到達させようとすると、研磨定盤に穴を開けて光源を
設ける、半導体ウェハのオーバーハング位置に光をあて
る、といった手段を講じる必要があるが、半導体ウェハ
面内における研磨状態に悪影響を与えるという懸念があ
る。また、半導体ウェハの裏面側から半導体ウェハを通
過する波長領域の光をあてる手法も考えられるが、研磨
ヘッドにこのような装置を設けることは、技術的なハー
ドルが高いことが予想される。
However, in this method, it is necessary to make light reach the surface of the semiconductor wafer being polished by some means, which involves technical difficulties. In order to make the light directly reach the wafer surface, it is necessary to take measures such as making a hole in the polishing platen to provide a light source and illuminating the overhang position of the semiconductor wafer with light. There is concern that the condition will be adversely affected. In addition, a method of irradiating light in a wavelength region passing through the semiconductor wafer from the back side of the semiconductor wafer is also conceivable. However, providing such a device in the polishing head is expected to have high technical hurdles.

【0007】[0007]

【発明が解決しようとする課題】このように、CMP技
術における課題の一つとして終点検出があるが、従来の
終点検出手法は必ずしも満足できるものとは言えなかっ
た。
As described above, end point detection is one of the problems in the CMP technique, but the conventional end point detection method has not always been satisfactory.

【0008】本発明は上記従来の課題に対してなされた
ものであり、CMP等の研磨における終点検出を容易か
つ確実に行うことが可能な研磨パッド、研磨装置及び研
磨方法を提供することを目的としている。
An object of the present invention is to provide a polishing pad, a polishing apparatus and a polishing method capable of easily and reliably detecting an end point in polishing such as CMP. And

【0009】[0009]

【課題を解決するための手段】本発明に係る研磨パッド
は、被処理基板表面の研磨に用いる研磨パッドであっ
て、面方向で互いに離間した複数の導電部を有すること
を特徴とする。
A polishing pad according to the present invention is a polishing pad used for polishing a surface of a substrate to be processed, and has a plurality of conductive portions spaced apart from each other in a plane direction.

【0010】本発明に係る研磨装置Aは、面方向で互い
に離間した複数の導電部を有する研磨パッドが装着され
る研磨盤と、被処理基板を保持して被処理基板の被研磨
面を前記研磨パッドが装着された研磨盤に対向させる保
持部と、前記研磨盤と前記保持部とを相対的に動かす駆
動部と、前記保持部に保持された被処理基板の被研磨面
の導電状態を前記研磨パッドが有する複数の導電部を介
して検出する検出部と、を有することを特徴とする。
A polishing apparatus A according to the present invention comprises: a polishing table on which a polishing pad having a plurality of conductive portions spaced apart from each other in a surface direction is mounted; and a polishing surface of the substrate to be processed while holding the substrate to be processed. A holding unit that faces a polishing board on which a polishing pad is mounted, a driving unit that relatively moves the polishing board and the holding unit, and a conductive state of a polished surface of a substrate to be processed held by the holding unit. And a detecting unit for detecting through a plurality of conductive portions of the polishing pad.

【0011】本発明によれば、被処理基板上に形成され
た金属膜等の導電体膜(金属膜以外でも、導電性を有す
る膜であればよく、例えばポリシリコンのような半導体
膜であってもよい。)の研磨工程において、被処理基板
の被研磨面の導電状態を複数の導電部を介して検出する
ことにより、簡便な方法によって研磨の終点検出を容易
かつ確実に行うことが可能となる。したがって、研磨が
不十分或いは過剰になることなく、適切な研磨を行うこ
とができる。
According to the present invention, a conductive film such as a metal film formed on a substrate to be processed (other than a metal film, any conductive film may be used. For example, a semiconductor film such as polysilicon may be used. In the polishing step, the conductive state of the surface to be polished of the substrate to be polished is detected via a plurality of conductive portions, so that the end point of polishing can be easily and reliably detected by a simple method. Becomes Therefore, appropriate polishing can be performed without insufficient or excessive polishing.

【0012】前記複数の導電部は、同心円状或いは散点
状に配置されていることが好ましいが、特に散点状に配
置する場合には研磨パッドを比較的低コストで生産する
ことができる。
It is preferable that the plurality of conductive portions be arranged concentrically or in a scattered manner. In particular, when the plurality of conductive portions are arranged in a scattered manner, a polishing pad can be produced at a relatively low cost.

【0013】また、前記複数の導電部を導電性高分子樹
脂を用いて形成することにより、導電部と導電部以外の
領域とで、研磨パッド表面の性質を類似させることがで
き、導電部による研磨特性への影響を低減することがで
きる。
Further, by forming the plurality of conductive portions using a conductive polymer resin, the properties of the polishing pad surface can be made similar between the conductive portion and the region other than the conductive portion. The effect on the polishing characteristics can be reduced.

【0014】また、前記検出部は、前記複数の導電部間
に高周波電圧を印加することにより、被処理基板の被研
磨面の導電状態を検出するものであることが好ましい。
高周波電圧を印加することにより、スラリーの電気分解
及び電気分解に伴う被処理基板上の金属膜の腐食を防止
することができるとともに、導電部と被研磨面との接触
が完全でない場合にも容量カップリングによって導電状
態を検出することが可能となる。
It is preferable that the detecting section detects a conductive state of a polished surface of a substrate to be processed by applying a high-frequency voltage between the plurality of conductive sections.
By applying a high frequency voltage, the electrolysis of the slurry and the corrosion of the metal film on the substrate to be processed due to the electrolysis can be prevented, and even when the contact between the conductive part and the surface to be polished is not perfect, the capacitance can be reduced. The coupling makes it possible to detect the conductive state.

【0015】本発明に係る研磨装置Bは、面方向で互い
に離間した複数の導電部を有し、該複数の導電部の先端
部が研磨パッドが装着される面から突出した突出部とな
っており、前記複数の導電部の突出部に対応した複数の
穴が設けられた研磨パッドが装着される研磨盤と、被処
理基板を保持して被処理基板の被研磨面を前記研磨パッ
ドが装着された研磨盤に対向させる保持部と、前記研磨
盤と前記保持部とを相対的に動かす駆動部と、前記保持
部に保持された被処理基板の被研磨面の導電状態を前記
複数の導電部を介して検出する検出部と、を有すること
を特徴とする。
The polishing apparatus B according to the present invention has a plurality of conductive portions spaced apart from each other in the surface direction, and the tips of the plurality of conductive portions are formed as protruding portions protruding from the surface on which the polishing pad is mounted. A polishing plate on which a polishing pad provided with a plurality of holes corresponding to the protrusions of the plurality of conductive portions is mounted, and the polishing pad is mounted on a surface to be polished of the substrate to be processed while holding the substrate to be processed. A holding unit that faces the polished plate, a driving unit that relatively moves the polishing plate and the holding unit, and a conductive state of the surface to be polished of the substrate to be processed held by the holding unit, the plurality of conductive members. And a detection unit that detects the signal via the unit.

【0016】本発明によっても、研磨装置Aと同様、被
処理基板の被研磨面の導電状態を複数の導電部を介して
検出することにより、簡便な方法によって研磨の終点検
出を容易かつ確実に行うことが可能となる。また、研磨
パッドに導電部を設けず、研磨盤に設けた複数の導電部
の突出部に対応した複数の穴を研磨パッドに設ければよ
いので、研磨パッドをさらに低コストで生産することが
できる。
According to the present invention, similarly to the polishing apparatus A, the conductive state of the surface to be polished of the substrate to be processed is detected through a plurality of conductive portions, so that the end point of polishing can be easily and reliably detected by a simple method. It is possible to do. Further, since the polishing pad is not provided with a conductive portion, and a plurality of holes corresponding to the protrusions of the plurality of conductive portions provided on the polishing board may be provided in the polishing pad, the polishing pad can be produced at lower cost. it can.

【0017】本発明に係る研磨装置Cは、面方向で互い
に離間した複数の導電部を有し、表面が研磨面となって
いる研磨盤と、被処理基板を保持して被処理基板の被研
磨面を前記研磨盤の研磨面に対向させる保持部と、前記
研磨盤と前記保持部とを相対的に動かす駆動部と、前記
保持部に保持された被処理基板の被研磨面の導電状態を
前記複数の導電部を介して検出する検出部と、を有する
ことを特徴とする。
The polishing apparatus C according to the present invention has a plurality of conductive portions which are spaced apart from each other in the plane direction and has a polishing surface having a polished surface, and a substrate to be processed which holds the substrate to be processed. A holding unit for causing the polishing surface to face the polishing surface of the polishing machine; a driving unit for relatively moving the polishing machine and the holding unit; and a conductive state of the surface to be polished of the substrate to be processed held by the holding unit. And a detecting unit for detecting through the plurality of conductive units.

【0018】本発明によっても、研磨装置Aと同様、被
処理基板の被研磨面の導電状態を複数の導電部を介して
検出することにより、簡便な方法によって研磨の終点検
出を容易かつ確実に行うことが可能となる。
According to the present invention, similarly to the polishing apparatus A, the conductive state of the surface to be polished of the substrate to be processed is detected through a plurality of conductive portions, so that the end point of polishing can be easily and reliably detected by a simple method. It is possible to do.

【0019】研磨装置B及びCにおいて、前記複数の導
電部は、同心円状或いは散点状に配置されていることが
好ましいが、特に散点状に配置する場合には研磨盤を比
較的低コストで生産することができる。また、研磨装置
Aと同様、前記複数の導電部間に高周波電圧を印加する
ことが好ましい。
In the polishing apparatuses B and C, the plurality of conductive portions are preferably arranged concentrically or in a scattered point. Can be produced in Further, similarly to the polishing apparatus A, it is preferable to apply a high-frequency voltage between the plurality of conductive parts.

【0020】なお、本発明において、研磨の概念には、
CMPの他、砥石を用いた研削も含まれるものとする。
In the present invention, the concept of polishing includes:
In addition to CMP, grinding using a grindstone is also included.

【0021】[0021]

【発明の実施の形態】以下、本発明の実施形態を図面を
参照して説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0022】(実施形態1)図1は本発明の第1の実施
形態に係る研磨装置の概略構成を模式的に示した図であ
り、図1(a)は同研磨装置を横から見た概略図、図1
(b)は同装置の主要部を上から見た概略図である。
(Embodiment 1) FIG. 1 is a view schematically showing a schematic configuration of a polishing apparatus according to a first embodiment of the present invention. FIG. 1 (a) shows the polishing apparatus viewed from the side. Schematic diagram, FIG.
(B) is the schematic which looked at the principal part of the apparatus from the top.

【0023】図1に示すように、研磨定盤101は、研
磨定盤回転軸102を中心に水平面内で矢印の方向に回
転するようになっており、その主表面上には研磨パッド
103が貼付されるようになっている。
As shown in FIG. 1, the polishing platen 101 rotates in a direction indicated by an arrow in a horizontal plane about a polishing platen rotating shaft 102, and a polishing pad 103 is provided on a main surface thereof. It is to be attached.

【0024】研磨定盤101の中心から偏心した位置の
上方には、半導体ウェハの保持部104が配置され、半
導体ウェハの保持部回転軸105を中心に、水平面内で
研磨定盤101と同方向に回転するようになっている。
この半導体ウェハ保持部104は、その下面において研
磨対象となる半導体ウェハ106を真空チャック等によ
って保持するようになっている。そして、保持された半
導体ウェハ106の被研磨面が研磨パッド103の研磨
面と接触するように、シリンダなどの駆動機構によって
一定の圧力で押圧されるようになっている。
Above a position eccentric from the center of the polishing platen 101, a holding portion 104 of the semiconductor wafer is disposed, and the same direction as the polishing platen 101 in a horizontal plane about a holding portion rotating shaft 105 of the semiconductor wafer. It is designed to rotate.
The lower surface of the semiconductor wafer holding unit 104 holds a semiconductor wafer 106 to be polished by a vacuum chuck or the like. Then, a driving mechanism such as a cylinder is pressed with a constant pressure so that the polished surface of the held semiconductor wafer 106 comes into contact with the polished surface of the polishing pad 103.

【0025】研磨定盤101の中心部の上方には、スラ
リー供給管107が配置され、このスラリー供給管10
7から研磨パッド103上にスラリー108が供給され
るようになっている。
Above the center of the polishing platen 101, a slurry supply pipe 107 is provided.
From 7, the slurry 108 is supplied onto the polishing pad 103.

【0026】研磨パッド103には、同心円上に2本の
研磨パッド導電部109が互いに離間して研磨パッド本
体(絶縁物)内に埋め込まれており、研磨時に半導体ウ
ェハ106の表面が2本の導電部109に接触するよう
に、2本の導電部109間の距離は設定されている。こ
の2本の導電部109には、電流モニター111の端子
110が接触するようになっており、電流モニター11
1によって高周波電圧が印加される。電流モニター11
1は、2本の導電部109間に流れる電流をモニター
し、そのモニター結果に基づいてCMP動作を制御でき
るようになっている。
In the polishing pad 103, two polishing pad conductive portions 109 are concentrically embedded in the polishing pad main body (insulator) so as to be separated from each other. The distance between the two conductive portions 109 is set so as to make contact with the conductive portion 109. The terminals 110 of the current monitor 111 come into contact with the two conductive portions 109, and the current monitor 11
1 applies a high frequency voltage. Current monitor 11
1 monitors the current flowing between the two conductive portions 109, and can control the CMP operation based on the monitoring result.

【0027】図2(a)は、図1に示した研磨装置によ
ってCMP処理が施される半導体ウェハ106の断面構
成を示した図である。すなわち、半導体ウェハ106の
主表面側にはシリコン酸化膜11が形成されており、こ
のシリコン酸化膜11に形成された配線用の溝を埋め込
むようにメタル膜12が成膜されている。本例では、こ
のような構造を有するデバイス面に対し、CMPによっ
て図2(b)に示すようなダマシン配線を形成するもの
とする。
FIG. 2A is a diagram showing a cross-sectional configuration of a semiconductor wafer 106 subjected to a CMP process by the polishing apparatus shown in FIG. That is, the silicon oxide film 11 is formed on the main surface side of the semiconductor wafer 106, and the metal film 12 is formed so as to fill the trench for wiring formed in the silicon oxide film 11. In this example, it is assumed that a damascene wiring as shown in FIG. 2B is formed by CMP on the device surface having such a structure.

【0028】半導体ウェハ106を保持した保持部10
4(回転速度50rpm)を、研磨パッド103が貼付
された研磨定盤101(回転速度50rpm)に荷重2
00g重/cm2 で押圧する。それと同時に、スラリー
供給管107からスラリー108を研磨パッド103上
に、200ml/minの割合で滴下する。スラリー1
08には、メタル膜12がタングステンの時は、例えば
アルミナ分散液に硝酸第2鉄を8wt%程溶かしたもの
が使われる。このようにして、半導体ウェハ106と研
磨パッド103の間にスラリー108を介在させて、半
導体ウェハ106のデバイス面のCMPを行う。
Holding section 10 holding semiconductor wafer 106
4 (rotation speed: 50 rpm) is applied to the polishing platen 101 (rotation speed: 50 rpm) to which the polishing pad 103 is attached.
Press at 00 g weight / cm 2 . At the same time, a slurry 108 is dropped from the slurry supply pipe 107 onto the polishing pad 103 at a rate of 200 ml / min. Slurry 1
For example, when the metal film 12 is tungsten, a material obtained by dissolving about 8 wt% of ferric nitrate in an alumina dispersion liquid is used as 08. Thus, the CMP of the device surface of the semiconductor wafer 106 is performed with the slurry 108 interposed between the semiconductor wafer 106 and the polishing pad 103.

【0029】半導体ウェハ106のデバイス面の全面に
メタル膜12が付いているときは、2本の導電部109
間に電流が多く流れるが、メタル膜12が薄くなるにつ
れて抵抗が上昇するため、2本の導電部109間に流れ
る電流がしだいに減少する。そして、溝以外の領域のメ
タル膜12が完全に除去された時点以降は、電流値は低
いレベルで一定になる。よって、このような電流変化か
ら、研磨の終点検出が可能になる。
When the metal film 12 is provided on the entire device surface of the semiconductor wafer 106, the two conductive portions 109
Although a large amount of current flows between them, the resistance increases as the metal film 12 becomes thinner, so that the current flowing between the two conductive portions 109 gradually decreases. Then, after the metal film 12 in the region other than the groove is completely removed, the current value becomes constant at a low level. Therefore, the end point of polishing can be detected from such a current change.

【0030】図3は、本システムの等価回路である。導
電部109の抵抗をr、導電部109間における半導体
ウェハ106の表面抵抗をrw、導電部109間におけ
る研磨パッド103上のスラリーのイオン伝導に関わる
抵抗をriとする。抵抗rwと抵抗riは並列になり、こ
の並列部に対して直列に抵抗rが接続された形となる。
抵抗rwはCMPによってメタル膜厚が薄くなるにつれ
て抵抗値が増大する可変抵抗であり、1Ω程度から無限
大まで抵抗値が変化する。抵抗rは10Ω程度であり、
抵抗riは、スラリーの電解質の種類や濃度によって異
なるが、大雑把に100Ω程度である。
FIG. 3 is an equivalent circuit of the present system. The resistance of the conductive part 109 is denoted by r, the surface resistance of the semiconductor wafer 106 between the conductive parts 109 is denoted by r w , and the resistance between the conductive parts 109 related to the ion conduction of the slurry on the polishing pad 103 is denoted by r i . Resistance r w and the resistor r i becomes parallel, and form the resistor r is connected in series with the parallel portion.
The resistance r w is a variable resistance whose resistance increases as the metal film thickness is reduced by CMP, and the resistance changes from about 1Ω to infinity. The resistance r is about 10Ω,
The resistance r i varies depending on the type and concentration of the electrolyte in the slurry, but is roughly 100Ω.

【0031】図4は、上記システムにおける、研磨時間
に対する電流(実効値)の変化の様子を示したものであ
る。メタル膜の膜厚が一定の割合で減少する、すなわち
一定の研磨レートでメタル膜が研磨されるものとして、
計算を行った結果である。
FIG. 4 shows how the current (effective value) changes with polishing time in the above system. Assuming that the thickness of the metal film decreases at a constant rate, that is, the metal film is polished at a constant polishing rate,
This is the result of calculation.

【0032】電流が減少する領域と一定になる領域との
境tcが、余分なメタル膜がちょうど除去された時点に
なる。この計算では、面内均一性を理想的なものとし、
メタルがちょうど除去された時間は、ウェハのどの位置
でも同じであるとしている。また、メタル膜厚が薄くな
った時の薄膜効果、すなわち界面における電子散乱に起
因する抵抗増加は無視している。そのため、tc近傍で
の電流変化は、実際には計算とは異なり、クリティカル
ではない場合が一般的である。したがって、この点を考
慮して、ジャストと判断される時間に対して10%程度
長く余裕をもたせて研磨を終了させることが好ましい。
The current border t c of the region is constant and decreasing region, the time the extra metal film has just been removed. In this calculation, the in-plane uniformity is idealized,
The time at which the metal has just been removed is the same at any location on the wafer. Further, the thin film effect when the metal film thickness is reduced, that is, the increase in resistance due to electron scattering at the interface is ignored. Therefore, the current change in the vicinity of t c is generally not critical, unlike the calculation. Therefore, in consideration of this point, it is preferable to end the polishing with a margin of about 10% longer than the time determined to be just.

【0033】導電部109間に印加する電圧Vは、スラ
リーが電気分解を起こさないこと、電気分解に伴って半
導体ウェハ106上のメタル膜が腐食を起こさないこと
を考えると、観測が可能な範囲でなるべく小さい方が良
い。mVオーダー程度以下が適当である。また、上記理
由により、導電部109間に印加する電圧は高周波が望
ましく、10kHz程度が理想的である。
The voltage V applied between the conductive parts 109 is within an observable range considering that the slurry does not cause electrolysis and that the metal film on the semiconductor wafer 106 does not corrode with the electrolysis. It is better to be as small as possible. It is appropriate to use a voltage of about mV order or less. For the above reason, the voltage applied between the conductive portions 109 is preferably a high frequency, and ideally about 10 kHz.

【0034】研磨パッドの導電部109には、導電性物
質と合成樹脂を混合したものを用いるか、半導体の性質
を示す高分子化合物を用いる。前者は、熱可塑性樹脂ま
たは熱硬化性樹脂に、Au、Ag、Cu、Ni、カーボ
ンブラック、黒鉛などの導電性粉末、或いは箔、金属繊
維、炭素繊維などの導電性繊維を、多量に配合したもの
が相当する。
For the conductive portion 109 of the polishing pad, a mixture of a conductive material and a synthetic resin is used, or a polymer compound having semiconductor properties is used. The former is a thermoplastic resin or thermosetting resin, conductive powder such as Au, Ag, Cu, Ni, carbon black, graphite, or foil, metal fiber, conductive fiber such as carbon fiber, a large amount was blended Things are equivalent.

【0035】また、導電部109加工の仕方としては、
研磨パッドの導電部を設ける部分をリング状に切り出し
て導電部を埋め込む方法、或いは、研磨パッドの導電部
を設ける部分に選択的に導電性物質をドープする方法な
どが考えられる。多層研磨パッドの上層だけに導電部を
設ける場合も有り得る。
The method of processing the conductive portion 109 is as follows.
A method in which a portion where the conductive portion of the polishing pad is provided is cut out in a ring shape and the conductive portion is buried, or a method in which a portion where the conductive portion of the polishing pad is provided with a conductive material is selectively conceivable. There may be a case where the conductive portion is provided only on the upper layer of the multilayer polishing pad.

【0036】また、導電部109の材料に要求されるこ
とは、電気抵抗が十分小さいことと、研磨特性に影響を
与えないことである。研磨特性に影響を与えないように
するため、周囲の研磨パッドの材料と、弾性的、粘弾性
的性質が類似していることが好ましい。また、導電部と
導電部の周囲との間で段差が生じないように、研磨時や
ドレッシング時における目減りが両者間で同等になるよ
うにする。また、CMP後にウェハ汚染をもたらすよう
な成分が溶出しないような材料を選択する。さらに、研
磨時にスクラッチを発生させるような硬くて大きい粒子
を含まないようにすることは言うまでもない。
The material required for the conductive portion 109 is that the electric resistance is sufficiently small and that the polishing characteristics are not affected. In order not to affect the polishing characteristics, it is preferable that the material of the surrounding polishing pad is similar in elasticity and viscoelasticity. In addition, in order to prevent a step from occurring between the conductive portion and the periphery of the conductive portion, the reduction in polishing or dressing is made equal between the two. In addition, a material that does not elute components that cause wafer contamination after CMP is selected. Further, it is needless to say that hard and large particles that cause scratches during polishing are not included.

【0037】端子110の導電部109への接触の仕方
にも注意を要する。不十分な接触で接触抵抗が上がるの
は防ぐべきである。バネを介して押し当てる等の工夫が
必要であり、端子の形状も筆先のようにする等の工夫が
必要である。また、端子110は一般に、強酸化性、強
酸性或いは強アルカリ性のスラリーに接触することにな
るので、耐薬品性の材質を選択する。Pt等の化学的に
安全なメタルでコーティングするようにしてもよい。
Care must also be taken in how the terminal 110 contacts the conductive portion 109. Increased contact resistance due to insufficient contact should be prevented. A device such as pressing with a spring is required, and a device such as the shape of the terminal is required. In addition, since the terminal 110 generally comes into contact with a strongly oxidizing, strongly acidic or strongly alkaline slurry, a material having chemical resistance is selected. It may be coated with a chemically safe metal such as Pt.

【0038】(実施形態2)図5は本発明の第2の実施
形態に係る研磨装置の概略構成を模式的に示した図であ
り、図5(a)は同研磨装置を横から見た概略図、図5
(b)は同装置の主要部を上から見た概略図である。
(Embodiment 2) FIG. 5 is a view schematically showing a schematic configuration of a polishing apparatus according to a second embodiment of the present invention. FIG. 5 (a) shows the polishing apparatus viewed from the side. Schematic diagram, FIG.
(B) is the schematic which looked at the principal part of the apparatus from the top.

【0039】図5に示すように、研磨定盤201は、研
磨定盤回転軸202を中心に水平面内で矢印の方向に回
転するようになっており、その主表面上には研磨パッド
203が貼付されるようになっている。
As shown in FIG. 5, the polishing platen 201 rotates in a direction indicated by an arrow in a horizontal plane about a polishing platen rotating shaft 202, and a polishing pad 203 is provided on a main surface thereof. It is to be attached.

【0040】研磨定盤201の中心から偏心した位置の
上方には、半導体ウェハの保持部204が配置され、半
導体ウェハ保持部回転軸205を中心に、水平面内で研
磨定盤201と同方向に回転するようになっている。こ
の半導体ウェハ保持部204は、その下面において研磨
対象となる半導体ウェハ206を真空チャック等によっ
て保持するようになっている。そして、保持された半導
体ウェハ206の被研磨面が研磨パッド203の研磨面
と接触するように、シリンダなどの駆動機構によって一
定の圧力で押圧されるようになっている。
Above a position eccentric from the center of the polishing platen 201, a holding portion 204 for the semiconductor wafer is disposed, and the semiconductor wafer holding portion rotating shaft 205 is centered in the same direction as the polishing platen 201 in a horizontal plane. It is designed to rotate. The semiconductor wafer holding section 204 holds a semiconductor wafer 206 to be polished on its lower surface by a vacuum chuck or the like. Then, a driving mechanism such as a cylinder is pressed with a constant pressure so that the polished surface of the held semiconductor wafer 206 comes into contact with the polished surface of the polishing pad 203.

【0041】研磨定盤201の中心部の上方には、スラ
リー供給管207が配置され、このスラリー供給管20
7から研磨パッド203上にスラリー208が供給され
るようになっている。
A slurry supply pipe 207 is disposed above the center of the polishing platen 201.
7, the slurry 208 is supplied onto the polishing pad 203.

【0042】研磨パッド203には、円柱状の二つの研
磨パッド導電部209が互いに離間して研磨パッド本体
(絶縁物)内に埋め込まれており、研磨時に半導体ウェ
ハ206の表面が二つの導電部209に接触するよう
に、二つの導電部209間の距離は設定されている。
In the polishing pad 203, two columnar polishing pad conductive portions 209 are embedded in the polishing pad body (insulator) at a distance from each other, and the surface of the semiconductor wafer 206 is polished during polishing. The distance between the two conductive parts 209 is set so as to contact the conductive parts 209.

【0043】この二つの導電部209は、研磨定盤20
1中に設けられた導電柱212に電気的に接続されてい
る。この導電柱212には、研磨定盤201の裏側で導
線214が電気的に接続している。この導線214は、
研磨定盤回転軸202の周囲に設けられた回転端子21
5に電気的に接続するようになっており、この回転端子
215には端子210を介して電流モニター211から
高周波電圧が印加される。電流モニター211は、導電
部209間に流れる電流をモニターし、そのモニター結
果に基づいてCMP動作を制御できるようになってい
る。なお、研磨定盤201が導体である場合には、導電
柱212の周囲に絶縁管213を設ける必要がある。ま
た、研磨定盤回転軸202が導体である場合には、回転
端子215との間に絶縁物を設けるようにする。
The two conductive portions 209 are provided on the polishing platen 20.
1 are electrically connected to the conductive columns 212 provided therein. A conductive wire 214 is electrically connected to the conductive column 212 on the back side of the polishing platen 201. This conductor 214
Rotary terminal 21 provided around polishing platen rotary shaft 202
5, and a high-frequency voltage is applied to the rotating terminal 215 from the current monitor 211 via the terminal 210. The current monitor 211 monitors the current flowing between the conductive units 209, and can control the CMP operation based on the monitoring result. When the polishing table 201 is a conductor, it is necessary to provide an insulating tube 213 around the conductive column 212. When the polishing platen rotating shaft 202 is a conductor, an insulator is provided between the rotating plate 202 and the rotating terminal 215.

【0044】なお、導電部209間に印加する電圧、導
電部209の材質や加工法に関しては、実施形態1と同
様である。
The voltage applied between the conductive portions 209, the material of the conductive portion 209, and the processing method are the same as in the first embodiment.

【0045】第1の実施形態と同様、図2(a)に示し
たような基板に対して、第1の実施形態で示した条件と
同様な条件でCMPを行い、図2(b)に示すようなダ
マシン配線を形成するものとする。
As in the first embodiment, CMP is performed on the substrate as shown in FIG. 2A under the same conditions as those in the first embodiment, and FIG. It is assumed that a damascene wiring as shown is formed.

【0046】研磨中に研磨定盤201が回転し、半導体
ウェハ206と二つの導電部209とが電気的に接触す
る時間帯Aにおいては、半導体ウェハ206の表面の電
気伝導と、半導体ウェハ206と研磨パッド203の間
に介在するスラリーのイオン伝導が反映される。一方、
半導体ウェハ206と二つの導電部209とが電気的に
接触しない時間帯Bにおいては、研磨パッド203上の
スラリーのイオン伝導のみが反映される。
In a time zone A during which the polishing platen 201 rotates during polishing and the semiconductor wafer 206 and the two conductive portions 209 are in electrical contact, the electric conduction on the surface of the semiconductor wafer 206 and the semiconductor wafer 206 The ion conduction of the slurry interposed between the polishing pads 203 is reflected. on the other hand,
In the time zone B in which the semiconductor wafer 206 and the two conductive portions 209 are not in electrical contact, only the ion conduction of the slurry on the polishing pad 203 is reflected.

【0047】時間帯Aにおいて、デバイス面の表面全体
にメタル膜12が存在しているときは、二つの導電部2
09間に電流が多く流れるが、メタル膜12が薄くなる
につれて抵抗が上昇するため、二つの導電部209間に
流れる電流がしだいに減少する。そして、溝以外の領域
のメタル膜12が完全に除去された時点以降は、電流値
はスラリーのイオン伝導のみの低いレベルで一定にな
る。また、時間帯Bにおいては、デバイス面のメタル膜
12の膜厚とは無関係に、電流値はスラリーのイオン伝
導のみの低いレベルで一定になる。
In the time zone A, when the metal film 12 is present on the entire device surface, the two conductive portions 2
Although a large amount of current flows between the two conductive portions 209, the current flowing between the two conductive portions 209 gradually decreases because the resistance increases as the metal film 12 becomes thinner. After the metal film 12 in the region other than the groove is completely removed, the current value is constant at a low level of only the ionic conduction of the slurry. In the time zone B, the current value is constant at a low level of only the ionic conduction of the slurry, regardless of the thickness of the metal film 12 on the device surface.

【0048】したがって、本例における電流(実効値)
変化はパルス状(時間帯Aで出現する)になる。このパ
ルスの周期は、研磨定盤201の回転数が50rpmで
あるため、1.2secである。そして、このパルスの
高さは徐々に低くなる。パルス状にはなるものの、基本
的な電流変化は図4と同等であり、第1の実施形態と同
様に研磨の終点検出が可能になる。
Therefore, the current (effective value) in this example
The change becomes pulse-like (appears in time zone A). The period of this pulse is 1.2 sec because the rotation speed of the polishing platen 201 is 50 rpm. Then, the height of this pulse gradually decreases. Although it becomes pulse-shaped, the basic current change is the same as in FIG. 4, and the end point of polishing can be detected as in the first embodiment.

【0049】なお、導電部209と導電柱212とのコ
ンタクト抵抗は小さいことが好ましいが、ある程度以上
の高周波を印加する場合には、多少のギャップによりコ
ンデンサ容量が介在してもよい。この点を留意すると、
研磨パッド203に導電部209を設けない構成も実現
可能である。
It is preferable that the contact resistance between the conductive portion 209 and the conductive column 212 is small. However, when a high frequency of a certain level or more is applied, a capacitor may be interposed by a slight gap. With this in mind,
A configuration in which the conductive portion 209 is not provided on the polishing pad 203 is also feasible.

【0050】図6は、このような構成を有する研磨装置
の概略構成を模式的に示した図であり、図5に示した構
成要素と対応する構成要素については同一の参照番号を
付している。
FIG. 6 is a diagram schematically showing a schematic configuration of a polishing apparatus having such a configuration. Components corresponding to the components shown in FIG. 5 are denoted by the same reference numerals. I have.

【0051】図6に示した構成では、導電柱212の上
部を研磨定盤201の上面から突出させて突出部212
aとし、研磨パッド203にはこの突出部212aに対
応した穴を設けている。この穴に突出部212aを通
し、研磨パッド203を研磨定盤201上に貼付ける。
突出部212aの上面の高さは研磨パッド203の上面
より僅かに低い程度であり、導電柱212の上面(突出
部212aの上面)がスラリーで腐食されるのを防ぐ目
的で、導電柱212の上面を薄い絶縁板221で覆うよ
うにしている。この絶縁板221には、誘電率が大きい
ものを用いるようにする。なお、この絶縁板221を、
研磨パッド203側に設けるようにしてもよい。
In the structure shown in FIG. 6, the upper part of the conductive column 212 is projected from the upper surface of the polishing
The polishing pad 203 is provided with a hole corresponding to the protrusion 212a. The polishing pad 203 is adhered on the polishing platen 201 through the protrusion 212 a through the hole.
The height of the upper surface of the projecting portion 212a is slightly lower than the upper surface of the polishing pad 203, and the upper surface of the conductive column 212 (the upper surface of the projecting portion 212a) is prevented from being corroded by the slurry. The upper surface is covered with a thin insulating plate 221. The insulating plate 221 having a large dielectric constant is used. In addition, this insulating plate 221 is
It may be provided on the polishing pad 203 side.

【0052】このように、図6に示した構成によれば、
研磨パッドに導電部を設けず、導電柱が通る穴を設ける
だけでよいので、研磨パッドを低コストで生産できると
いうメリットがある。
As described above, according to the configuration shown in FIG.
Since it is only necessary to provide a hole through which the conductive column passes without providing the conductive portion on the polishing pad, there is an advantage that the polishing pad can be produced at low cost.

【0053】なお、上述した各例ではCMPについて説
明したが、砥石を用いる研削に対しても本発明は同様に
適応可能である。砥石を用いた場合も、基本的には図1
〜図6で説明したようなCMPの各例と同様の構成をと
ることが可能であり、例えば図7に示したような構成を
とることができる。図7に示した例では、砥石231に
よって研磨定盤を構成し、砥石231の上面を研磨面と
し、砥石231内に導電柱232を設けている。図6に
示した例と同様、導電柱232の上面を薄い絶縁板で覆
うようにしてもよい。
In each of the examples described above, CMP has been described. However, the present invention is similarly applicable to grinding using a grindstone. When using a whetstone, basically
It is possible to take a configuration similar to each example of the CMP described in FIG. 6 to FIG. 6, for example, a configuration as shown in FIG. In the example illustrated in FIG. 7, a polishing platen is configured by the grindstone 231, and the upper surface of the grindstone 231 is used as a polishing surface, and the conductive pillar 232 is provided in the grindstone 231. As in the example shown in FIG. 6, the upper surface of the conductive column 232 may be covered with a thin insulating plate.

【0054】なお、上述した第1及び第2の実施形態で
は、導電部(研磨パッドの導電部、導電柱)を二つ設け
るようにしたが、導電部の数をさらに増やして半導体ウ
ェハの表面に多数接触するようにすれば、ウェハの中心
と周辺の削れ具合、すなわちCMPの面内均一性もモニ
ターすることが可能になる。
In the first and second embodiments described above, two conductive portions (conductive portions and conductive columns of the polishing pad) are provided. However, the number of conductive portions is further increased to increase the surface of the semiconductor wafer. When a large number of contacts are made, the degree of scraping of the center and the periphery of the wafer, that is, the in-plane uniformity of the CMP can be monitored.

【0055】以上、本発明の実施形態を説明したが、本
発明は上記実施形態に限定されるものではなく、その趣
旨を逸脱しない範囲内において種々変形して実施するこ
とが可能である。
Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and can be variously modified and implemented without departing from the gist of the present invention.

【0056】[0056]

【発明の効果】本発明によれば、被処理基板の被研磨面
の導電状態を複数の導電部を介して検出することによ
り、簡便な方法によって研磨の終点検出を容易かつ確実
に行うことが可能となる。
According to the present invention, the end point of polishing can be easily and reliably detected by a simple method by detecting the conductive state of the surface to be polished of the substrate to be processed through a plurality of conductive portions. It becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態に係る研磨装置の概略
構成を模式的に示した図。
FIG. 1 is a diagram schematically showing a schematic configuration of a polishing apparatus according to a first embodiment of the present invention.

【図2】本発明に係る研磨装置を用いた研磨処理の一例
を示した図。
FIG. 2 is a view showing an example of a polishing process using the polishing apparatus according to the present invention.

【図3】本発明に係る研磨装置の主要部における等価回
路を示した図。
FIG. 3 is a diagram showing an equivalent circuit in a main part of the polishing apparatus according to the present invention.

【図4】本発明に係る研磨装置によって研磨を行ったと
きの研磨時間に対する電流変化を示した図。
FIG. 4 is a diagram showing a change in current with respect to a polishing time when polishing is performed by the polishing apparatus according to the present invention.

【図5】本発明の第2の実施形態に係る研磨装置の一例
についてその概略構成を模式的に示した図。
FIG. 5 is a diagram schematically showing a schematic configuration of an example of a polishing apparatus according to a second embodiment of the present invention.

【図6】本発明の第2の実施形態に係る研磨装置の他の
例についてその概略構成を模式的に示した図。
FIG. 6 is a diagram schematically showing a schematic configuration of another example of the polishing apparatus according to the second embodiment of the present invention.

【図7】本発明の第3の実施形態に係る研磨装置の他の
例についてその概略構成を模式的に示した図。
FIG. 7 is a diagram schematically showing a schematic configuration of another example of the polishing apparatus according to the third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11…シリコン酸化膜 12…メタル膜 101、201…研磨定盤 102、202…回転軸 103、203…研磨パッド 104、204…保持部 105、205…回転軸 106、206…半導体ウェハ 107、207…スラリー供給管 108、208…スラリー 109、209…研磨パッド導電部 110、210…端子 111、211…電流モニター 212、232…導電柱 212a…突出部 213…絶縁管 214…導線 215…回転端子 221…絶縁板 231…砥石 DESCRIPTION OF SYMBOLS 11 ... Silicon oxide film 12 ... Metal film 101, 201 ... Polishing surface plate 102, 202 ... Rotation axis 103, 203 ... Polishing pad 104, 204 ... Holder 105, 205 ... Rotation axis 106, 206 ... Semiconductor wafer 107, 207 ... Slurry supply pipes 108, 208 Slurries 109, 209 Polishing pad conductive parts 110, 210 Terminals 111, 211 Current monitors 212, 232 Conductive pillars 212a Projecting parts 213 Insulating pipes 214 Conductive wires 215 Rotating terminals 221 Insulating plate 231 ... Whetstone

Claims (13)

【特許請求の範囲】[Claims] 【請求項1】被処理基板表面の研磨に用いる研磨パッド
であって、面方向で互いに離間した複数の導電部を有す
ることを特徴とする研磨パッド。
1. A polishing pad used for polishing a surface of a substrate to be processed, comprising: a plurality of conductive portions which are separated from each other in a plane direction.
【請求項2】前記複数の導電部は、同心円状に配置され
ていることを特徴とする請求項1に記載の研磨パッド。
2. The polishing pad according to claim 1, wherein the plurality of conductive portions are arranged concentrically.
【請求項3】前記複数の導電部は、散点状に配置されて
いることを特徴とする請求項1に記載の研磨パッド。
3. The polishing pad according to claim 1, wherein the plurality of conductive portions are arranged in a scattered manner.
【請求項4】前記複数の導電部は、導電性高分子樹脂を
用いて形成されていることを特徴とする請求項1に記載
の研磨パッド。
4. The polishing pad according to claim 1, wherein the plurality of conductive portions are formed using a conductive polymer resin.
【請求項5】請求項1乃至4のいずれかに記載の研磨パ
ッドが装着される研磨盤と、 被処理基板を保持して被処理基板の被研磨面を前記研磨
パッドが装着された研磨盤に対向させる保持部と、 前記研磨盤と前記保持部とを相対的に動かす駆動部と、 前記保持部に保持された被処理基板の被研磨面の導電状
態を前記研磨パッドが有する複数の導電部を介して検出
する検出部と、 を有することを特徴とする研磨装置。
5. A polishing disk on which the polishing pad according to claim 1 is mounted, and a polishing disk holding a substrate to be processed and a polishing surface of the substrate to be polished mounted with the polishing pad. A driving unit that relatively moves the polishing plate and the holding unit; and a plurality of conductive members that the polishing pad has to determine the conductive state of the surface to be polished of the substrate to be processed held by the holding unit. A polishing apparatus, comprising: a detection unit that detects through a unit.
【請求項6】前記検出部は、前記複数の導電部間に高周
波電圧を印加することにより、被処理基板の被研磨面の
導電状態を検出するものであることを特徴とする請求項
5に記載の研磨装置。
6. The apparatus according to claim 5, wherein said detecting section detects a conductive state of a polished surface of a substrate to be processed by applying a high frequency voltage between said plurality of conductive sections. The polishing apparatus according to the above.
【請求項7】請求項5又は6に記載の研磨装置を用いた
研磨方法であって、 前記保持部に保持された被処理基板を前記研磨盤に装着
された前記研磨パッドによって研磨し、前記保持部に保
持された被処理基板の被研磨面の導電状態を前記研磨パ
ッドが有する複数の導電部を介して前記検出部によって
検出することを特徴とする研磨方法。
7. A polishing method using the polishing apparatus according to claim 5 or 6, wherein the substrate to be processed held by the holding portion is polished by the polishing pad mounted on the polishing board. A polishing method, wherein the detection unit detects a conductive state of a surface to be polished of a substrate to be processed held by a holding unit via a plurality of conductive units of the polishing pad.
【請求項8】面方向で互いに離間した複数の導電部を有
し、該複数の導電部の先端部が研磨パッドが装着される
面から突出した突出部となっており、前記複数の導電部
の突出部に対応した複数の穴が設けられた研磨パッドが
装着される研磨盤と、 被処理基板を保持して被処理基板の被研磨面を前記研磨
パッドが装着された研磨盤に対向させる保持部と、 前記研磨盤と前記保持部とを相対的に動かす駆動部と、 前記保持部に保持された被処理基板の被研磨面の導電状
態を前記複数の導電部を介して検出する検出部と、 を有することを特徴とする研磨装置。
8. A plurality of conductive portions having a plurality of conductive portions which are separated from each other in a plane direction, and tips of the plurality of conductive portions project from a surface on which a polishing pad is mounted. A polishing pad on which a polishing pad provided with a plurality of holes corresponding to the projections of the polishing pad is mounted, and a substrate to be processed is held and the surface to be polished of the substrate is opposed to the polishing pad on which the polishing pad is mounted. A holding unit, a driving unit that relatively moves the polishing board and the holding unit, and a detection that detects a conductive state of a polished surface of the substrate to be processed held by the holding unit via the plurality of conductive units. A polishing apparatus comprising: a unit;
【請求項9】前記検出部は、前記複数の導電部間に高周
波電圧を印加することにより、被処理基板の被研磨面の
導電状態を検出するものであることを特徴とする請求項
8に記載の研磨装置。
9. The apparatus according to claim 8, wherein said detecting section detects a conductive state of a polished surface of a substrate to be processed by applying a high frequency voltage between said plurality of conductive sections. The polishing apparatus according to the above.
【請求項10】請求項8又は9に記載の研磨装置を用い
た研磨方法であって、 前記保持部に保持された被処理基板を前記研磨盤に装着
された前記研磨パッドによって研磨し、前記保持部に保
持された被処理基板の被研磨面の導電状態を前記複数の
導電部を介して前記検出部によって検出することを特徴
とする研磨方法。
10. A polishing method using the polishing apparatus according to claim 8 or 9, wherein the substrate to be processed held by the holding section is polished by the polishing pad mounted on the polishing board. A polishing method, comprising: detecting a conductive state of a surface to be polished of a substrate to be polished held by a holding unit by the detection unit via the plurality of conductive units.
【請求項11】面方向で互いに離間した複数の導電部を
有し、表面が研磨面となっている研磨盤と、 被処理基板を保持して被処理基板の被研磨面を前記研磨
盤の研磨面に対向させる保持部と、 前記研磨盤と前記保持部とを相対的に動かす駆動部と、 前記保持部に保持された被処理基板の被研磨面の導電状
態を前記複数の導電部を介して検出する検出部と、 を有することを特徴とする研磨装置。
11. A polishing plate having a plurality of conductive portions spaced apart from each other in a plane direction and having a polished surface, and a polished surface of the polished disk holding a substrate to be processed and a polished surface of the substrate. A holding unit opposed to a polishing surface, a driving unit for relatively moving the polishing board and the holding unit, and a conductive state of the surface to be polished of the substrate to be processed held by the holding unit, the plurality of conductive units A polishing apparatus, comprising: a detection unit that detects the electric current through the polishing apparatus.
【請求項12】前記検出部は、前記複数の導電部間に高
周波電圧を印加することにより、被処理基板の被研磨面
の導電状態を検出するものであることを特徴とする請求
項11に記載の研磨装置。
12. The apparatus according to claim 11, wherein said detecting section detects a conductive state of a polished surface of a substrate to be processed by applying a high frequency voltage between said plurality of conductive sections. The polishing apparatus according to the above.
【請求項13】請求項11又は12に記載の研磨装置を
用いた研磨方法であって、 前記保持部に保持された被処理基板を前記研磨盤の研磨
面によって研磨し、前記保持部に保持された被処理基板
の被研磨面の導電状態を前記複数の導電部を介して前記
検出部によって検出することを特徴とする研磨方法。
13. A polishing method using the polishing apparatus according to claim 11, wherein the substrate to be processed held by said holding portion is polished by a polishing surface of said polishing board, and held by said holding portion. A polishing method, wherein the detecting unit detects the conductive state of the polished surface of the substrate to be processed via the plurality of conductive units.
JP2000086382A 2000-03-27 2000-03-27 Polishing pad, polishing device, and polishing method Pending JP2001269862A (en)

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