JP2001267894A - Voltage comparison circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a voltage comparison output resulting from the comparison of a threshold voltage with an input signal voltage without a spike. SOLUTION: The circuit is constituted of (a) a first voltage output circuit having the first series negative resistance element circuits of first and second negative resistance element circuits and a field effect transistor whose drain is connected to the connection middle point of the first and second negative resistance element circuits and whose source to a power terminal, in which a clock signal voltage is applied between both ends and an input signal voltage is applied to the gate of the field effect transistor, (b) a second voltage output circuit which has the second series negative resistance element circuit of third and fourth negative resistance element circuits and in which the clock signal voltage is applied between both ends (c) a differential circuit outputting a differential voltage between output from the connection middle point of the first and second negative resistance element circuits and output from the connection middle point of the third and fourth negative resistance element circuit. A voltage comparison output resulting from the comparison of a scheduled threshold voltage with an input signal voltage is outputted from the differential circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a voltage comparison circuit for comparing an input signal voltage with a predetermined threshold voltage and outputting the result as a voltage comparison output.

[0002]

2. Description of the Related Art A voltage comparison circuit described below with reference to FIG. 7 has been proposed (reference: K. Maezawa).
and T. Mizutani, “A New Re
sonant Tunneling Logic Ga
te Employing Monostable-B
isable Transition, "Jpn.
J. Appl. Phys. vol. 32, pp. 42-
44, 1993). That is, a first negative resistance element circuit B1 having one two-terminal negative resistance element D1 and a second negative resistance element circuit B2 also having one two-terminal negative resistance element D2 are connected in series. And a drain connected to the first negative terminal of the series negative resistance element circuit G.
Connection point P between the second negative resistance element circuits B1 and B2
And a field-effect transistor M having a source connected to one end of the series negative resistance element circuit G on the side of the negative resistance element circuit B2.

[0003] One end of the negative resistance element circuit B1 side of the series negative resistance element circuit G has been implicated as a "0" correlated obtained binary display meanings at a low voltage V _L at a high voltage V _H It is connected to a clock signal voltage source terminal Ec that outputs a clock signal voltage Vc that repeats alternately taking binary display “1” sequentially, and the other of the series negative resistance element circuit G on the negative resistance element circuit B2 side The end is a constant voltage source end E1 that outputs a constant voltage V1.
, Whereby the clock signal voltage Vc is applied across the series negative resistance element circuit G.

A gate of the field effect transistor M is connected to a signal input terminal IN from which an input signal voltage Vi is obtained, and a connection midpoint between the negative resistance element circuits B1 and B2 of the series negative resistance element circuit G. An output terminal OUT is derived from P.

In this case, the two-terminal negative resistance element D1 of the negative resistance element circuit B1 and the two-terminal negative resistance element D2 of the negative resistance element circuit B2 have an N-shaped current as shown in FIG. -It has voltage characteristics. That is, by increasing the current from zero value in a positive direction, but the voltage is a voltage value higher in the positive direction from zero value in response thereto, the current is the peak current value I _P
Once you reach the voltage is transferred to the higher voltage value V _q than the voltage value V _p to it at that time, also, by increasing the current from that state, a positive voltage from the voltage value V _q accordingly becomes a voltage value that is higher in the direction, further, if reducing the current from that state, becomes a voltage value the voltage drops in the negative direction accordingly, if reached its current to valley current value I _r, voltage There was transferred to a low voltage value V _s than the voltage value V _r to it at that time, also, the voltage when caused to decrease the current from that state, decreases from the voltage value at that time is a voltage in the negative direction accordingly Value.

Accordingly, the peak current value I _P seen from the current-voltage characteristics of the two-terminal negative resistance element D1 is defined as I _P1 ,
The voltage values V _P , V _q , V _r, and V _s are represented by V _P1 ,
And V _q1, V _r1 and V _s1, when the current value I _r and I _r1, negative resistance element circuit B1 only with a two-terminal negative-resistance elements D1, it is as shown in FIG. 9, the current -It has voltage characteristics.

The peak current value I _P seen from the current-voltage characteristics of the two-terminal negative resistance element D 2 is defined as I _P2 , and the voltage value V
_P, V _q, the V _r and V _s and V _P2, V _q2, V _r2 and V _s2, respectively, when the current value I _r and I _r2, negative only has two terminals and the negative resistance element D2 which The resistive element circuit B2 has a current-voltage characteristic as shown in FIG. However, in this case, the peak current value I _P2 is smaller than the peak current value I _{P1 of} the two-terminal negative resistance element D1 (I _P1
> _IP2 ).

Further, the field effect transistor M is, for example, an n-type. In this case, the field effect transistor M
Passes through the midpoint P between the connection of the negative resistance element circuits B1 and B2 and the constant voltage source terminal E1, and changes the drain current as the input signal voltage Vi applied to the gate increases in the positive direction. Has the property of increasing

When a parallel circuit of the negative resistance element circuit B2 and the field-effect transistor M is used as a composite circuit C, the composite circuit C includes a connection point P between the negative resistance element circuits B1 and B2 and a constant voltage. It has a characteristic of flowing a current that is the sum of the current flowing through the two-terminal negative resistance element D2 and the drain current of the field-effect transistor M through the source terminal E1.

Accordingly, the composite circuit C corresponds to the peak current value I _P2 , the voltage values V _P2 , V _q2 , V _r2 and V _s2 , and the current value I _r2 as seen from the current-voltage characteristics of the two-terminal negative resistance element D2. _Are respectively set to the peak current value I _P2 ′, the voltage value V _P2 ′,
When V _q2 ′, V _r2 ′ and V _s2 ′, and a current value I _r2 ′,
As shown in FIG. 11, the peak current I depends on the input signal voltage Vi applied to the gate of the field effect transistor M.
_It has an N-shaped current-voltage characteristic in which _p2 'changes.

The above is the configuration of the conventionally proposed voltage comparison circuit. According to the conventional voltage comparison circuit having such a configuration, the input signal voltage V
The i is compared with a threshold voltage of the plan (referred to as V _T), and outputs the result as a voltage comparison output. Here, the threshold voltage V _T is the peak current value I _P1 of the two-terminal negative resistance element D1.
And the peak value I _{P2 of the} two-terminal negative resistance element D2 is equal to the input signal voltage Vi (I _P1 = I _P2 ).

[0012] First, the case where the input signal voltage Vi is lower than the threshold voltage _{V T (Vi <V T)} . In this case, the peak current value I _p2 ′ of the composite circuit C is
1 is smaller than the peak current value I _p1 (I _p2 ′ <I _p1 ).
Therefore, the clock signal voltage Vc low voltage is implicated in "0" binary display of taking the value V _L and a high voltage V _H which is implicated in the "1" in the binary display at an appropriate value If selected, the clock signal voltage V is applied to the output terminal OUT.
Depending on whether c takes "0" or "1" in binary display, an output voltage having "0" or "1" in binary display is obtained. This situation will be described in detail below. I do.

[0013] conventional voltage comparator circuit shown in FIG. 7 has, by using the clock signal voltage Vc, the input signal voltage Vi, the comparison voltage comparison output and the threshold voltage V _T, the function of outputting to the output terminal OUT Is the clock signal voltage Vc, the current time is t, and the sequential time points are t1, t2, t3, t4,
At times t5, t6, and t7, as shown in FIGS. 13 and 15, from time t1 to time t3 (t1 <t <t
3), it takes the higher becomes the voltage value with time from a low voltage value V _L to a high voltage V _H, in the following, during the period from time point t3 to time point t4 (t3 <t <t4) , keeping the high voltage V _H From the time point t4 to the time point t6 (t4 <t <t6), a voltage value that decreases with time from the high voltage value _VH to the low voltage value _VL is taken, and from the time point t6 to the time point t7 (t6 <t6). <
t7) It is assumed that the low voltage value _VL is maintained and the same is repeated hereafter.

On the other hand, the negative resistance element circuit B1 functions as a load circuit of the composite circuit C. For this reason, as shown in FIG. 12, the current-voltage characteristic shown in FIG. 9 of the negative resistance element circuit B1 is shown on the graph showing the current-voltage characteristic shown in FIG. Can be written as a load line H1 as shown by a dotted line, intersecting with a curve H2 representing the current-voltage characteristic of the composite circuit C.

Therefore, the peak current value I _p2 ′ of the composite circuit C
Is smaller than the peak current value I _p1 of the negative resistance element circuit B1 (I _P2 ′ <I _P1 ), the output voltage obtained at the output terminal OUT is obtained by taking the following voltage value. .

[0016] That is, during the period from time t1 to time t2 (t1 <t <t2) , the intersection point Q of the load lines H1 to intersect the curve H2 is, as shown in FIG. 12A, the voltage from the position of the voltage value V _L2 ' Moving over time towards the position of value V _P2 ′,
Therefore, the output voltage obtained at the output terminal OUT is as shown in FIG.
As shown in FIG. 7, the voltage value increases with time from the voltage value V _L2 ′ toward the voltage value V _P2 ′.

When the time t2 is reached (t = t2),
As shown in FIG. 12B, the intersection Q shifts from the position of the voltage value V _P2 ′ to the position of the voltage value V _A1 , and thus the output terminal OUT
As shown in FIG. 13B, the output voltage obtained in the step (b) changes from the voltage value V _P2 ′ to the voltage value V _A1 .

Further, between the time point t2 and the time point t3 (t2 <t <t3), as shown in FIG. 12C, the intersection point Q is moved from the position of the voltage value V _{A1 to} the position of the voltage value V _H2 ′ with time. As a result, the output voltage obtained at the output terminal OUT takes a voltage value that increases from the voltage value V _A1 to the voltage value V _H2 ′ as shown in FIG. 13B.

Further, from the time point t3 to the time point t4 (t3 <t <t4), the intersection point Q does not move, so that the output voltage obtained at the output terminal OUT maintains the voltage value V _H2 ′.

Between the time point t4 and the time point t5 (t4 <t <t5), the intersection Q moves from the position of the voltage value V _H2 ′ to the position of the voltage value V _A2 , so that the output terminal As shown in FIG. 13B, the output voltage obtained at OUT takes a voltage value that decreases with time from the voltage value V _H2 ′ toward the voltage value A _A2 .

When the time t5 is reached (t = t
5) As shown in FIG. 12D, the intersection Q shifts from the position of the voltage value _{VA2 to} the position of the voltage value _VA3 , and thus the output terminal O
Output voltage obtained at the UT, as shown in FIG. 13B, transitions from voltage V _A2 to the voltage value V _A3.

Between the time point t5 and the time point t6 (t5 <t <t6), as shown in FIG. 12E, the intersection Q moves from the position of the voltage value V _{A3 to} the position of the voltage value V _L2 ′ with time. As a result, the output voltage obtained at the output terminal OUT takes a voltage value that decreases from the voltage value _VA3 to the voltage value _VL2 ', as shown in FIG. 13B.

Further, after time t6, (t6 <t <
t7) The intersection Q does not move, so that the output voltage obtained at the output terminal OUT has the voltage value V _L2 ′ as shown in FIG. 13B.
Keep.

From the above, in the case of the conventional voltage comparison circuit shown in FIG. 7, the input signal voltage Vi changes from the voltage value lower than the threshold voltage V _T to the threshold voltage V _{T as} shown in FIG.
To a higher voltage value than _T, when taking the voltage value increases with time, the input signal voltage Vi voltage value lower than the threshold voltage V _T (Vi <V _T) at which period, the clock signal voltage Vc, Fig. As shown in FIG. 16B, the output voltage that takes on “0” or “1” in binary display depends on whether it takes “0” or “1” in binary display.
Then, as shown in FIG. 16C, it is obtained by taking the voltage values described above with reference to FIGS.

Next, the case where the input signal voltage Vi is higher than the threshold voltage V _T (Vi> V _T ) will be described. In this case, the peak current value I _p2 ′ of the composite circuit C is
1 is larger than the peak current value I _p1 . For this reason, it will be described in detail in [Problems to be Solved by the Invention],
At the output terminal OUT, an output voltage that takes only binary display “0” is obtained regardless of whether the clock signal voltage Vc takes binary display “0” or “1”.

As described above, according to the conventional voltage comparison circuit shown in FIG. 7, when the input signal voltage Vi has a voltage value lower than the threshold voltage V _T (Vi> V _T ), the clock signal voltage Vc becomes An output voltage that takes on a binary display “0” or “1” is obtained at the output terminal OUT depending on whether the binary display takes “0” or “1”, and the input signal voltage Vi
Has a voltage value higher than the threshold voltage V _T (Vi>
V _T ), an output voltage that takes a binary value “0” is obtained at the output terminal OUT regardless of whether the clock signal voltage Vc takes a binary value “0” or “1”. function of outputting a comparison voltage comparison output and the threshold voltage V _T of the input signal voltage Vi is obtained.

[0027]

In the conventional voltage comparison circuit shown in FIG. 7, the input signal voltage Vi is higher than the threshold voltage V _T (Vi> V _T ), and the peak current I
_p2 'is greater than the peak current value I _p1 of the negative resistance element circuit _{B1 (I p2'> I p1} ) case, the output voltage obtained at the output terminal OUT is obtained by taking the described below voltage value .

That is, from the time point t1 to the time point t2 (t1 <t <t2), the intersection Q where the load line H1 intersects the curve H2 is, as shown in FIG. 14A, the voltage from the position of the voltage value V _L2 ′. The voltage that moves with time toward the position of the value V _B1 , so that the output voltage obtained at the output terminal OUT increases with time from the voltage value V _L2 ′ toward the voltage value V _B1 as shown in FIG. 15B. Take a value.

When time t2 is reached (t = t2),
The intersection Q shifts from the position of the voltage value V _{B1 to} the position of the voltage value V _B2 as shown in FIG. 14B, so that the output voltage obtained at the output terminal OUT becomes the voltage value V V as shown in FIG.
_The voltage transitions from _B1 to the voltage value _VB2 .

Further, between the time point t2 and the time point t3 (t2 <t <t3), the intersection Q moves from the position of the voltage value V _{B2 to} the position of the voltage value V _B3 with time as shown in FIG. 14C. Therefore, as shown in FIG. 15B, the output voltage obtained at the output terminal OUT takes a voltage value that increases from the voltage value V _B2 to the voltage value V _B3 .

Further, between the time point t3 and the time point t4 (t3 <t <t4), the intersection point Q does not move, so that the output voltage obtained at the output terminal OUT maintains the voltage value V _B3 .

In addition, from time t4 to time t5 (t
4 <t <t5), the intersection point Q moves from the position of the voltage value V _B3 toward the position of the voltage value V _B4 , so that the output voltage obtained at the output terminal OUT becomes the voltage as shown in FIG. Value V
_The voltage value decreases with time from _B3 toward the voltage value _VB4 .

Further, when time t5 is reached (t = t
5) As shown in FIG. 14D, the intersection Q shifts from the position of the voltage value V _{B4 to} the position of the voltage value V _B5 , so that the output terminal O
The output voltage obtained at the UT transitions from the voltage value V _B4 to the voltage value V _B5 as shown in FIG. 15B.

Also, between time t5 and time t6 (t
At 5 <t <t6), the intersection Q moves with time from the position of the voltage value V _{B5 to} the position of the voltage value V _L2 ′ as shown in FIG. 14E, so that the output voltage obtained at the output terminal OUT becomes 15B, the voltage value decreases from the voltage value V _B5 to the voltage value V _H2 ′.

Further, after time t6, (t6 <t <
t7) The intersection Q does not move, and thus the output voltage obtained at the output terminal OUT becomes the voltage value V _L2 ′ as shown in FIG. 15B.
Keep.

From the above, in the case of the conventional voltage comparison circuit shown in FIG. 7, the input signal voltage Vi has a voltage value higher than the threshold voltage V _T (Vi> V _T ) as shown in FIG. 16A. In the section, the clock signal voltage Vc is
As shown in FIG. 16C, an output voltage that takes only binary display “0” regardless of whether it takes binary display “0” or “1” is applied to the output terminal OUT as shown in FIG. 16C. , FIG.
And the voltage value described above with reference to FIG.

For this reason, especially in the section where the input signal voltage Vi is higher than the threshold voltage V _T , the output voltage which can take only “0” in the binary display becomes the high voltage value V _{H and} therefore the binary display. However, it has a drawback that it can be regarded as "1", and can only be obtained with a spike. Therefore, the present invention proposes a novel voltage comparison circuit that does not have the above-mentioned disadvantages.

[0038]

According to a first aspect of the present invention, there is provided a voltage comparison circuit comprising: (A) one two-terminal negative resistance element or a plurality of n two-terminal negative resistance elements connected in series; A first two-terminal negative resistance element circuit, and one two-terminal negative resistance element depending on whether the first negative resistance element circuit has one or a plurality of n two-terminal negative resistance elements. A first series negative resistance element circuit in which a second negative resistance element circuit having a plurality of n two-terminal negative resistance elements connected in series and a drain connected to the first series negative resistance element circuit; The series negative resistance element circuit is connected to a connection midpoint between the first and second negative resistance element circuits, and the source is connected to one end of the first series negative resistance element circuit or a power supply terminal to which a constant voltage is applied. And a field-effect transistor that is connected to the first series negative resistance element circuit. In binary display between the end "0" and "1"
And the input signal voltage is applied to the gate of the field effect transistor, and the first and second series negative resistance element circuits of the first series are connected to each other. A first voltage output circuit configured such that a connection point of the negative resistance element circuit is a first output terminal from which a first output voltage is output; and (B) the first and second negative output circuits. One two-terminal negative resistance element or a plurality of n two-terminal negative resistance elements connected in series depending on whether the negative resistance element circuit has one two-terminal negative resistance element or plural n-terminal negative resistance elements A third two-terminal negative resistance element circuit and one two-terminal negative resistance element depending on whether the third negative resistance element circuit has one or a plurality of n two-terminal negative resistance elements. A fourth device having a plurality of n two-terminal negative resistance elements connected in series A second series negative resistance element circuit connected in series with the negative resistance element circuit, and the clock signal voltage is applied across both ends of the second series negative resistance element circuit. A second output terminal from which a second output voltage is output, wherein a connection midpoint between the third and fourth negative resistance element circuits of the second series negative resistance element circuit is a second output terminal; (C) a first output voltage output from a first output terminal of the first voltage output circuit and a second output voltage output from a second output terminal of the second voltage output circuit. And a differential circuit configured to receive the output voltage of the input signal voltage and a differential circuit configured to receive the output voltage of the input signal voltage. The voltage is output as a voltage comparison output that is compared with a predetermined threshold voltage.

The voltage comparison circuit according to the second aspect of the present invention includes: (A) a first negative terminal having one two-terminal negative resistance element or a plurality of n two-terminal negative resistance elements connected in series; A two-terminal negative resistance element or a plurality of serially connected negative resistance elements depending on whether the first negative resistance element circuit has one or two n-terminal negative resistance elements. a first series negative resistance element circuit in which a second negative resistance element circuit having n two-terminal negative resistance elements is connected in series, and a drain connected to the first series negative resistance element circuit A first electric field connected to a connection midpoint between the first and second negative resistance element circuits, and a source connected to one end of the first series negative resistance element circuit or a power supply terminal supplied with a constant voltage. Effect transistor, and a binary table between both ends of the first series negative resistance element circuit. A clock signal voltage that repeats "0" and "1" is applied, and an input signal voltage is applied to the gate of the first field-effect transistor. A first voltage output circuit configured to set a connection midpoint between the first and second negative resistance element circuits of the negative resistance element circuit as a first output terminal from which a first output voltage is output; (B) The first
And the second negative resistance element circuit sets the two-terminal negative resistance element to one.
A third two-terminal negative resistance element circuit having one two-terminal negative resistance element or a plurality of n two-terminal negative resistance elements connected in series, depending on whether there are n or two or more n terminals; 3
One two-terminal negative resistance element or a plurality of n two-terminal negative resistance elements connected in series, depending on whether the negative resistance element circuit has one or two or more two-terminal negative resistance elements. A second series negative resistance element circuit in which a fourth negative resistance element circuit having an element is connected in series; and a drain connected to the third and fourth negative resistance circuits of the second series negative resistance element circuit. A second field-effect transistor connected to a connection midpoint of the negative resistance element circuit, and having a source connected to one end of the second series negative resistance element circuit or a power supply end to which a constant voltage is applied,
The clock signal voltage is applied between both ends of the second series negative resistance element circuit, and the input signal voltage is applied to a gate of the second field effect transistor. A second voltage output, wherein a connection point between the third and fourth negative resistance element circuits of the two series negative resistance element circuits is set as a second output terminal from which a second output voltage is output. A circuit; (C) a first output voltage output from a first output terminal of the first voltage output circuit and a second output output from a second output terminal of the second voltage output circuit. And a differential circuit configured to receive a differential voltage between the input signal voltage and the differential signal output from the differential circuit. The voltage is output as a voltage comparison output compared with the voltage.

In the above-described voltage comparison circuit according to the first invention of the present application and the voltage comparison circuit according to the second invention of the present application, the first of the first series negative resistance element circuits
And the second negative resistance element circuit, and the third series and fourth negative resistance element circuits of the second series negative resistance element circuit have a plurality of n two-terminal negative resistance elements,
The first output voltage output from the first voltage output circuit and the second output voltage output from the second voltage output circuit take an (n + 1) value.

[0041]

First Embodiment Next, a first embodiment of a voltage comparison circuit according to the present invention will be described with reference to FIG. FIG.
In FIG. 7, parts corresponding to those in FIG. 7 are denoted by the same reference numerals, and detailed description is omitted.

The voltage comparison circuit according to the present invention shown in FIG.
A first voltage output circuit U1 and a second voltage output circuit U2
And a differential circuit F. In this case, the voltage output circuit U
1 is a negative resistance element circuit B1 having a two-terminal negative resistance element D1 and a negative resistance element circuit B2 having a two-terminal negative resistance element D2, as described in the conventional voltage comparison circuit shown in FIG. Are connected in series, and a field-effect transistor M connected in the same manner
And

As in the case of the conventional voltage comparison circuit shown in FIG. 7, one end of the series negative resistance element circuit G is connected to the clock signal voltage source terminal Ec, and the other end is connected to the constant voltage source terminal Ec.
1, the gate of the field effect transistor M is connected to the signal input terminal IN, and the output terminal OUT (hereinafter referred to as O) from the connection point P between the negative resistance element circuits B1 and B2.
UT1) is derived. In this case, the two-terminal negative resistance element D1 and the negative resistance element circuit B1 having only the same have the current-voltage characteristics shown in FIG. 9 similar to those of the conventional voltage comparison circuit shown in FIG. Have.

Further, the two-terminal negative resistance element D2 and the negative resistance element circuit B2 having only the two-terminal negative resistance element D2 have the same current-voltage as that of the conventional voltage comparison circuit shown in FIG. Has characteristics. Further, the field effect transistor M has the same characteristics as those of the conventional voltage comparison circuit shown in FIG. Further, the composite circuit C, which is a parallel circuit of the negative resistance element circuit B2 and the field effect transistor M, also has a current-voltage characteristic as shown in FIG. Have.

Further, the voltage output circuit U2 includes a third negative resistance element circuit B having one two-terminal negative resistance element D3.
3 and a second series negative resistance element circuit G2 in which a fourth negative resistance element circuit B4 also having one two-terminal negative resistance element D4 is connected in series.

One end of the series negative resistance element circuit G2 on the negative resistance element circuit B3 side is connected to the clock signal voltage source end E.
c, the other end on the side of the negative resistance element circuit B4 is connected to the constant voltage source terminal E1, and the output terminal OUT2 is derived from a connection point P2 between the negative resistance element circuits B3 and B4. . In this case, the two-terminal negative resistance elements D3 and D4, and the negative resistance element circuits B3 and B4 having only the same have current-voltage characteristics similar to those of the two-terminal negative resistance elements D1 and D2. When their peak current values are I _P3 and I _P4 , respectively, there is a relationship of I _P3 <I _P4 .

Further, the differential circuit F may have various configurations known per se. As shown in the figure, for example, the differential circuit F has two field effect transistors Q1 and Q2, and their sources are They are connected to a constant voltage source terminal E2 through a common constant current circuit H, and the drains of the field effect transistors Q1 and Q2 are connected to the voltage source terminal EF through load resistors R1 and R2, respectively.

Then, the field effect transistors Q1 and Q
2 are connected to the output terminal OUT1 of the voltage output circuit U1 and the output terminal OUT2 of the voltage output circuit U2, respectively, and the output terminal OUT is connected to the middle point between the drain of the field effect transistor Q2 and the load resistor R2. Derived. In this case, the differential circuit F includes an output voltage output from the output terminal OUT1 of the voltage output circuit U1 and the voltage output circuit U1.
2 has an output voltage output from the second output terminal OUT2, and has a characteristic that a difference voltage between the two is output to the output terminal OUT.

The above is the first of the voltage comparison circuits according to the present invention.
It is a configuration of the embodiment. According to the voltage comparison circuit of the present invention having such a configuration, the voltage output circuit U1
However, it has the same configuration as the conventional voltage comparison circuit shown in FIG.

For this reason, although detailed description is omitted, assuming that the clock signal voltage Vc takes a voltage value as shown in FIG. 2B as in the case of the conventional voltage comparison circuit shown in FIG. the input signal voltage Vi is, as shown in FIG. 2A, a voltage value lower than the threshold voltage V _T, the threshold voltage V _T
If the input signal voltage Vi is lower than the threshold voltage V _T , the clock signal voltage Vc takes a binary value of “0” or “1” when the input signal voltage Vi is lower than the threshold voltage VT. , The output voltage which takes "0" or "1" in binary display is output terminal OUT1.
Then, as shown in FIG. 2C, a voltage value similar to that shown in FIG. 16C is obtained.

In a section where the input signal voltage Vi is higher than the threshold voltage V _T , regardless of whether the clock signal voltage Vc takes “0” or “1” in binary display, An output voltage that can only take the value “0” in the value display is obtained at the output terminal OUT1 by taking the same voltage value as shown in FIG. 16C as shown in FIG. 2C.

The voltage output circuit U2 has a configuration in which the field-effect transistor M is omitted from the voltage output circuit U1, and the peak current value I _P3 of the negative resistance element circuit B3 is changed to the negative resistance. Peak current value I of the element circuit B4
_It has a configuration that is always smaller than _P4 .

[0053] Thus, although not a detailed description, also in the input signal voltage Vi is lower interval than the threshold voltage V _T,
Also in addition the input signal voltage Vi is higher section than the threshold voltage V _T, regardless of whether the clock signal voltage Vc takes a "1" or take "0" in binary display, display of a binary "0"
Only the output voltage does not take the, to the output terminal OUT2, as shown in FIG. 2D, obtained by taking the same voltage value when obtained in high period than the input voltage Vi is the threshold voltage V _T at the voltage output circuit U1.

Further, the differential circuit F performs a differential operation by using the output voltage as shown in FIG. 2C and the output voltage as shown in FIG. 2D as inputs. For this reason, in the section where the input signal voltage Vi is a voltage value higher than the threshold voltage V _T , the binary display is performed according to whether the clock signal voltage Vc takes “0” or “1” in binary display. The output voltage which takes "0" or "1" at the output terminal OUT is obtained by taking a voltage value without spikes as shown in FIG. 2E, almost similar to that shown in FIG. 16C.

[0055] Further, in the high input voltage Vi is higher than the threshold voltage V _T interval, regardless of whether the clock signal voltage Vc takes a "1" or take "0" in binary display, display of a binary "0" The output voltage that can be obtained is obtained at the output terminal OUT by taking a voltage value without spikes as shown in FIG. 16C.

As described above, according to the voltage comparison circuit of the present invention shown in FIG. 1, the threshold voltage V _T of the input voltage Vi can be reduced without the disadvantages of the conventional voltage comparison circuit shown in FIG. The compared voltage comparison output can be easily obtained.

[0057]

Second Embodiment Next, a second embodiment of a voltage comparison circuit according to the present invention will be described with reference to FIG. FIG.
In the figure, the same reference numerals are given to parts corresponding to those in FIG. 1 and detailed description is omitted.

The voltage comparison circuit according to the present invention shown in FIG.
The voltage output circuit U2 includes a series negative resistance element circuit G2, a drain is connected to a connection point P2 between the negative resistance element circuits B3 and B4, and a source is connected to the series negative resistance element circuit G2.
1 except that the field effect transistor M2 is connected to one end of the negative resistance element circuit B4 side, and the gate of the field effect transistor M2 is connected to the signal input terminal IN. It has a configuration similar to that of the voltage comparison circuit according to the present invention shown.

Therefore, like the voltage output circuit U1, the voltage output circuit U2 compares the input signal voltage Vi with a predetermined threshold voltage (referred to as _VT2 ) and outputs the result as a voltage comparison output. However, in this case, the peak current value I _P3 of the negative resistance element circuit B3 and the peak current value I _P4 of the negative resistance element circuit B4 correspond to the threshold voltage V _{T2 and the} voltage output circuit U1.
A value different from the threshold voltage V _T, i.e., to take a smaller value than, for example, the threshold voltage V _T, are selected.

The above is the description of the second embodiment of the voltage comparison circuit according to the present invention.
It is a configuration of the embodiment. According to the voltage comparison circuit of the present invention having such a configuration, the voltage output circuit U1
Has the same configuration as the voltage comparison circuit according to the present invention shown in FIG.

For this reason, although the detailed description is omitted, the clock signal voltage Vc is the same as that shown in FIG. 2B as shown in FIG.
When the voltage value as shown in FIG.
i, as shown in the same FIG. 4A to that shown in Figure 2A, the voltage value lower than the threshold voltage V _T, to a higher voltage value than the threshold voltage V _T, if taking the voltage value increases with time, input In a section where the signal voltage Vi is lower than the threshold voltage V _T , the binary display is “0” or “1” depending on whether the clock signal voltage Vc takes “0” or “1” in binary display. Is obtained at the output terminal OUT1 with the same voltage value as shown in FIG. 4C similar to that shown in FIG. 2C.

[0062] Further, the voltage output circuit U2, except that it has a threshold voltage V _T2 is smaller than the threshold voltage V _T of the voltage output circuit U1, has the same configuration as the voltage output circuit U1. For this reason, although detailed description is omitted, the input signal voltage V
In a section where i is a voltage value lower than the threshold voltage V _T2 (Vi <V _T2 ), binary display is performed according to whether the clock signal voltage Vc takes binary display “0” or “1”. Is "0" or "1" at the output terminal OUT2.
In addition, as shown in FIG. 2D, the input signal voltage V
In a section in which i is lower than the threshold voltage V _T, it is obtained by taking a voltage value similar to that obtained as shown in FIG. 2C.

In a section where the input signal voltage Vi is a voltage value higher than the threshold voltage V _T2 (Vi> V _T2 ), the clock signal voltage Vc takes “0” in binary display or “1”.
4C, an output voltage that takes only binary display “0” is applied to the output terminal OUT2 as shown in FIG. 4C.
Obtained by taking the same voltage value and that obtained as shown in FIG. 2C in the input signal voltage Vi is higher section than the threshold voltage V _T to the output terminal T1.

Further, the differential circuit F performs a differential operation by using the output voltage as shown in FIG. 2C and the output voltage as shown in FIG. 2D as inputs. Therefore, the segment input voltage Vi is a voltage value lower than the threshold voltage _{V T2 (Vi <V T2)} , regardless of whether the clock signal voltage Vc takes a "1" or take "0" in the binary display An output voltage that can take only binary “0” is obtained at the output terminal OUT by using a voltage value without spikes as shown in FIG. 16C.

In addition, a voltage value where the input signal voltage Vi is higher than the threshold voltage V _T2 but lower than the threshold voltage V _T (V _T2 <Vi
<V _T ), depending on whether the clock signal voltage Vc takes “0” or “1” in binary display,
An output voltage having a value of “0” or “1” is obtained at the output terminal OUT by a voltage value without spikes, almost similar to that shown in FIG. 16C, as shown in FIG. 2E.

Further, in a section where the input voltage Vi is a voltage value higher than the threshold voltage V _T (Vi> V _T ), it is determined whether the clock signal voltage Vc takes “0” or “1” in binary display. Regardless, an output voltage that only takes "0" in binary display can be obtained at the output terminal OUT by using a voltage value without spikes as shown in FIG. 16C.

[0067] From the foregoing, according to the voltage comparator circuit according to the present invention shown in FIG. 3, the two comparison literal voltage comparator output to a threshold voltage V _T and V _T2 of the input voltage Vi,
As in the case of the voltage comparison circuit according to the present invention shown in FIG.
It can be easily obtained without spikes.

[0068]

Third Embodiment Next, a third embodiment of the voltage comparison circuit according to the present invention will be described with reference to FIG. FIG.
In FIG. 7, the same reference numerals are given to the portions corresponding to those in FIG. 3, and detailed description is omitted.

The voltage comparison circuit according to the present invention shown in FIG.
Except for the following, it has the same configuration as that of the voltage comparison circuit according to the present invention shown in FIG. That is, instead of the source of the field effect transistor M being connected to one end of the series negative resistance element circuit G, it is connected to another constant voltage source terminal E1 'corresponding to the constant voltage source terminal E1. ing.

The output voltages of the voltage output circuits U1 and U2 are supplied to the differential circuit F via the level shift circuits SH1 and SH2. in this case,
The level shift circuits SH1 and SH2 may have various configurations known per se. For example, the level shift circuit SH1 is connected between the voltage sources ES1 and ES1 'by a field effect transistor Q11, diodes d11 and d1.
2. The field effect transistor Q12 is connected in series in that order, the gate of the field effect transistor Q11 is connected to the output terminal OUT1 of the voltage output circuit U1, the gate of the field effect transistor Q12 is connected to the control voltage source terminal ECN, Diode d11 and field effect transistor Q1
2 is connected to the field effect transistor Q1 of the differential circuit F
May be configured to be connected to the gate.

The level shift circuit SH2 also has the voltage sources ES2 and ES2 ', like the level shift circuit SH1.
Field effect transistor Q21, diode d21
And d22, the field effect transistor Q22 is connected in series in that order, the gate of the field effect transistor Q21 is connected to the output terminal OUT2 of the voltage output circuit U2, and the gate of the field effect transistor Q22 is connected to the control voltage source terminal EC.
N, and a connection midpoint between the diode d21 and the field effect transistor Q22 may be connected to the gate of the field effect transistor Q2 of the differential circuit F.

The above is the third example of the voltage comparison circuit according to the present invention.
It is a configuration of the embodiment. The voltage comparison circuit according to the present invention having such a configuration has the same configuration as that of the voltage comparison circuit according to the present invention shown in FIG.

Therefore, although detailed description is omitted, the same operation and effect as in the case of the voltage comparison circuit according to the present invention shown in FIG. 3 can be obtained. However, in this case, the negative resistance element circuit B
In the case of the voltage comparison circuit according to the present invention shown in FIG.
2 corresponds to a current flowing from the connection middle point to the constant voltage source terminal E1.

The sum of the currents flowing from the connection point P2 between the negative resistance element circuits B3 and B4 to the constant voltage source terminals E1 and E1 'is equal to the negative resistance in the voltage comparison circuit according to the present invention shown in FIG. This corresponds to the current flowing from the connection point between the element circuits B3 and B4 to the constant voltage source terminal E1.

Further, the output voltages obtained at the output terminals OUT1 and OUT2 can be supplied to the differential circuit F in a level-shifted manner so that the differential operation is effectively performed.

[0076]

Fourth Embodiment Next, a fourth embodiment of the voltage comparison circuit according to the present invention will be described with reference to FIG. FIG.
In the figure, the same reference numerals are given to parts corresponding to those in FIG. 1 and detailed description is omitted.

The voltage comparison circuit according to the present invention shown in FIG.
Each of the negative resistance element circuits B1, B2, B3, and B4 has one two-terminal negative resistance element D1, D2, D3, and D4, and two two-terminal negative resistance elements connected in series. Resistive elements D11 and D12, D21 and D22, D
It has the same configuration as that of the voltage comparison circuit according to the present invention shown in FIG. 1 except that it has D31 and D32, and D41 and D42, respectively.

However, in this case, the two-terminal negative resistance element D
11 and D12 have current-voltage characteristics having peak current values at different voltage positions, and therefore, the negative resistance element circuit B1 has current-voltage characteristics having two peak current values. Similarly, each of the two-terminal negative resistance elements D21 and D22, D31 and D32, and D41 and D42 has a current-voltage characteristic having a peak current value at a voltage position different from each other. Each of the circuits B2, B3, and B4 also has a current-voltage characteristic having two peak current values.

The above is the fourth example of the voltage comparison circuit according to the present invention.
It is a configuration of the embodiment. According to the voltage comparison circuit according to the present invention having such a configuration, it has the same configuration as that of the voltage comparison circuit according to the present invention shown in FIG.

For this reason, although a detailed description is omitted, it is understood that an output voltage having a ternary value can be obtained as a voltage comparison output by taking a voltage value without a spike at the output terminal OUT.
it is obvious.

In the above, only a few embodiments of the present invention have been shown, and various modifications can be made without departing from the spirit of the present invention. For example, in the voltage comparison circuit according to the present invention shown in FIG. 1, instead of connecting one ends of the series negative resistance element circuits U1 and U2 to a constant voltage source terminal E1 common to them, a constant voltage that can obtain mutually different constant voltages is used. A configuration connected to the voltage source terminal may be employed to obtain the same operation and effect as described in the voltage comparison circuit according to the present invention shown in FIG.

In the voltage comparison circuit according to the present invention shown in FIG. 1, the source of the field effect transistor M is connected to the constant voltage source terminal E1 'according to the voltage comparison circuit according to the present invention shown in FIG. The same operation and effect as those of the voltage comparison circuit according to the present invention shown in FIG. 1 can be obtained with the features described in the voltage comparison circuit according to the present invention shown in FIG.

Further, in the voltage comparison circuit according to the present invention shown in FIG. 3, the sources of the field effect transistors M and M2 are different from the constant voltage source terminal E1 according to the case of the voltage comparison circuit according to the present invention shown in FIG. As a configuration connected to the constant voltage source terminal, the same operation and effect as described in the voltage comparison circuit according to the present invention shown in FIG. 3 can be obtained.

In the voltage comparison circuit according to the present invention shown in FIG. 5, the sources of the field effect transistors M and M2 are connected to the constant voltage source terminal E1 according to the case of the voltage comparison circuit according to the present invention shown in FIG. It can also be configured.

Further, in each of the voltage comparison circuits according to the present invention shown in FIGS. 1, 3, 5, and 6, each of the negative resistance element circuits B1 to B4 is connected to a plurality of n 2 (N)
+1) An output voltage having a value may be output to the output terminal OUT as a voltage comparison output.

Further, in the above description, the field effect transistor is connected to the clock signal voltage source terminal V of the series negative resistance element circuit.
Although the case where the negative resistance element circuit side opposite to the c side is connected has been described, the field effect transistor is connected to the clock signal voltage source terminal Vc side of the series negative resistance element circuit in the same manner as described above. By connecting them, the same operation and effect can be obtained.

[0087]

According to the voltage comparison circuit of the present invention, the voltage comparison output of the input signal voltage compared with the threshold voltage is
It can be easily obtained without spikes.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing a first embodiment of a voltage comparison circuit according to the present invention.

FIG. 2 is a voltage waveform diagram for explaining the voltage comparison circuit according to the present invention shown in FIG. 1;

FIG. 3 is a connection diagram showing a voltage comparison circuit according to a second embodiment of the present invention.

FIG. 4 is a voltage waveform diagram for explaining the voltage comparison circuit according to the present invention shown in FIG. 3;

FIG. 5 is a connection diagram showing a third embodiment of the voltage comparison circuit according to the present invention.

FIG. 6 is a connection diagram showing a fourth embodiment of the voltage comparison circuit according to the present invention.

FIG. 7 is a connection diagram showing a conventional voltage comparison circuit.

FIG. 8 is a diagram showing current-voltage characteristics of a two-terminal negative resistance element for describing a voltage comparison circuit according to the present invention and a conventional voltage comparison circuit.

FIG. 9 is a diagram showing current-voltage characteristics of a two-terminal negative resistance element, a negative resistance element circuit, and a composite circuit for describing a voltage comparison circuit according to the present invention and a conventional voltage comparison circuit.

FIG. 10 is a diagram showing current-voltage characteristics of a two-terminal negative resistance element and a negative resistance element circuit for describing a voltage comparison circuit according to the present invention and a conventional voltage comparison circuit.

FIG. 11 is a diagram showing current-voltage characteristics of a composite circuit for describing a voltage comparison circuit according to the present invention and a conventional voltage comparison circuit.

FIG. 12 is a diagram showing a current-voltage characteristic curve for explaining the operations of the voltage comparison circuit according to the present invention and the conventional voltage comparison circuit.

FIG. 13 is a voltage waveform chart for explaining the operations of the voltage comparison circuit according to the present invention and the conventional voltage comparison circuit.

FIG. 14 is a diagram showing a current-voltage characteristic curve for explaining the operations of the voltage comparison circuit according to the present invention and the conventional voltage comparison circuit.

FIG. 15 is a voltage waveform chart for explaining the operations of the voltage comparison circuit according to the present invention and the conventional voltage comparison circuit.

FIG. 16 is a voltage waveform diagram for explaining the operation of a conventional voltage comparison circuit.

[Explanation of symbols]

B1 to B4 Negative resistance element circuit C Composite circuit D1 to D4, D11, D12, D21, D22, D3
1, D32, D41, D42 Two-terminal negative resistance element E1, E2 Constant voltage source terminal Ec Clock signal voltage source terminal ECN Control voltage source terminal EF Voltage source terminal F Differential circuit G, G2 Series negative resistance element circuit H Constant Current circuit M Field effect transistor IN Signal input terminal OUT, OUT1, OUT2 output terminal Q1, Q2, Q11, Q12, Q21, Q22 Field effect transistor R1, R2 Load resistance SH1, SH2 Level shift circuit U1, U2 Voltage output circuit

Claims (5)

[Claims] 1. A first negative resistance element circuit having one two-terminal negative resistance element or a plurality of n two-terminal negative resistance elements connected in series, and the first negative resistance element Circuit 2
A second negative terminal having one two-terminal negative resistive element or a plurality of n two-terminal negative resistive elements connected in series depending on whether it has one terminal negative resistive element or a plurality of n negative resistive elements A first series negative resistance element circuit in which a resistance element circuit is connected in series; and a drain connecting point between the first and second negative resistance element circuits of the first series negative resistance element circuit. And a source connected to one end of the first series negative resistance element circuit or a power supply terminal to which a constant voltage is supplied, and a source of the first series negative resistance element circuit. A clock signal voltage that repeatedly takes “0” and “1” in binary display is applied between both ends,
An input signal voltage is applied to a gate of the field effect transistor, and a connection point between the first and second negative resistance element circuits of the first series negative resistance element circuit is set to a first point.
A first voltage output circuit configured to serve as a first output terminal from which the output voltage is output, and whether the first and second negative resistance element circuits have one two-terminal negative resistance element. One 2 depending on whether there are a plurality of n
Terminal negative resistance element or a plurality of n 2 connected in series
A third negative resistance element circuit having a terminal negative resistance element;
The third negative resistance element circuit has a two-terminal negative resistance element of one.
And a fourth negative resistance element circuit having a plurality of n two-terminal negative resistance elements connected in series, or a plurality of n negative resistance elements connected in series, depending on whether or not there are n or more n. A second series negative resistance element circuit connected thereto, wherein the clock signal voltage is applied across both ends of the second series negative resistance element circuit; A second voltage output circuit configured to set a connection point between the third and fourth negative resistance element circuits of the resistance element circuit as a second output terminal from which a second output voltage is output; A first output voltage output from a first output terminal of the first voltage output circuit and a second output voltage output from a second output terminal of the second voltage output circuit; And a differential circuit configured to output a differential voltage, wherein the differential voltage is output from the differential circuit. , The voltage comparator circuit, characterized in that it is designed to output as a voltage comparison output which is compared to a threshold voltage of the appointment of the input signal voltage. 2. A first negative resistance element circuit having one two-terminal negative resistance element or a plurality of n two-terminal negative resistance elements connected in series, and the first negative resistance element. Circuit 2
A second negative terminal having one two-terminal negative resistive element or a plurality of n two-terminal negative resistive elements connected in series depending on whether it has one terminal negative resistive element or a plurality of n negative resistive elements A first series negative resistance element circuit in which a resistance element circuit is connected in series; and a drain connecting point between the first and second negative resistance element circuits of the first series negative resistance element circuit. And a first field-effect transistor having a source connected to one end of the first series negative resistance element circuit or a power supply end to which a constant voltage is applied, and the first series negative resistance element A clock signal voltage that repeatedly takes "0" and "1" in binary display is applied between both ends of the circuit, and an input signal voltage is applied to the gate of the first field effect transistor. And the first series negative resistance element circuit A first voltage output circuit configured to set a connection midpoint between the first and second negative resistance element circuits as a first output terminal from which a first output voltage is output; One 2 terminal negative resistance element depending on whether the circuit has one or two n-terminal negative resistance elements.
Terminal negative resistance element or a plurality of n 2 connected in series
A third negative resistance element circuit having a terminal negative resistance element;
The third negative resistance element circuit has a two-terminal negative resistance element of one.
And a fourth negative resistance element circuit having a plurality of n two-terminal negative resistance elements connected in series, or a plurality of n negative resistance elements connected in series, depending on whether or not there are n or more n. A connected second series negative resistance element circuit, a drain connected to a connection midpoint of the third and fourth negative resistance element circuits of the second series negative resistance element circuit, and a source connected to the second series negative resistance element circuit. Second
A second field-effect transistor connected to one end of the series negative resistance element circuit or a power supply terminal to which a constant voltage is supplied, and the clock signal is connected between both ends of the second series negative resistance element circuit. A voltage is applied, and the input signal voltage is applied to the gate of the second field effect transistor. The third and fourth negative resistances of the second series negative resistance element circuit A second voltage output circuit configured to set a connection middle point of the resistance element circuit as a second output terminal from which a second output voltage is output; and from a first output terminal of the first voltage output circuit. A differential circuit configured to input a first output voltage to be output and a second output voltage output from a second output terminal of the second voltage output circuit, and output a difference voltage between the two. And the difference voltage output from the differential circuit is Voltage comparator circuit, characterized in that it is designed to output as the comparison voltage comparison output and the threshold voltage of the appointment of the input signal voltage. 3. The voltage comparison circuit according to claim 1, wherein the first and second negative resistance element circuits of the first series negative resistance element circuit and the second series negative resistance element are connected to each other. The first and second output voltage output from the first voltage output circuit, because the third and fourth negative resistance element circuits of the resistance element circuit have a plurality of n two-terminal negative resistance elements, The second
The second output voltage output from the voltage output circuit of (n) is (n
+1) A voltage comparison circuit that takes a value. 4. The voltage comparison circuit according to claim 1, wherein the first and second negative resistance element circuits of the first series negative resistance element circuit and the second series negative resistance element are connected to each other. Since the third and fourth negative resistance element circuits of the resistance element circuit have one two-terminal negative resistance element, the first output voltage output from the first voltage output circuit; A voltage comparison circuit, wherein the second output voltage output from the second voltage output circuit takes two values. 5. The voltage comparison circuit according to claim 1, wherein the first and second negative resistance element circuits of the first series negative resistance element circuit and the second series negative resistance element are connected to each other. It is assumed that a plurality of n two-terminal negative resistance elements included in the third and fourth negative resistance element circuits of the resistance element circuit are provided. When n is 2, the two-terminal negative resistance element is output from the first voltage output circuit. A first output voltage and a second output voltage output from the second voltage output circuit take three values.