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JP2001267564A - Semiconductor device and method of manufacturing for semiconductor device - Google Patents

Semiconductor device and method of manufacturing for semiconductor device

Info

Publication number
JP2001267564A
JP2001267564A JP2000080441A JP2000080441A JP2001267564A JP 2001267564 A JP2001267564 A JP 2001267564A JP 2000080441 A JP2000080441 A JP 2000080441A JP 2000080441 A JP2000080441 A JP 2000080441A JP 2001267564 A JP2001267564 A JP 2001267564A
Authority
JP
Japan
Prior art keywords
semiconductor device
teeth
electrode
comb
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000080441A
Other languages
Japanese (ja)
Inventor
Noboru Noda
昇 野田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000080441A priority Critical patent/JP2001267564A/en
Publication of JP2001267564A publication Critical patent/JP2001267564A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/481—Disposition
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, whose high-frequency high-output characteristic can be improved by fining the structure, without having to increase the size of the semiconductor device. SOLUTION: A plurality of rod-type first conductors are aligned in the vertical direction, so as to be in face-contact with a semiconductor region. On the semiconductor region, a plurality of rod-type second conductors are aligned in the vertical direction on both the right side and the left side of the first conductors. A comb-like third conductor which has a plurality of fist teeth, which are connected with end portions of the first conductors on the rear and aligned in a lateral direction and the rear of which conductor is exposed, and a comb-like forth conductor, having second teeth which are arranged between the first teeth and are connected with end portions of the second conductors on the rear and the rear of which conductor is exposed, are arranged above the first and the second conductors. Thereby the shapes and alignment of the first and the second conductors can be determined, without depending on the shapes of the third and the fourth conductors.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、無線電話機等に用
いられる高周波高出力の半導体装置に関し、特に、微細
化に適するようにトランジスタ・ユニットと引き出し用
の電極を配置した半導体装置とこの半導体装置の製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency, high-output semiconductor device used for a radio telephone or the like, and more particularly to a semiconductor device having a transistor unit and a lead-out electrode suitable for miniaturization and this semiconductor device. And a method for producing the same.

【０００２】[0002]

【従来の技術】図１７に従来いられる高周波高出力用の
半導体装置を示す。半導体基板の上の上方に第１の主電
極用ボンディングパッド６５が配置され、ボンディング
パッド６５の下に櫛状の第１の主電極６３が接続されて
いる。この第１の主電極６３の櫛状の歯は下の方向を向
くように配置させる。第１の主電極６３の櫛状の歯の１
本毎に周辺に沿うように制御電極６２を配置する。制御
電極６２を挿んで第１の主電極６３の櫛状の歯の反対側
に制御電極６２の周辺に沿うように第２の主電極６１が
配置される。制御電極６２の下方で接続するように制御
電極の第１の引き出し電極６４が配置される。そして、
引きだし電極６４の下方で接続するように制御電極用ボ
ンディングパッド６６が配置される。ボンディングパッ
ド６６の下方には、上記のボンディングパッド６５から
ボンディングパッド６６までの配置をボンディングパッ
ド６６で折り返したように配置される。第１の主電極６
３の櫛状の歯と、制御電極６２と、第２の主電極６１の
紙面奥の方向の半導体基板にはトランジスタが形成され
ている。第２の主電極用ボンディングパッドは半導体基
板表面には形成されず、第２の主電極６１は、半導体基
板中を通って基板の裏面に配置された電極に引き出され
る。2. Description of the Related Art FIG. 17 shows a conventional high-frequency high-output semiconductor device. A first main electrode bonding pad 65 is arranged above the semiconductor substrate, and a comb-shaped first main electrode 63 is connected below the bonding pad 65. The comb-like teeth of the first main electrode 63 are arranged so as to face downward. 1 of the comb-shaped teeth of the first main electrode 63
The control electrode 62 is arranged along the periphery for each book. The second main electrode 61 is arranged on the opposite side of the comb-shaped teeth of the first main electrode 63 with the control electrode 62 inserted, along the periphery of the control electrode 62. A first extraction electrode 64 of the control electrode is arranged so as to be connected below the control electrode 62. And
A control electrode bonding pad 66 is arranged so as to be connected below the extraction electrode 64. Below the bonding pad 66, the arrangement from the bonding pad 65 to the bonding pad 66 is arranged such that the bonding pad 66 is turned back. First main electrode 6
A transistor is formed on the semiconductor substrate in the direction away from the paper of the third comb-shaped teeth, the control electrode 62, and the second main electrode 61. The second main electrode bonding pad is not formed on the surface of the semiconductor substrate, and the second main electrode 61 passes through the semiconductor substrate and is led out to an electrode arranged on the back surface of the substrate.

【０００３】トランジスタを挿んでボンディングパッド
６５とボンディングパッド６６が交互に配列されること
になる。このことにより、ボンディングパッド６５とト
ランジスタ間の距離と、ボンディングパッド６５とトラ
ンジスタ間の距離の均一性を高めることができ、トラン
ジスタ動作の均一性を高めることができた。第１の主電
極６３の櫛状の歯の長さを５０ｕｍと短くすることで、
高周波特性を向上すると共に電極の電流密度を１Ｅ５Ａ
／ｃｍ２以下に抑えられ信頼性も確保している。[0003] Bonding pads 65 and bonding pads 66 are alternately arranged by inserting transistors. Thus, the uniformity of the distance between the bonding pad 65 and the transistor and the distance between the bonding pad 65 and the transistor can be improved, and the uniformity of the transistor operation can be improved. By shortening the length of the comb-like teeth of the first main electrode 63 to 50 μm,
Improve high frequency characteristics and reduce electrode current density to 1E5A
/ Cm2 or less, and reliability is also ensured.

【０００４】しかし、さらに高周波特性を向上させるた
めに、ドレイン・ソース間距離を微細化することが必要
であるが、この距離の微細化により必然的に第１の主電
極６３の櫛状の歯の幅が狭くなるので、信頼性確保の為
に電流密度を上記の範囲以下に抑えるために歯の長さを
短くしなければならない。一方、総電流量も増やさない
までも微細化前の値を維持したい。そこで、歯の長さを
短くし、歯の数等を増やしてトランジスタ横に長くする
と、ボンディングパッド６５と６６の左右両側に不使用
の半導体表面がおおきくなってしまい、半導体装置が大
きくなってしまう問題があった。さらに、半導体装置の
横幅が大きくなることで、半導体装置の左右からの中央
に位置するボンディングパッドにボンディングするため
のボンディングワイヤーが長くなり直列インダクタンス
が大きく高周波ロスが大きいという問題があった。さら
に、トランジスタの微細化等の設計変更によりトランジ
スタの大きさが変わるとボンディングパッド６５と６６
の間隔を変えたり、トランジスタの段数を増やすとパッ
ド６５と６６の数を増やす必要があった。このことはパ
ッケージの設計の変更を意味し半導体装置の製造コスト
を押し上げる原因となっていた。However, in order to further improve the high-frequency characteristics, it is necessary to reduce the distance between the drain and the source. However, the reduction in the distance inevitably results in the comb-like teeth of the first main electrode 63. Therefore, the length of the teeth must be shortened in order to keep the current density below the above-mentioned range in order to secure reliability. On the other hand, it is desired to maintain the value before miniaturization without increasing the total current amount. Therefore, if the length of the teeth is shortened, the number of teeth is increased, and the width of the transistor is lengthened, the unused semiconductor surface becomes large on the left and right sides of the bonding pads 65 and 66, and the semiconductor device becomes large. There was a problem. Further, as the lateral width of the semiconductor device is increased, there is a problem that a bonding wire for bonding to a bonding pad located at the center from the left and right of the semiconductor device becomes longer, a series inductance is increased, and a high-frequency loss is increased. Further, when the size of the transistor changes due to a design change such as miniaturization of the transistor, the bonding pads 65 and 66 may be changed.
It was necessary to increase the number of pads 65 and 66 by changing the distance between them and increasing the number of transistor stages. This means that the design of the package has been changed, which has increased the manufacturing cost of the semiconductor device.

【０００５】[0005]

【発明が解決しようとする課題】本発明は、上記事情に
鑑みてなされたものであり、その目的とするところは、
半導体装置を大きくしたりボンディングワイヤーを長く
したり電流密度を高くすることなしに、高周波高出力特
性を改善できる半導体装置を提供する事にある。DISCLOSURE OF THE INVENTION The present invention has been made in view of the above circumstances.
An object of the present invention is to provide a semiconductor device capable of improving high-frequency high-output characteristics without increasing the size of the semiconductor device, lengthening the bonding wire, or increasing the current density.

【０００６】また、本発明の目的は、パッケージの設計
の変更なしに、高周波高出力特性を改善できる半導体装
置を提供する事にある。Another object of the present invention is to provide a semiconductor device capable of improving high-frequency high-output characteristics without changing the design of a package.

【０００７】さらに、本発明の目的は、半導体装置を大
きくしたりボンディングワイヤーを長くしたり電流密度
を高くすることなしに、高周波高出力特性を改善できる
半導体装置の製造方法を提供する事にある。It is a further object of the present invention to provide a method of manufacturing a semiconductor device capable of improving high-frequency high-output characteristics without increasing the size of the semiconductor device, lengthening the bonding wire, or increasing the current density. .

【０００８】最後に、本発明の目的は、パッケージの設
計の変更なしに、高周波高出力特性を改善できる半導体
装置の製造方法を提供する事にある。Finally, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving high-frequency high-output characteristics without changing the design of a package.

【０００９】[0009]

【課題を解決するための手段】上記問題点を解決するた
めの本発明の第１の特徴は、第１導電型の第１の半導体
領域と、この第１の半導体領域の表面の一部に面接触し
縦方向に長い第２導電型の複数の第２の半導体領域と、
この第２の半導体領域に面接触し縦方向に並ぶ複数の第
１の歯部とこの第１の歯部に接続する第１の背部を有す
る櫛状の第１の導体と、第１の半導体領域の上に設けら
れ第１の歯部の左右両側に縦方向に並ぶ複数の第２の歯
部とこの第２の歯部に接続する第２の背部を有する櫛状
の第２の導体と、第１の背部と裏面で接続して第１と第
２の導体の上方で横方向に並ぶ複数の第３の歯部とこの
第３の歯部に接続し露出する第３の背部を有する櫛状の
第３の導体と、第２の背部と裏面で接続して第１と第２
の導体の上方で第３の歯部と歯部の間に配置される第４
の歯部とこの第４の歯部に接続し露出する第４の背部を
有する櫛状の第４の導体とを備える半導体装置であるこ
とである。A first feature of the present invention for solving the above problems is that a first semiconductor region of a first conductivity type and a part of the surface of the first semiconductor region are provided. A plurality of second semiconductor regions of a second conductivity type which are in surface contact and elongated in the longitudinal direction;
A first comb-shaped conductor having a plurality of first tooth portions which are in surface contact with the second semiconductor region and are arranged in the vertical direction, and a first back portion connected to the first tooth portion; A second comb-shaped conductor having a plurality of second teeth arranged on the left and right sides on the left and right sides of the first teeth and a second back connected to the second teeth; , A plurality of third teeth connected laterally above the first and second conductors connected at the first back and the back, and a third back connected to and exposed to the third teeth. A third conductor in the form of a comb is connected to the second back part and the back surface by the first and second conductors.
A fourth tooth disposed between the third teeth above the conductor
And a comb-shaped fourth conductor having a fourth back portion connected to and exposed to the fourth tooth portion.

【００１０】ここで、「第１導電型」と「第２導電型」
とは、互いに反対の導電型である。例えば、第１導電型
をｎ型とすれば、第２導電型はｐ型であり、第１導電型
をｐ型とすれば、第２導電型はｎ型である。第１及び第
２の「半導体領域」の材料としては例えば単結晶シリコ
ンや単結晶ガリウム砒素（ＧａＡｓ）等が代表的であ
る。「歯部と背部を有する櫛状」の、歯部は櫛で髪を梳
かす時に髪の間に入る部分であり、背部は複数の歯部を
固定する部分のことである。「露出する」とは、保護膜
等によって覆われていない事を意味する。Here, the "first conductivity type" and the "second conductivity type"
Are the opposite conductivity types. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type. As a material of the first and second “semiconductor regions”, for example, single crystal silicon, single crystal gallium arsenide (GaAs), or the like is representative. In the “comb shape having a tooth portion and a back portion”, the tooth portion is a portion that enters between hairs when combing hair with a comb, and the back portion is a portion that fixes a plurality of teeth. “Exposed” means not covered by a protective film or the like.

【００１１】このことにより、第１の歯部はトランジス
タの第１の主電極として機能し、第２の歯部は同一のト
ランジスタの制御電極として機能させることができる。
そして、第３の背部の露出部はこの第１の主電極のボン
ディングパッドとして、また、第４の背部の露出部はこ
の制御電極のボンディングパッドとして機能させること
ができる。ここで、主電極とは、電界効果トランジスタ
ではドレイン電極又はソース電極のことであり、バイポ
ーラトランジスタではエミッタ電極又はコレクタ電極の
ことである。制御電極とは、電界効果トランジスタでは
ゲート電極のことであり、バイポーラトランジスタでは
ベース電極のことである。また、ボンディングパッドと
は、この半導体装置に外部の電源を接続したり、入出力
信号を外部回路に出入力させるために引き出されている
接続端子のことである。Thus, the first tooth part can function as the first main electrode of the transistor, and the second tooth part can function as the control electrode of the same transistor.
The exposed portion of the third back portion can function as a bonding pad of the first main electrode, and the exposed portion of the fourth back portion can function as a bonding pad of the control electrode. Here, the main electrode is a drain electrode or a source electrode in a field effect transistor, and is an emitter electrode or a collector electrode in a bipolar transistor. The control electrode is a gate electrode in a field effect transistor, and is a base electrode in a bipolar transistor. The bonding pad is a connection terminal that is drawn out to connect an external power supply to the semiconductor device or input / output an input / output signal to / from an external circuit.

【００１２】そして、この半導体装置においては、トラ
ンジスタの間にボンディングパッドを配置していないの
で、ボンディングパッドの配置位置に影響されることな
くトランジスタの配置等の設計変更が可能である。ボン
ディングパッドは、トランジスタの周辺部に配置される
のでボンディングパッドから外部に引き出すボンディン
グワイヤの長さを短くすることができる。In this semiconductor device, since no bonding pads are arranged between the transistors, it is possible to change the design such as the arrangement of the transistors without being affected by the arrangement positions of the bonding pads. Since the bonding pad is arranged at the periphery of the transistor, the length of the bonding wire pulled out from the bonding pad to the outside can be reduced.

【００１３】なお、主電極と制御電極からボンディング
パッドまでの距離が、各歯部の位置によって大きく異な
ってしまう。この距離の差による電気抵抗の差は、第３
の歯部と第４の歯部の厚さと幅を大きくすることができ
るので、トランジスタ動作の均一性が確保できるまで低
減することができる。Note that the distance from the main electrode and the control electrode to the bonding pad greatly varies depending on the position of each tooth. The difference in electrical resistance due to this difference in distance is the third
Since the thickness and width of the tooth portion and the fourth tooth portion can be increased, it can be reduced until uniformity of transistor operation can be ensured.

【００１４】さらに高周波特性を向上させるために、主
電極同士の間隔を微細化する場合を考える。この距離の
微細化により、必然的に第１の歯部の幅が狭くなるの
で、信頼性確保の為に電流密度を一定値以下に抑えるた
めに第１の歯部の長さを短くしなければならない。そし
て、総電流量も増やさないまでも微細化前の値を維持す
るために、第１の歯部の幅が狭くなった分だけ歯部の数
を増やし、第１の歯部の長さが短くなった分だけ第３の
歯部の数を増やせばよい。そして、この微細化の前後
で、トランジスタの配置される領域を大きく変更させる
ことなく、トランジスタの活性領域も同等な面積を確保
でき、同等な許容電流を確保できるので、ボンディング
パッドの配置や個数を変更する必要がなく、半導体装置
を大きくしなくてすむ。パッケージの形状の変更も不要
である。In order to further improve the high frequency characteristics, consider a case where the distance between the main electrodes is reduced. Since the width of the first tooth portion is inevitably narrowed due to the miniaturization of the distance, the length of the first tooth portion must be shortened in order to keep the current density below a certain value in order to ensure reliability. Must. Then, in order to maintain the value before the miniaturization without increasing the total current amount, the number of the teeth is increased by an amount corresponding to the decrease in the width of the first teeth, and the length of the first teeth is reduced. What is necessary is just to increase the number of 3rd tooth parts by the part shortened. Before and after the miniaturization, the active region of the transistor can have the same area and the same allowable current can be ensured without greatly changing the region where the transistor is arranged. There is no need to change, and the semiconductor device does not need to be large. There is no need to change the shape of the package.

【００１５】本発明の第１の特徴は、第１と第２の導体
の上で、第３と第４の導体の下に第１の絶縁膜を備える
事により一層効果的である。このことにより、第１の絶
縁膜は第１と第２の導体と、第３と第４の導体を仕切る
層間絶縁膜として機能する。そして、第１と第２の導体
によらず、第３と第４の導体の太さを太くすることがで
きる。The first feature of the present invention is more effective by providing a first insulating film on the first and second conductors and below the third and fourth conductors. Thus, the first insulating film functions as an interlayer insulating film that partitions the first and second conductors and the third and fourth conductors. And the thickness of the third and fourth conductors can be increased irrespective of the first and second conductors.

【００１６】本発明の第１の特徴は、第１の背部を挿ん
で両側に第１の歯部を有する事、そして、第２の背部を
挿んで両側に第２の歯部を有する事により一層効果的で
ある。このことにより、第１の背部の数とこれに接続す
る第３の歯部の数、そして、第２の背部の数とこれに接
続する第４の歯部の数を減らすことができる。A first feature of the present invention is that a first back portion is inserted to have first tooth portions on both sides, and a second back portion is inserted to have second tooth portions on both sides. More effective. As a result, the number of the first spines and the number of the third teeth connected thereto, and the number of the second spines and the number of the fourth teeth connected thereto can be reduced.

【００１７】本発明の第１の特徴は、第３の歯は第３の
背部に近い部分ほど太い事、そして、第４の歯は第４の
背部に近い部分ほど太い事により一層効果的である。こ
のことにより、歯部のどの部分においても電流密度を一
定値以下たとえば１×１０５Ａ／ｃｍ２以下にできるの
で装置の信頼性を高く保つことができる。The first feature of the present invention is that the third teeth are thicker near the third back, and the fourth teeth are thicker near the fourth back. is there. As a result, the current density can be reduced to a certain value or less, for example, 1 × 10 5 A / cm 2 or less at any part of the tooth portion, and the reliability of the device can be kept high.

【００１８】本発明の第１の特徴は、露出した第３と第
４の背部に接続するワイヤーを備える事により一層効果
的である。このことにより、露出した第３と第４の背部
はボンディングパッドとして機能し、ワイヤーはボンデ
ィングワイヤーとして機能する。そして、外部回路との
接続や、パッケージの形成が可能になる。The first feature of the present invention is more effective by providing wires connecting to the exposed third and fourth backs. Thus, the exposed third and fourth backs function as bonding pads, and the wires function as bonding wires. Then, connection with an external circuit and formation of a package become possible.

【００１９】本発明の第１の特徴は、第２の歯部と第１
の半導体領域とに面接触し互いの接触面が平行であり第
２の半導体領域の端部と面接触する縦方向に長い第２の
絶縁膜と、第１の半導体領域の表面の一部に面接触し第
２の絶縁膜の端部と面接触する縦方向に長い第２導電型
の複数の第３の半導体領域を備える事により一層効果的
である。このことにより、第２の半導体領域は電界効果
トランジスタのドレイン領域として、第３の半導体領域
はソース領域として、第１の歯部はドレイン電極とし
て、第２の歯部はゲート電極として、第２の絶縁膜はゲ
ート絶縁膜として機能させることができる。The first feature of the present invention is that the second tooth portion and the first
A second insulating film, which is in longitudinal contact with the semiconductor region of the first semiconductor region and whose contact surfaces are parallel to each other and which is in surface contact with the end of the second semiconductor region, and a part of the surface of the first semiconductor region; It is more effective to provide a plurality of third semiconductor regions of the second conductivity type that are long in the vertical direction and are in surface contact with the end of the second insulating film. Thus, the second semiconductor region serves as a drain region of the field effect transistor, the third semiconductor region serves as a source region, the first tooth portion serves as a drain electrode, the second tooth portion serves as a gate electrode, and the second tooth portion serves as a gate electrode. Can function as a gate insulating film.

【００２０】本発明の第１の特徴は、第２の歯部と第１
の半導体領域とが面接触し、第１の半導体領域の裏面と
面接触する第２導電型の第４の半導体領域を備える事に
より一層効果的である。このことにより、第１の半導体
領域はバイポーラトランジスタのベース領域として、第
２の半導体領域はエミッタ領域として、第４の半導体領
域はコレクタ領域として、第１の歯部はエミッタ電極と
して、第２の歯部はベース電極として機能させることが
できる。The first feature of the present invention is that the second tooth portion and the first
It is more effective to provide a fourth semiconductor region of the second conductivity type which is in surface contact with the first semiconductor region and is in surface contact with the back surface of the first semiconductor region. Thus, the first semiconductor region serves as a base region of the bipolar transistor, the second semiconductor region serves as an emitter region, the fourth semiconductor region serves as a collector region, the first tooth portion serves as an emitter electrode, and the second semiconductor region serves as a second electrode. The teeth can function as a base electrode.

【００２１】本発明の第２の特徴は、第１導電型の第１
の半導体領域の表面の一部に面接触する縦方向に長い第
２導電型の複数の第２の半導体領域を形成する工程と、
この第２の半導体領域に面接触し縦方向に並ぶ複数の第
１の歯部とこの第１の歯部に接続する第１の背部を有す
る櫛状の第１の導体を形成する行程と、第１の半導体領
域の上に設けられ第１の歯部の左右両側に縦方向に並ぶ
複数の第２の歯部と、第２の歯部に接続する第２の背部
を有する櫛状の第２の導体を形成する工程と、第１の背
部と裏面で接続して第１と第２の導体の上方で横方向に
並ぶ複数の第３の歯部とこの第３の歯部に接続し露出す
る第３の背部を有する櫛状の第３の導体を形成する工程
と、第２の背部と裏面で接続して第１と第２の導体の上
方で第３の歯と歯の間に配置される第４の歯部とこの第
４の歯部に接続し露出する第４の背部を有する櫛状の第
４の導体を形成する工程とを有する半導体装置の製造方
法であることである。このことにより、本発明の第１の
特徴の半導体装置を製造することができる。The second feature of the present invention is that the first conductivity type
Forming a plurality of second semiconductor regions of a second conductivity type that are vertically long and are in surface contact with a part of the surface of the semiconductor region;
Forming a first comb-shaped conductor having a plurality of first teeth that are in surface contact with the second semiconductor region and are arranged in the vertical direction, and a first back connected to the first teeth; Comb-shaped second teeth provided on the first semiconductor region and having a plurality of second teeth vertically aligned on both left and right sides of the first teeth, and a second spine connected to the second teeth. Forming a second conductor; connecting a first back portion and a back surface to a plurality of third teeth portions arranged in a horizontal direction above the first and second conductors; and connecting to the third teeth portions. Forming a third comb-shaped conductor having an exposed third back, connecting the second back and the back and connecting the third conductor between the third teeth above the first and second conductors; Forming a fourth comb-shaped conductor having a fourth tooth portion disposed and a fourth back portion connected to and exposed to the fourth tooth portion. . Thus, the semiconductor device according to the first aspect of the present invention can be manufactured.

【００２２】本発明の第２の特徴は、第２の半導体領域
を形成する工程において第２の半導体領域を配置するピ
ッチを狭める事と、第１の導体を形成する行程において
第１の歯部の幅を狭くし長さを短くし本数を増やす事
と、第２の導体を形成する行程において第２の歯部の幅
を狭くし長さを短くし本数を増やす事と、第３の導体を
形成する行程において第３の歯部の本数を増やす事と、
第４の導体を形成する行程において第４の歯部の本数を
増やす事により一層効果的である。ここで、「ピッチ」
とは、第２の半導体領域を配置する繰り返し間隔のこと
である。このことにより、本発明の第１の特徴の半導体
装置の高周波特性を向上させる事ができる。A second feature of the present invention is that the pitch for arranging the second semiconductor region is reduced in the step of forming the second semiconductor region, and the first tooth portion is formed in the process of forming the first conductor. The width of the second tooth portion is increased by reducing the width of the second tooth portion, and the number of the second tooth portion is reduced by increasing the number of the third conductor in the process of forming the second conductor. Increasing the number of third teeth in the process of forming
It is more effective to increase the number of the fourth teeth in the process of forming the fourth conductor. Where "pitch"
Is a repetition interval at which the second semiconductor region is arranged. Thus, the high-frequency characteristics of the semiconductor device according to the first aspect of the present invention can be improved.

【００２３】[0023]

【発明の実施の形態】次に、図面を参照して、本発明の
実施の形態として半導体装置と半導体装置の製造方法を
説明する。以下の図面の記載において、同一又は類似の
部分には同一又は類似の符号を付している。また、図面
は模式的なものであり、厚みと平面寸法との関係、各層
の厚みの比率等は現実のものとは異なることに留意すべ
きである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor device and a method of manufacturing the semiconductor device will be described as an embodiment of the present invention with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. In addition, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from actual ones.

【００２４】（実施例１）図１は、本発明の実施例１に
係る半導体装置の上方からの透視図である。この半導体
装置は電界効果トランジスタ（ＦＥＴ）である。半導体
装置の左側に第１の主電極用ボンディングパッド７５が
上下方向に２つ並べて配置され、右方向に伸びる２本の
歯を有する櫛状の第１の主電極用の引き出し電極４がボ
ンディングパッド７５に接続するように配置されてい
る。２本の歯はボンディングパッド７５に近くなる程太
くなる。半導体装置の右側に制御電極用ボンディングパ
ッド７６が上下方向に２つ並べて配置され、左方向に伸
びる３本の歯を有する櫛状の制御電極用の第２の引き出
し電極５がボンディングパッド７６に接続するように配
置されている。３本の歯はボンディングパッド７６に近
くなる程太くなる。引き出し電極４と５の奥側に第２の
主電極１と、引き出し電極５に接続する制御電極２と、
引き出し電極４に接続する第１の主電極３が配置されて
いる。(Embodiment 1) FIG. 1 is a perspective view from above of a semiconductor device according to Embodiment 1 of the present invention. This semiconductor device is a field effect transistor (FET). Two first main electrode bonding pads 75 are vertically arranged on the left side of the semiconductor device, and a comb-like first main electrode lead electrode 4 having two teeth extending rightward is used as a bonding pad. 75. The two teeth become thicker as they come closer to the bonding pad 75. Two control electrode bonding pads 76 are vertically arranged on the right side of the semiconductor device, and a comb-shaped control electrode second lead-out electrode 5 having three teeth extending leftward is connected to the bonding pad 76. It is arranged to be. The three teeth become thicker as they come closer to the bonding pad 76. A second main electrode 1 behind the extraction electrodes 4 and 5, a control electrode 2 connected to the extraction electrode 5,
The first main electrode 3 connected to the extraction electrode 4 is arranged.

【００２５】図２（ａ）も、本発明の実施例１に係る半
導体装置の上方からの透視図である。図２（ｂ）は、本
発明の実施例１に係る半導体装置の断面図である。図１
は図２の一部の拡大図である。図１で説明したボンディ
ングパッド７５と７６、引き出し電極４と５が、半導体
基板（いわゆるペレット）７の上に配置されている。半
導体基板７は、ペレット・マウント材１０によってペレ
ット実装基板１１の凹部の中央に接着してある。実装基
板１１の凹形状の肩部にリード９が固定され、リード９
は半導体装置の外部まで引き出されている。ボンディン
グワイヤ８が、リード９とボンディングパッド７５ある
いは７６の間を接続するように配置される。実装基板１
１の肩部の周囲には側壁１２が設けられ、側壁１２の上
には蓋１３が設けられる。実装基板１１、リード９、側
壁１２と蓋１３とによって内部空間は気密が保持されて
いる。ボンディングパッド７５と７６は、半導体基板７
の周辺部に配置されるのでボンディングワイヤ８の長さ
を短くすることができる。FIG. 2A is also a perspective view from above of the semiconductor device according to the first embodiment of the present invention. FIG. 2B is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention. FIG.
3 is an enlarged view of a part of FIG. The bonding pads 75 and 76 and the lead electrodes 4 and 5 described in FIG. 1 are arranged on a semiconductor substrate (so-called pellet) 7. The semiconductor substrate 7 is adhered to the center of the concave portion of the pellet mounting substrate 11 by the pellet mounting material 10. The lead 9 is fixed to the concave shoulder of the mounting substrate 11,
Are drawn out of the semiconductor device. A bonding wire 8 is arranged to connect between the lead 9 and the bonding pad 75 or 76. Mounting board 1
A side wall 12 is provided around the shoulder portion 1, and a lid 13 is provided on the side wall 12. The internal space is kept airtight by the mounting board 11, the leads 9, the side walls 12, and the lid 13. The bonding pads 75 and 76 are
, The length of the bonding wire 8 can be reduced.

【００２６】図３も、本発明の実施例１に係る半導体装
置の上方からの透視図である。図３では図１のボンディ
ングパッド７５と７６、引き出し電極４と５をも透視し
たとして省略して記載している。半導体基板上の上方に
制御電極の第１の引き出し電極１４が配置され、引き出
し電極１４の表面は図１の制御電極の第２の引き出し電
極５の裏面と接続している。引き出し電極１４の下に櫛
状の制御電極２が接続されている。この制御電極２の櫛
状の歯は下の方向を向くように配置させる。制御電極２
の櫛状の左右両端に位置する歯の外側と、歯と歯の間の
１つおきに第２の主電極１を配置する。制御電極２の歯
の部分を挿んで第２の主電極１の反対側に第１の主電極
３の櫛状の歯の部分が配置される。第１の主電極３は上
下両方向に両刃の櫛状の歯が配置されている。第１の主
電極３の櫛状の背の下方には、上記の引き出し電極１４
から第１の主電極３の櫛状の背までの配置を第１の主電
極３の櫛状の背で折り返したように配置される。同様
に、中央部の引き出し電極１４の下方には、最上部の引
き出し電極１４から中央部の引き出し電極１４までの配
置を中央部の引き出し電極１４で折り返したように配置
される。第１の主電極３の櫛状の背部の表面は図１の第
１の主電極用の引き出し電極４の裏面と接続している。FIG. 3 is a perspective view from above of the semiconductor device according to the first embodiment of the present invention. In FIG. 3, the bonding pads 75 and 76 and the extraction electrodes 4 and 5 in FIG. A first extraction electrode 14 of the control electrode is arranged above the semiconductor substrate, and the surface of the extraction electrode 14 is connected to the back surface of the second extraction electrode 5 of the control electrode in FIG. The comb-shaped control electrode 2 is connected below the extraction electrode 14. The comb-shaped teeth of the control electrode 2 are arranged so as to face downward. Control electrode 2
The second main electrode 1 is arranged outside the teeth located at the left and right ends of the comb and every other between the teeth. The comb-shaped teeth of the first main electrode 3 are arranged on the opposite side of the second main electrode 1 by inserting the teeth of the control electrode 2. The first main electrode 3 has comb-shaped teeth of both edges arranged in both the upper and lower directions. Below the comb-shaped back of the first main electrode 3, the above-mentioned extraction electrode 14 is provided.
From the first main electrode 3 to the comb-shaped spine of the first main electrode 3. Similarly, below the central extraction electrode 14, the arrangement from the uppermost extraction electrode 14 to the central extraction electrode 14 is arranged so as to be folded back by the central extraction electrode 14. The surface of the comb-shaped back portion of the first main electrode 3 is connected to the back surface of the first main electrode extraction electrode 4 in FIG.

【００２７】第１の主電極３の櫛状の歯と、制御電極２
の櫛状の歯と、第２の主電極１の紙面奥の方向の半導体
基板にはトランジスタが形成されている。トランジスタ
を構成する最小の領域は、セル・トランジスタ１７と１
８である。セル・トランジスタ１７と１８とは線対称の
関係にあり、トランジスタとしては同等の電気特性を発
揮する。このセル・トランジスタ１７と１８を交互に６
個ずつ並べることでトランジスタ・ユニット１５と１６
が構成されている。トランジスタ・ユニット１５と１６
とは、配置される位置が１８０度回転しているだけで全
く同一の構造をしている。トランジスタ・ユニット１５
と１６が交互に２つずつ並べられて半導体装置が構成さ
れている。ユニット１５と１６の間隔は３０μｍ程度離
して配列する。トランジスタ・ユニット１５と１６は、
半導体装置の活性領域であり、その面積の総和は半導体
装置の最大の許容電流量に比例する。The comb-shaped teeth of the first main electrode 3 and the control electrode 2
A transistor is formed on the semiconductor substrate in the direction of the second main electrode 1 in the depth direction of the paper surface of the comb-like teeth of the second main electrode 1. The minimum area constituting the transistor is the cell transistors 17 and 1
8 The cell transistors 17 and 18 have a line-symmetric relationship, and exhibit the same electrical characteristics as transistors. The cell transistors 17 and 18 are alternately set to 6
Transistor units 15 and 16
Is configured. Transistor units 15 and 16
Has exactly the same structure except that the position where it is arranged is rotated by 180 degrees. Transistor unit 15
And 16 are alternately arranged two by two to form a semiconductor device. The units 15 and 16 are arranged at intervals of about 30 μm. The transistor units 15 and 16
An active region of a semiconductor device, the sum of the areas of which is proportional to the maximum allowable current of the semiconductor device.

【００２８】図４は図１のＩ−Ｉ方向の断面図である。
本発明の第１の実施の形態に係る半導体装置には、ｐ＋
型半導体基板７の上にｐ型エピタキシャル成長層２０
と、ｐ ＋型ソース領域１９が形成されている。成長層２
０の表面を含む領域にｎ型ドレイン領域２１が形成さ
れ、成長層２０とｐ＋型ソース領域１９の両方の表面を
含む領域にｎ型ソース領域２２と２３が形成されてい
る。ドレイン領域２１とソース領域２２、２３で挟まれ
た成長層２０の表面の上に面接触するようにゲート絶縁
膜２４が形成され、ゲート絶縁膜２４の上にゲート電極
（制御電極）２が配置されている。ゲート絶縁膜２４と
ゲート電極２の側面と、ゲート電極２、ドレイン領域２
１とソース領域２２と２３の上に第１の層間絶縁膜２５
が配置される。第１の主電極（ドレイン電極）３は、ド
レイン領域２１の表面上に面接触し、絶縁膜２５の側壁
と上面に接するように配置される。第２の主電極（ソー
ス電極）１は、ソース領域１９と２２と２３の表面上に
面接触し、絶縁膜２５の側壁と上面に接するように配置
される。絶縁膜２５、ドレイン電極３とソース電極１の
上に第２の層間絶縁膜２６が配置される。絶縁膜２６の
上には第１の主電極用の引き出し電極４が配置される。
絶縁膜２６と引き出し電極４の上にはパッシベーション
膜２７が配置される。ソース電極用ボンディングパッド
は半導体基板表面には形成されず、ソース領域２２、２
３への電流は、基板７の裏面から基板７、ソース領域１
９、次に、ソース電極１を経由してソース領域２２、２
３に注入される。FIG. 4 is a sectional view taken along the line II of FIG.
The semiconductor device according to the first embodiment of the present invention includes p+
P-type epitaxial growth layer 20 on p-type semiconductor substrate 7
And p +A mold source region 19 is formed. Growth layer 2
N-type drain region 21 is formed in a region including the surface of
And the growth layer 20 and p+Clean both surfaces of the mold source region 19
N-type source regions 22 and 23 are formed in
You. Sandwiched between the drain region 21 and the source regions 22 and 23
Gate insulation to make surface contact on the surface of grown layer 20
A film 24 is formed, and a gate electrode is formed on the gate insulating film 24.
(Control electrode) 2 is arranged. With the gate insulating film 24
Side surface of gate electrode 2, gate electrode 2, drain region 2
1 and a first interlayer insulating film 25 on source regions 22 and 23.
Is arranged. The first main electrode (drain electrode) 3 is
Surface contact is made on the surface of the rain region 21 and the side wall of the insulating film 25 is formed.
And are arranged so as to be in contact with the upper surface. Second main electrode (saw
Electrodes 1) on the surfaces of the source regions 19, 22 and 23
Arranged so as to be in surface contact and in contact with the side wall and upper surface of insulating film 25
Is done. The insulating film 25, the drain electrode 3 and the source electrode 1
A second interlayer insulating film 26 is disposed thereon. Of the insulating film 26
A lead electrode 4 for the first main electrode is arranged on the upper side.
Passivation on insulating film 26 and lead electrode 4
A membrane 27 is disposed. Bonding pad for source electrode
Are not formed on the surface of the semiconductor substrate.
3 flows from the back surface of the substrate 7 to the substrate 7 and the source region 1.
9, then, via the source electrode 1, the source regions 22, 2
3 injected.

【００２９】図５は図１のII−II方向の断面図である。
本発明の実施例１に係る半導体装置には、ｐ＋型半導体
基板７の上にｐ型エピタキシャル成長層２０が形成され
ている。成長層２０の表面を含む領域にｎ型ドレイン領
域２１が形成されている。ドレイン領域２１で挟まれた
成長層２０の表面の上にトランジスタ・ユニット分離用
絶縁膜２８と３８が配置される。絶縁膜２８と３８は基
板７と電極２と３の間の寄生容量を低減させる効果があ
る。絶縁膜２８の上に制御電極２が配置される。制御電
極２、絶縁膜２８と３８とドレイン領域２１の上に第１
の層間絶縁膜２５が配置される。ドレイン電極３は、ド
レイン領域２１の表面上に面接触し、絶縁膜２５の側壁
と上面に接するように配置される。制御電極の第１の引
き出し電極１４は、制御電極２の表面上に面接触し、絶
縁膜２５の側壁と上面に接するように配置される。絶縁
膜２５、ドレイン電極３と引き出し電極１４の上に第２
の層間絶縁膜２６が配置される。引き出し電極４は、ド
レイン電極３の表面上に面接触し、絶縁膜２６の側壁と
上面に接するように配置される。絶縁膜２６にはいわゆ
るスルーホールが設けられることになり、そのホールは
幅２０μｍの長方形にすればよい。制御電極の第２の引
き出し電極５は、引き出し電極１４の表面上に面接触
し、絶縁膜２６の側壁と上面に接するように配置され
る。こちらも絶縁膜２６にはいわゆるスルーホールが設
けられることになり、そのホールは幅２０μｍの長方形
にすればよい。引き出し電極４と５と絶縁膜２６の上に
はパッシベーション膜２７が配置される。FIG. 5 is a sectional view taken along the line II-II of FIG.
In the semiconductor device according to the first embodiment of the present invention, a p-type epitaxial growth layer 20 is formed on a p + -type semiconductor substrate 7. An n-type drain region 21 is formed in a region including the surface of the growth layer 20. Transistor / unit isolation insulating films 28 and 38 are arranged on the surface of growth layer 20 sandwiched between drain regions 21. The insulating films 28 and 38 have an effect of reducing the parasitic capacitance between the substrate 7 and the electrodes 2 and 3. The control electrode 2 is arranged on the insulating film 28. On the control electrode 2, the insulating films 28 and 38 and the first
Is disposed. The drain electrode 3 is arranged so as to be in surface contact with the surface of the drain region 21 and to be in contact with the side wall and the upper surface of the insulating film 25. The first lead electrode 14 of the control electrode is arranged so as to be in surface contact with the surface of the control electrode 2 and to be in contact with the side wall and the upper surface of the insulating film 25. A second layer is formed on the insulating film 25, the drain electrode 3 and the extraction electrode 14.
Is disposed. The extraction electrode 4 is arranged so as to be in surface contact with the surface of the drain electrode 3 and to be in contact with the side wall and the upper surface of the insulating film 26. A so-called through hole is provided in the insulating film 26, and the hole may be a rectangle having a width of 20 μm. The second extraction electrode 5 of the control electrode is arranged so as to be in surface contact with the surface of the extraction electrode 14 and to be in contact with the side wall and the upper surface of the insulating film 26. Also here, a so-called through hole is provided in the insulating film 26, and the hole may be formed in a rectangle having a width of 20 μm. A passivation film 27 is disposed on the extraction electrodes 4 and 5 and the insulating film 26.

【００３０】このように、本発明の実施例１に係る半導
体装置においては、図３のトランジスタ・ユニット１５
と１６の間にボンディングパッド７５と７６を配置して
いないので、ボンディングパッド７５と７６の配置位置
に影響されることなくユニット１５と１６の配置等の設
計変更が可能である。ユニット１５と１６が配置される
領域の最外郭から、引き出し電極４と５によりこの最外
郭の外側にパッド７５と７６を引き出している。As described above, in the semiconductor device according to the first embodiment of the present invention, the transistor unit 15 shown in FIG.
Since the bonding pads 75 and 76 are not arranged between the units 15 and 16, the design of the units 15 and 16 can be changed without being affected by the arrangement positions of the bonding pads 75 and 76. The pads 75 and 76 are drawn out of the outermost region of the region where the units 15 and 16 are arranged by the lead electrodes 4 and 5 to the outside of the outermost region.

【００３１】なお、ユニット１５、１６内のセル・トラ
ンジスタ１７、１８において、特に、ユニット１５、１
６の左右両端に位置するセル１７、１８において、パッ
ド７５あるいは７６との距離が大きく異なってしまう。
この距離の差による電気抵抗の差が生じてしまう。しか
し、ユニット１５、１６の構造に変更することなく、こ
の抵抗の差を生じさせる引き出し電極４と５の櫛状の歯
の部分の電極の厚さと幅を大きくすることができるの
で、抵抗の差をトランジスタ動作の均一性が確保できる
まで低減することができる。また、引き出し電極４と５
の櫛状の歯の形状をパッド７５、７６に近ずく程太くす
ることにより、歯のどの部分においても電流密度を一定
値以下たとえば１×１０５Ａ／ｃｍ２以下にできるので
装置の信頼性を高く保つことができる。また、第１の主
電極３の櫛状の歯の長さ（図３のｄ７）を５０μｍと短
くすることで、高周波特性を向上すると共に電極３の電
流密度が１×１０５Ａ／ｃｍ２以下に抑えられ装置の信
頼性が確保できる。In the cell transistors 17 and 18 in the units 15 and 16, especially the units 15, 1
The distance between the cells 17 and 18 located at the left and right ends of the pad 6 and the pads 75 or 76 is greatly different.
The difference in the electric resistance is caused by the difference in the distance. However, without changing the structure of the units 15 and 16, the thickness and width of the comb-like tooth portions of the extraction electrodes 4 and 5, which cause this difference in resistance, can be increased. Can be reduced until uniformity of transistor operation can be ensured. Also, the extraction electrodes 4 and 5
By increasing the shape of the comb-like teeth closer to the pads 75 and 76, the current density can be reduced to a certain value or less, for example, 1 × 10 5 A / cm 2 or less at any part of the teeth, so that the reliability of the device is improved. Can be kept high. Further, by shortening the length of the comb-like teeth (d7 in FIG. 3) of the first main electrode 3 to 50 μm, the high-frequency characteristics are improved and the current density of the electrode 3 is reduced to 1 × 10 5 A / cm 2. Therefore, the reliability of the apparatus can be secured.

【００３２】さらに高周波特性を向上させるために、ド
レイン・ソース間距離ｄ２とｄ３を微細化する場合を考
える。この距離ｄ２とｄ３の微細化によりセル１７、１
８の幅は狭くなり、必然的に第１の主電極３の櫛状の歯
の幅ｄ５が狭くなるので、信頼性確保の為に電流密度を
上記の範囲以下に抑えるために歯の長さｄ７を短くしな
ければならない。一方、総電流量も増やさないまでも微
細化前の値を維持したい。そこで、歯の幅ｄ５が狭くな
った分、歯の数等を増やしてユニット１５、１６の横の
長さｄ６を微細化前後で同程度にし、歯の長さｄ７が短
くなった分、ユニット１５、１６の数等を増やして全長
ｄ８を微細化前後で同程度にする。このように微細化の
前後で、ユニットの配置される領域は横幅ｄ６、縦幅ｄ
８の方形の領域で変更させる必要がなく。トランジスタ
の活性領域も同等な面積を確保できており、同等な許容
電流を確保できている。従って、パッド７５、７６の配
置や個数を変更する必要がなく、半導体装置を大きくし
なくてすむ。よって、パッケージの設計の変更もしなく
てよくなる。To further improve the high frequency characteristics, consider the case where the distances d2 and d3 between the drain and the source are reduced. By miniaturizing the distances d2 and d3, cells 17, 1
8, the width d5 of the comb-shaped teeth of the first main electrode 3 is inevitably narrowed, and the length of the teeth is controlled to keep the current density within the above range for ensuring reliability. d7 must be shortened. On the other hand, it is desired to maintain the value before miniaturization without increasing the total current amount. Therefore, the width d5 of the teeth is reduced, the number of teeth is increased, and the lateral length d6 of the units 15 and 16 is made the same before and after miniaturization. The total length d8 is made the same before and after miniaturization by increasing the number of 15, 16 and the like. As described above, before and after the miniaturization, the area where the units are arranged has a horizontal width d6 and a vertical width d6.
There is no need to change it in the square area of 8. The active area of the transistor can secure the same area, and the same allowable current can be secured. Therefore, there is no need to change the arrangement and number of the pads 75 and 76, and the semiconductor device does not need to be large. Therefore, there is no need to change the package design.

【００３３】次に、本発明の実施例１に係る半導体装置
の製造方法について説明する。製造方法は図６乃至図９
の断面図を用いて説明するが、図中の（ａ）は図１のI-
I方向の断面図であり、（ｂ）はII-II方向の断面図であ
る。Next, a method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described. The manufacturing method is shown in FIGS.
1 will be described with reference to the cross-sectional view of FIG.
It is sectional drawing of I direction, (b) is sectional drawing of II-II direction.

【００３４】（イ）まず、ｐ＋型半導体基板７の上にｐ
型エピタキシャル成長層２０を形成する。成長層２０の
形成は、材料ガスにジシラン（Ｓｉ２Ｈ６）とジボラン
（Ｂ ２Ｈ６）を用いシリコン基板７の温度を６００℃以
上１２００℃以下に加熱した化学気相成長（ＣＶＤ）法
によりｐ型シリコン膜を成膜すればよい。(A) First, p+P on the semiconductor substrate 7
The epitaxial growth layer 20 is formed. Of the growth layer 20
The formation is performed by using disilane (Si2H6) And diborane
(B 2H6) To raise the temperature of the silicon substrate 7 to 600 ° C. or less.
Chemical vapor deposition (CVD) method heated to 1200 ° C or lower
May be used to form a p-type silicon film.

【００３５】次に、図６（ａ）に示すように、ｐ＋型ソ
ース領域１９を形成する。フォトレジスト膜を成長膜２
０の上の領域１９を形成する以外の場所に形成する。レ
ジスト膜をマスクにボロンイオン（Ｂ＋）を成長膜２０
と基板７に注入する。熱処理を行いボロンイオンを活性
化させる。図６（ｂ）のように、ユニット分離用絶縁膜
２８、３８を選択酸化（ＬＯＣＯＳ）法により形成す
る。Next, as shown in FIG. 6A, ap + type source region 19 is formed. Photoresist film is grown 2
It is formed in a place other than the area 19 above 0. Boron ions (B + ) are grown using the resist film as a mask.
Is injected into the substrate 7. Heat treatment is performed to activate boron ions. As shown in FIG. 6B, the unit isolation insulating films 28 and 38 are formed by a selective oxidation (LOCOS) method.

【００３６】（ロ）ゲート絶縁膜２４を酸素雰囲気中で
７００℃以上１０００℃以下の基板温度の熱酸化により
成膜する。次に、ゲート電極２となる高融点金属例えば
モリビデン（Ｍｏ）、タングステン（Ｗ）、チタン（Ｔ
ｉ）、タンタル（Ｔａ）とこれら金属の窒化物をスパッ
タリングや反応性スパッタリングにより成膜する。次
に、フォトエッチングプロセス（ＰＥＰ）により、図７
（ａ）のようにゲート電極２とゲート絶縁膜２４を形成
する。フォトレジスト２９をｐ＋型ソース領域１９の上
に形成する。このレジスト２９とゲート電極２をマスク
として成長層２０とｐ＋型ソース領域１９にリンイオン
（Ｐ＋）をイオン注入する。熱処理を行い打ち込んだイ
オンの活性化を行い、図７（ａ）と（ｂ）のようにｎ型
ドレイン領域２１とｎ型ソース領域２２、２３を形成す
る。(B) The gate insulating film 24 is formed by thermal oxidation at a substrate temperature of 700 ° C. to 1000 ° C. in an oxygen atmosphere. Next, a high melting point metal such as molybdenum (Mo), tungsten (W), titanium (T
i), tantalum (Ta) and nitrides of these metals are formed by sputtering or reactive sputtering. Next, FIG. 7 is obtained by a photo etching process (PEP).
The gate electrode 2 and the gate insulating film 24 are formed as shown in FIG. A photoresist 29 is formed on the p + type source region 19. Using the resist 29 and the gate electrode 2 as a mask, phosphorus ions (P + ) are implanted into the growth layer 20 and the p + -type source region 19. The heat treatment is performed to activate the implanted ions to form an n-type drain region 21 and n-type source regions 22 and 23 as shown in FIGS. 7A and 7B.

【００３７】（ハ）第１層間絶縁膜２５として、原料ガ
スにテトラエチルオルトシリケイト（ＴＥＯＳ：Ｓｉ
（ＯＣＨ２ＣＨ３）４）とトリメチルフォスフェート
（ＴＭＰ：ＰＯ（ＯＣＨ３）３）を用い基板温度４００
℃以上７００℃以下の減圧の熱ＣＶＤ法によりリンガラ
ス（ＰＳＧ）膜を成膜する。次に、図８（ａ）と（ｂ）
に示すように絶縁膜２５にＰＥＰを用いてドレイン領域
２１とソース領域１９、２２、２３の上にスルーホール
を形成する。(C) As the first interlayer insulating film 25, tetraethyl orthosilicate (TEOS: Si
(OCH 2 CH 3 ) 4 ) and trimethyl phosphate (TMP: PO (OCH 3 ) 3 ) and a substrate temperature of 400
A phosphorus glass (PSG) film is formed by a thermal CVD method at a reduced pressure of 700C or higher and 700C or lower. Next, FIGS. 8A and 8B
As shown in (1), through holes are formed on the drain region 21 and the source regions 19, 22, and 23 by using PEP for the insulating film 25.

【００３８】（ニ）電極１、３と１４用に、チタンナイ
トライド（ＴｉＮ）とアルミニウム（Ａｌ）の積層膜を
反応性スパッタリングとスパッタリング法により成膜す
る。次に、積層膜にＰＥＰを用いて電極１、３と１４を
形成する。このときスルーホール内には積層膜が埋め込
まれる。(D) For the electrodes 1, 3 and 14, a laminated film of titanium nitride (TiN) and aluminum (Al) is formed by reactive sputtering and sputtering. Next, electrodes 1, 3, and 14 are formed using PEP for the laminated film. At this time, the laminated film is buried in the through hole.

【００３９】第２層間絶縁膜２６として、原料ガスにＴ
ＥＯＳと酸素（Ｏ２）を用い基板温度３００℃以上５０
０℃以下のプラズマＣＶＤ法によりシリコン酸化膜を成
膜する。次に、図９（ｂ）に示すように絶縁膜２６にＰ
ＥＰを用いて電極３と１４の上にスルーホールを形成す
る。As the second interlayer insulating film 26, T
Using EOS and oxygen (O 2 ), the substrate temperature is 300 ° C. or more and 50
A silicon oxide film is formed by a plasma CVD method at 0 ° C. or lower. Next, as shown in FIG.
Through holes are formed on the electrodes 3 and 14 using EP.

【００４０】（ホ）電極４と５とパッド７５と７６用
に、チタンナイトライドとアルミニウムの積層膜を反応
性スパッタリングとスパッタリング法により成膜する。
このときスルーホール内には積層膜が埋め込まれる。次
に、積層膜にＰＥＰを用いて電極４と５とパッド７５と
７６を形成する。(E) A laminated film of titanium nitride and aluminum is formed for the electrodes 4 and 5 and the pads 75 and 76 by reactive sputtering and sputtering.
At this time, the laminated film is buried in the through hole. Next, the electrodes 4 and 5 and the pads 75 and 76 are formed using PEP for the laminated film.

【００４１】図４と図５に示すように、パッシベーショ
ン膜２７として、原料ガスにＴＥＯＳ、ＴＭＰと酸素を
用い基板温度３００℃以上５００℃以下のプラズマＣＶ
Ｄ法によるリンガラスと、原料ガスにシラン（Ｓｉ
Ｈ４）とアンモニア（ＮＨ３）を用い基板温度３００℃
以上５００℃以下のプラズマＣＶＤ法によるシリコン窒
化膜の積層膜を成膜する。パッド７５と７６の上に成膜
された積層膜をＰＥＰにより除去する。As shown in FIGS. 4 and 5, as the passivation film 27, a plasma CV having a substrate temperature of 300 ° C. to 500 ° C. using TEOS, TMP and oxygen as source gases.
Phosphorus glass by the D method and silane (Si
Substrate temperature 300 ° C. using H 4 ) and ammonia (NH 3 )
A stacked film of a silicon nitride film is formed by a plasma CVD method at a temperature of 500 ° C. or less. The laminated film formed on the pads 75 and 76 is removed by PEP.

【００４２】（ヘ）最後に、半導体基板７の裏面を研磨
し、半導体装置毎のペレットにダイシングする。リード
９と側壁１２とが固定されたペレット実装基板１１に、
ペレットの半導体基板７をマウント材１０で接着する。
次に、リード９とパッド７５、７６間をワイヤー８でワ
イヤーボンディングする。蓋１３を側壁１２に接着す
る。(F) Finally, the back surface of the semiconductor substrate 7 is polished and diced into pellets for each semiconductor device. On the pellet mounting substrate 11 on which the leads 9 and the side walls 12 are fixed,
The pellet semiconductor substrate 7 is bonded with the mounting material 10.
Next, the wire 8 is wire-bonded between the lead 9 and the pads 75 and 76. The lid 13 is bonded to the side wall 12.

【００４３】（実施例２）図１０は、本発明の実施例２
に係る半導体装置の上方からの透視図である。この半導
体装置はバイポーラトランジスタである。半導体装置内
の第１の主電極用ボンディングパッド７５、第１の主電
極用の引き出し電極４、制御電極用ボンディングパッド
７６と制御電極用の引き出し電極５の位置関係と形状
は、実施例１に係る半導体装置と同じである。引き出し
電極４と５の奥側に、引き出し電極５に接続する制御電
極２と、引き出し電極４に接続する第１の主電極３が配
置されている。(Embodiment 2) FIG. 10 shows Embodiment 2 of the present invention.
1 is a perspective view from above of a semiconductor device according to FIG. This semiconductor device is a bipolar transistor. The positional relationship and the shape of the first main electrode bonding pad 75, the first main electrode lead electrode 4, the control electrode bonding pad 76, and the control electrode lead electrode 5 in the semiconductor device are the same as those in the first embodiment. This is the same as the semiconductor device. A control electrode 2 connected to the extraction electrode 5 and a first main electrode 3 connected to the extraction electrode 4 are arranged behind the extraction electrodes 4 and 5.

【００４４】図１１も、本発明の実施例２に係る半導体
装置の上方からの透視図である。図１１では図１０のボ
ンディングパッド７５と７６、引き出し電極４と５をも
透視したとして省略して記載している。半導体基板の上
の上方に櫛状の歯を下に向けた制御電極２が配置され、
制御電極２の櫛状の背部の表面は図１０の引き出し電極
５の歯の部分の裏面と接続している。制御電極２の歯の
部分を挿むように第１の主電極３の櫛状の歯の部分が配
置される。第１の主電極３には上下両方向に両刃の櫛状
の歯が配置されている。第１の主電極３の櫛状の背の下
方には、上記の制御電極２から第１の主電極３の櫛状の
背までの配置を第１の主電極３の櫛状の背で折り返した
ように配置される。同様に、中央部の制御電極２の下方
には、最上部の制御電極２から中央部の制御電極２まで
の配置を中央部の制御電極２で折り返したように配置さ
れる。第１の主電極３の櫛状の背部の表面は図１０の引
き出し電極４の歯の部分の裏面と接続している。FIG. 11 is a perspective view from above of a semiconductor device according to the second embodiment of the present invention. In FIG. 11, the bonding pads 75 and 76 and the extraction electrodes 4 and 5 in FIG. A control electrode 2 with comb-like teeth facing down is arranged above the semiconductor substrate,
The front surface of the comb-shaped back portion of the control electrode 2 is connected to the back surface of the tooth portion of the extraction electrode 5 in FIG. The comb-shaped teeth of the first main electrode 3 are arranged so as to insert the teeth of the control electrode 2. The first main electrode 3 is provided with comb-shaped teeth having both edges in both the upper and lower directions. Below the comb-like spine of the first main electrode 3, the arrangement from the control electrode 2 to the comb-like spine of the first main electrode 3 is folded back by the comb-like spine of the first main electrode 3. Are arranged as shown. Similarly, below the central control electrode 2, the arrangement from the uppermost control electrode 2 to the central control electrode 2 is arranged so as to be folded back by the central control electrode 2. The surface of the comb-shaped back portion of the first main electrode 3 is connected to the back surface of the tooth portion of the extraction electrode 4 in FIG.

【００４５】第１の主電極３の櫛状の歯と制御電極２の
櫛状の歯の紙面奥の方向の半導体基板にはトランジスタ
が形成されている。トランジスタを構成する最小の領域
は、セル・トランジスタ３７と３８である。セル・トラ
ンジスタ３７と３８とは線対称の関係にあり、トランジ
スタとしては同等の電気特性を発揮する。このセル・ト
ランジスタ３７と３８を交互に１２個ずつ並べることで
トランジスタ・ユニット１５と１６が構成されている。
トランジスタ・ユニット１５と１６とは、配置される位
置が１８０度回転しているだけで全く同一の構造をして
いる。トランジスタ・ユニット１５と１６が交互に２つ
ずつ並べられて半導体装置が構成されている。ユニット
１５と１６の間隔は３０μｍ程度離して配列する。Transistors are formed on the semiconductor substrate in the direction away from the paper of the comb-shaped teeth of the first main electrode 3 and the comb-shaped teeth of the control electrode 2. The smallest area constituting the transistor is the cell transistors 37 and 38. The cell transistors 37 and 38 have a line-symmetric relationship, and exhibit the same electrical characteristics as transistors. Transistor units 15 and 16 are configured by alternately arranging 12 cell transistors 37 and 38 each.
The transistor units 15 and 16 have exactly the same structure except that the arrangement positions are rotated by 180 degrees. A semiconductor device is constituted by alternately arranging two transistor units 15 and 16 alternately. The units 15 and 16 are arranged at intervals of about 30 μm.

【００４６】トランジスタ・ユニット１５と１６は、半
導体装置の活性領域であり、その面積の総和は半導体装
置の最大の許容電流量に比例する。The transistor units 15 and 16 are active regions of the semiconductor device, and the total area thereof is proportional to the maximum allowable current of the semiconductor device.

【００４７】図１２は図１０のＩ−Ｉ方向の断面図であ
る。本発明の実施例２に係る半導体装置には、ｎ＋型半
導体基板３１の上にｎ−型エピタキシャル成長層３２が
配置され、基板３１と成長層３２はコレクタ領域として
機能する。成長層３２の上にはｐ型ベース領域３３が形
成されている。ベース領域３３の表面の一部を含む領域
にｎ＋型エミッタ領域３４が形成されている。ベース領
域３３とエミッタ領域３４の上に第１の層間絶縁膜２５
が配置される。第１の主電極（エミッタ電極）３は、エ
ミッタ領域３４の表面上に面接触し、絶縁膜２５の側壁
と上面に接するように配置される。制御電極（ベース電
極）２は、ベース領域３３の表面上に面接触し、絶縁膜
２５の側壁と上面に接するように配置される。絶縁膜２
５、エミッタ電極３とベース電極２の上に第２の層間絶
縁膜２６が配置される。絶縁膜２６の上には第１の主電
極（エミッタ電極）用の引き出し電極４が配置される。
絶縁膜２６と引き出し電極４の上にはパッシベーション
膜２７が配置される。FIG. 12 is a sectional view taken along the line II of FIG. In the semiconductor device according to the second embodiment of the present invention, an n − -type epitaxial growth layer 32 is disposed on an n + -type semiconductor substrate 31, and the substrate 31 and the growth layer 32 function as a collector region. On the growth layer 32, a p-type base region 33 is formed. An n + -type emitter region 34 is formed in a region including a part of the surface of the base region 33. A first interlayer insulating film 25 over the base region 33 and the emitter region 34;
Is arranged. The first main electrode (emitter electrode) 3 is arranged so as to be in surface contact with the surface of the emitter region 34 and to be in contact with the side wall and the upper surface of the insulating film 25. The control electrode (base electrode) 2 is arranged so as to be in surface contact with the surface of the base region 33 and to be in contact with the side wall and the upper surface of the insulating film 25. Insulating film 2
5. A second interlayer insulating film 26 is disposed on the emitter electrode 3 and the base electrode 2. A lead electrode 4 for a first main electrode (emitter electrode) is arranged on the insulating film 26.
A passivation film 27 is disposed on the insulating film 26 and the extraction electrode 4.

【００４８】図１３は図１０のII−II方向の断面図であ
る。本発明の実施例２に係る半導体装置には、基板３１
の上に成長層３２とベース領域３３が形成されている。
ベース領域３３の表面を含む領域にエミッタ領域３４が
形成される。エミッタ領域３４で挟まれたベース領域３
３の表面の上にトランジスタ・ユニット分離用絶縁膜２
８と３８が配置される。絶縁膜２８と３８はベース領域
３３と電極２と３の間の寄生容量を低減させる効果があ
る。絶縁膜２８と３８とエミッタ領域３４の上に第１の
層間絶縁膜２５が配置される。エミッタ電極３は、エミ
ッタ領域３４の表面上に面接触し、絶縁膜２５の側壁と
上面に接するように配置される。ベース電極２は、絶縁
膜２５あるいは２８の上面に接するように配置される。
絶縁膜２５、ベース電極３とエミッタ電極３の上に第２
の層間絶縁膜２６が配置される。引き出し電極４は、エ
ミッタ電極３の表面上に面接触し、絶縁膜２６の側壁と
上面に接するように配置される。絶縁膜２６にはいわゆ
るスルーホールが設けられることになり、そのホールは
幅２０μｍの長方形にすればよい。ベース電極の引き出
し電極５は、ベース電極２の表面上に面接触し、絶縁膜
２６の側壁と上面に接するように配置される。こちらも
絶縁膜２６にはいわゆるスルーホールが設けられること
になり、そのホールは幅２０μｍの長方形にすればよ
い。引き出し電極４と５と絶縁膜２６の上にはパッシベ
ーション膜２７が配置される。FIG. 13 is a sectional view taken along the line II-II of FIG. The semiconductor device according to the second embodiment of the present invention includes a substrate 31
A growth layer 32 and a base region 33 are formed thereon.
An emitter region 34 is formed in a region including the surface of base region 33. Base region 3 sandwiched between emitter regions 34
3 is an insulating film for transistor / unit isolation on the surface of 3
8 and 38 are arranged. The insulating films 28 and 38 have an effect of reducing the parasitic capacitance between the base region 33 and the electrodes 2 and 3. A first interlayer insulating film 25 is arranged on insulating films 28 and 38 and emitter region 34. Emitter electrode 3 is arranged so as to be in surface contact with the surface of emitter region 34 and to be in contact with the side wall and upper surface of insulating film 25. The base electrode 2 is arranged so as to be in contact with the upper surface of the insulating film 25 or 28.
A second insulating film 25 is formed on the base electrode 3 and the emitter electrode 3.
Is disposed. The extraction electrode 4 is arranged so as to be in surface contact with the surface of the emitter electrode 3 and to be in contact with the side wall and the upper surface of the insulating film 26. A so-called through hole is provided in the insulating film 26, and the hole may be a rectangle having a width of 20 μm. The extraction electrode 5 of the base electrode is arranged so as to be in surface contact with the surface of the base electrode 2 and to be in contact with the side wall and the upper surface of the insulating film 26. Also here, a so-called through hole is provided in the insulating film 26, and the hole may be formed in a rectangle having a width of 20 μm. A passivation film 27 is disposed on the extraction electrodes 4 and 5 and the insulating film 26.

【００４９】このように、本発明の実施例２に係る半導
体装置においては、図１１のトランジスタ・ユニット１
５と１６の間にボンディングパッド７５と７６を配置し
ていないので、ボンディングパッド７５と７６の配置位
置に影響されることなくユニット１５と１６の配置等の
設計変更が可能である。ユニット１５と１６が配置され
る領域の最外郭から、引き出し電極４と５によりこの最
外郭の外側にパッド７５と７６を引き出しているからで
ある。As described above, in the semiconductor device according to the second embodiment of the present invention, the transistor unit 1 shown in FIG.
Since the bonding pads 75 and 76 are not disposed between 5 and 16, the design of the units 15 and 16 can be changed without being affected by the positions of the bonding pads 75 and 76. This is because the pads 75 and 76 are drawn out of the outermost area of the region where the units 15 and 16 are arranged by the extraction electrodes 4 and 5 to the outside of the outermost area.

【００５０】なお、ユニット１５、１６内のセル・トラ
ンジスタ１７、１８において、特に、ユニット１５、１
６の左右両端に位置するセル１７、１８において、パッ
ド７５あるいは７６との距離が大きく異なってしまう。
この距離の差による電気抵抗の差は、ユニット１５、１
６の構造に変更することなく、この抵抗の差を生じさせ
る引き出し電極４と５の櫛状の歯の部分の電極の厚さと
幅を大きくすることで、トランジスタ動作の均一性が確
保できるまで低減することができる。また、引き出し電
極４と５の櫛状の歯の形状をパッド７５、７６に近ずく
程太くすることにより、歯のどの部分においても電流密
度を一定値以下たとえば１×１０５Ａ／ｃｍ２以下にで
きるので装置の信頼性を高く保つことができる。It should be noted that, in the cell transistors 17 and 18 in the units 15 and 16,
The distance between the cells 17 and 18 located at the left and right ends of the pad 6 and the pads 75 or 76 is greatly different.
The difference in electrical resistance due to this difference in distance is equal to the units 15, 1
By increasing the thickness and width of the comb-shaped tooth portions of the extraction electrodes 4 and 5 that cause this difference in resistance without changing to the structure of 6, the uniformity of transistor operation can be reduced. can do. Further, by increasing the shape of the comb-like teeth of the extraction electrodes 4 and 5 toward the pads 75 and 76, the current density can be reduced to a certain value or less, for example, 1 × 10 5 A / cm 2 or less in any part of the teeth. Therefore, the reliability of the apparatus can be kept high.

【００５１】また、エミッタ電極３とベース電極２の櫛
状の歯の長さ（図１１のｄ２７）を５０μｍと短くする
ことで、高周波特性を向上すると共に電極３の電流密度
が１×１０５Ａ／ｃｍ２以下に抑えられ装置の信頼性が
確保できる。Further, by shortening the length of the comb-like teeth (d27 in FIG. 11) of the emitter electrode 3 and the base electrode 2 to 50 μm, the high frequency characteristics are improved and the current density of the electrode 3 is reduced to 1 × 10 5. A / cm 2 or less, ensuring the reliability of the device.

【００５２】さらに高周波特性を向上させるために、エ
ミッタ・ベース間距離ｄ２２とｄ２３を微細化する場合
を考える。この距離ｄ２２とｄ２３の微細化によりセル
１７、１８の幅は狭くなり、必然的にエミッタ電極３の
櫛状の歯の幅ｄ２５が狭くなるので、信頼性確保の為に
電流密度を上記の範囲以下に抑えるために歯の長さｄ２
７を短くしなければならない。一方、半導体装置全体に
流せる総電流量も増やさないまでも微細化前の値を維持
したい。そこで、歯の幅ｄ２５が狭くなった分、歯の数
等を増やしてユニット１５、１６の横の長さｄ２６を微
細化前後で同程度にし、歯の長さｄ２７が短くなった
分、ユニット１５、１６の数等を増やして全長ｄ２８を
微細化前後で同程度にする。このように微細化の前後
で、ユニットの配置される領域は横幅ｄ２６、縦幅ｄ２
８の方形の領域で変更させる必要がなく。トランジスタ
の活性領域も同等な面積を確保できており、同等な許容
電流を確保できる。従って、パッド７５、７６の配置や
個数を変更する必要がなく、半導体装置を大きくしなく
てすむ。よって、パッケージの設計の変更も不要であ
る。To further improve the high frequency characteristics, consider the case where the emitter-base distances d22 and d23 are made finer. As the distances d22 and d23 become finer, the width of the cells 17 and 18 becomes narrower, and the width d25 of the comb-like teeth of the emitter electrode 3 becomes inevitably narrower. To minimize the length of the teeth d2
7 must be shortened. On the other hand, it is desired to maintain the value before miniaturization without increasing the total amount of current that can flow through the entire semiconductor device. Therefore, the width d25 of the teeth is reduced, the number of teeth is increased, and the lateral length d26 of the units 15 and 16 is made the same before and after the miniaturization, and the unit d27 is shortened by the shortened tooth length d27. The total length d28 is made the same before and after miniaturization by increasing the number and the like of 15, 16 and the like. As described above, before and after the miniaturization, the area where the units are arranged has a horizontal width d26 and a vertical width d2.
There is no need to change it in the square area of 8. The active area of the transistor can also have the same area, and can have the same allowable current. Therefore, there is no need to change the arrangement and number of the pads 75 and 76, and the semiconductor device does not need to be large. Therefore, there is no need to change the package design.

【００５３】（実施例３）図１４は、本発明の実施例３
に係る半導体装置の上方からの透視図である。この半導
体装置は電界効果トランジスタ（ＦＥＴ）であり、本発
明の実施例１に係る半導体装置よりも高周波特性を向上
させるために、図３のドレイン・ソース間距離ｄ２とｄ
３を微細化する等の設計変更をしている。半導体装置の
左側に第１の主電極用ボンディングパッド７５が上下方
向に２つ並べて配置され、右方向に伸びる３本の歯を有
する櫛状の第１の主電極用の引き出し電極４４がボンデ
ィングパッド７５に接続するように配置されている。３
本の歯はボンディングパッド７５に近くなる程太くな
る。半導体装置の右側に制御電極用ボンディングパッド
７６が上下方向に２つ並べて配置され、左方向に伸びる
４本の歯を有する櫛状の制御電極用の第２の引き出し電
極４５がボンディングパッド７６に接続するように配置
されている。４本の歯もボンディングパッド７６に近く
なる程太くなる。引き出し電極４４と４５の奥側に第２
の主電極４１と、引き出し電極４５に接続する制御電極
４２と、引き出し電極４４に接続する第１の主電極４３
が配置されている。(Embodiment 3) FIG. 14 shows Embodiment 3 of the present invention.
1 is a perspective view from above of a semiconductor device according to FIG. This semiconductor device is a field-effect transistor (FET). In order to improve high-frequency characteristics over the semiconductor device according to the first embodiment of the present invention, the distances d2 and d2 between the drain and the source in FIG.
Design changes such as miniaturization of 3 have been made. Two first main electrode bonding pads 75 are vertically arranged on the left side of the semiconductor device, and a comb-shaped first main electrode lead electrode 44 having three teeth extending rightward is used as a bonding pad. 75. Three
The closer the teeth are to the bonding pad 75, the thicker the teeth become. Two control electrode bonding pads 76 are arranged vertically on the right side of the semiconductor device, and a comb-shaped second lead-out electrode 45 having four teeth extending to the left is connected to the bonding pad 76. It is arranged to be. The four teeth also become thicker as they come closer to the bonding pad 76. The second on the back side of the extraction electrodes 44 and 45
Main electrode 41, a control electrode 42 connected to the extraction electrode 45, and a first main electrode 43 connected to the extraction electrode 44.
Is arranged.

【００５４】このように、引き出し電極４４、４５は、
図１の引き出し電極４、５に比べ櫛状の歯の本数が増え
てはいる。しかし、パッド７５と７６の数と配置位置は
変化させなくてよく、ペレットの大きさも著しく大きく
なることはないので、図２のパッケージがそのまま使用
できる。As described above, the extraction electrodes 44 and 45
Compared with the extraction electrodes 4 and 5 of FIG. 1, the number of comb-shaped teeth is increased. However, the number and arrangement of the pads 75 and 76 do not need to be changed, and the size of the pellet does not increase significantly, so that the package shown in FIG. 2 can be used as it is.

【００５５】図１５も、本発明の実施例３に係る半導体
装置の上方からの透視図である。図１５では図１４のボ
ンディングパッド７５と７６、引き出し電極４と５をも
透視したとして省略して記載している。図１５に記載さ
れた半導体装置は、図３と比較して同じ種類だけの構成
要素を有している。しかし、それらが小さくなったり数
が増えたりしている。以下に具体的に、半導体装置の高
周波特性を向上できる本発明の実施例３に係る半導体装
置の製造方法を説明する。FIG. 15 is a perspective view from above of a semiconductor device according to Embodiment 3 of the present invention. In FIG. 15, the bonding pads 75 and 76 and the extraction electrodes 4 and 5 in FIG. The semiconductor device illustrated in FIG. 15 has only the same types of components as compared to FIG. But they are getting smaller and larger. Hereinafter, a method for manufacturing a semiconductor device according to a third embodiment of the present invention that can improve the high-frequency characteristics of the semiconductor device will be specifically described.

【００５６】（イ）まず、図１６のステップＳ３のよう
にセル・トランジスタ設計を行う。そのために、まず、
ドレイン・ソース間距離ｄ１２とｄ１３を微細化する。(A) First, a cell transistor is designed as in step S3 of FIG. First of all,
The distances d12 and d13 between the drain and the source are reduced.

【００５７】（ロ）この距離ｄ１２とｄ１３の微細化に
よりセル・トランジスタ５７、５８の幅が狭くなり、ス
テップＳ５のように必然的に第１の主電極４３と制御電
極４２の櫛状の歯の幅ｄ１５とｄ１４を狭くする。この
ことにより、信頼性確保の為に電流密度を規定値以下の
範囲に抑えるために、ステップＳ６のように歯の長さ
（いわゆるフィンガー長）ｄ１７を短くする。(B) Due to the miniaturization of the distances d12 and d13, the widths of the cell transistors 57 and 58 are narrowed, and the comb-shaped teeth of the first main electrode 43 and the control electrode 42 are inevitably in step S5. Widths d15 and d14 are reduced. As a result, the tooth length (so-called finger length) d17 is shortened as in step S6 in order to suppress the current density to a range equal to or less than the specified value in order to ensure reliability.

【００５８】（ハ）一方、総電流量も増やさないまでも
微細化前の値を維持したい。そこで、まず、ステップＳ
２のようにトランジスタ・ユニットの設計を行う。すな
わちステップＳ７のように歯の幅ｄ１４とｄ１５が狭く
なった分、歯の数を増やしてユニット５５、５６の横の
長さｄ１６を微細化前後で同程度にしている。例えば第
１の主電極４３では６本から９本に増やしている。(C) On the other hand, it is desired to maintain the value before miniaturization without increasing the total current amount. Therefore, first, step S
Design the transistor unit as in 2. That is, as the width d14 and d15 of the teeth are reduced as in step S7, the number of teeth is increased to make the horizontal length d16 of the units 55 and 56 the same before and after the miniaturization. For example, the number of the first main electrodes 43 is increased from six to nine.

【００５９】（ニ）また、総電流量を維持するために、
ステップＳ１のようにトランジスタ・ユニットの配置を
する。すなわちステップＳ８のように歯の長さｄ１７が
短くなった分、ユニット５５、５６の数を増やして全長
ｄ１８を微細化前後で同程度にする。例えば図３から図
１５においてはユニットを４個から６個に増やしてい
る。(D) In order to maintain the total current,
The transistor units are arranged as in step S1. That is, the number of the units 55 and 56 is increased by an amount corresponding to the decrease in the tooth length d17 as in step S8, and the total length d18 is made equal before and after the miniaturization. For example, in FIGS. 3 to 15, the number of units is increased from four to six.

【００６０】このように微細化の前後で、ユニットの配
置される領域は横幅ｄ１６、縦幅ｄ１８の方形の領域で
変更しておらず、トランジスタの活性領域も同等な面積
を確保できており、同等な許容電流を確保できている。
従って、ステップＳ９のようにパッド７５、７６の配置
や個数を変更する必要がなく、半導体装置を大きさしな
くてすむ。よって、パッケージの設計の変更もしなくて
よくなる。As described above, before and after the miniaturization, the area in which the units are arranged is not changed from the rectangular area having the width d16 and the height d18, and the active area of the transistor can have the same area. The same allowable current can be secured.
Therefore, there is no need to change the arrangement and number of the pads 75 and 76 as in step S9, and the semiconductor device does not need to be large. Therefore, there is no need to change the package design.

【００６１】（その他の実施例）上記のように、本発明
は３つの実施例によって記載したが、この開示の一部を
なす論述及び図面はこの発明を限定するものであると理
解すべきではない。この開示から当業者には様々な代替
実施の形態、実施例及び運用技術が明らかとなろう。実
施例においてはＦＥＴとバイポーラトランジスタについ
て述べたが、表面に２端子以上の引き出し電極を有する
半導体装置であれば適用可能で、例えばサイリスタや静
電誘導型トランジスタであってもよい。したがって、本
発明の技術的範囲は上記の説明から妥当な特許請求の範
囲に係る発明特定事項によってのみ定められるものであ
る。(Other Embodiments) As described above, the present invention has been described with reference to the three embodiments. However, it should be understood that the description and drawings forming part of this disclosure limit the present invention. Absent. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art. In the embodiments, the FET and the bipolar transistor have been described. However, the present invention is applicable to any semiconductor device having two or more extraction electrodes on the surface, such as a thyristor or an electrostatic induction transistor. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

【００６２】[0062]

【発明の効果】以上説明したように、本発明によれば、
半導体装置を大きくしたりボンディングワイヤーを長く
したり電流密度を高くすることなしに、高周波高出力特
性を改善できる半導体装置を提供できる。As described above, according to the present invention,
A semiconductor device capable of improving high-frequency high-output characteristics without increasing the size of the semiconductor device, lengthening the bonding wire, or increasing the current density can be provided.

【００６３】また、本発明によれば、パッケージの設計
の変更なしに、高周波高出力特性を改善できる半導体装
置を提供できる。Further, according to the present invention, it is possible to provide a semiconductor device capable of improving high-frequency high-output characteristics without changing the package design.

【００６４】さらに、本発明によれば、半導体装置を大
きくしたりボンディングワイヤーを長くしたり電流密度
を高くすることなしに、高周波高出力特性を改善できる
半導体装置の製造方法を提供できる。Further, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of improving high-frequency high-output characteristics without increasing the size of the semiconductor device, lengthening the bonding wire, or increasing the current density.

【００６５】最後に、本発明によれば、パッケージの設
計の変更なしに、高周波高出力特性を改善できる半導体
装置の製造方法を提供できる。Finally, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of improving high-frequency high-output characteristics without changing the package design.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施例１に係る半導体装置の上方から
の透視図（その１）である。FIG. 1 is a top perspective view (part 1) of a semiconductor device according to a first embodiment of the present invention;

【図２】図２（ａ）は本発明の実施例１に係る半導体装
置の上方からの透視図（その２）で、（ｂ）はその断面
図である。FIG. 2A is a perspective view (part 2) from above of the semiconductor device according to the first embodiment of the present invention, and FIG. 2B is a cross-sectional view thereof.

【図３】本発明の実施例１に係る半導体装置の上方から
の透視図（その３）である。FIG. 3 is a perspective view (part 3) from above of the semiconductor device according to the first embodiment of the present invention;

【図４】本発明の実施例１に係る半導体装置の断面図
（その２）である。FIG. 4 is a sectional view (part 2) of the semiconductor device according to the first embodiment of the present invention;

【図５】本発明の実施例１に係る半導体装置の断面図
（その３）である。FIG. 5 is a sectional view (part 3) of the semiconductor device according to the first embodiment of the present invention;

【図６】本発明の実施例１に係る半導体装置の製造方法
を説明するための図（その１）である。（ａ）は図４の
断面図に対応し、（ｂ）は図５の断面図に対応する。FIG. 6 is a view (No. 1) for describing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. (A) corresponds to the cross-sectional view of FIG. 4, and (b) corresponds to the cross-sectional view of FIG.

【図７】本発明の実施例１に係る半導体装置の製造方法
を説明するための図（その２）である。（ａ）は図４の
断面図に対応し、（ｂ）は図５の断面図に対応する。FIG. 7 is a view (No. 2) for describing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. (A) corresponds to the cross-sectional view of FIG. 4, and (b) corresponds to the cross-sectional view of FIG.

【図８】本発明の実施例１に係る半導体装置の製造方法
を説明するための図（その３）である。（ａ）は図４の
断面図に対応し、（ｂ）は図５の断面図に対応する。FIG. 8 is a view (No. 3) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention. (A) corresponds to the cross-sectional view of FIG. 4, and (b) corresponds to the cross-sectional view of FIG.

【図９】本発明の実施例１に係る半導体装置の製造方法
を説明するための図（その４）である。（ａ）は図４の
断面図に対応し、（ｂ）は図５の断面図に対応する。FIG. 9 is a view (No. 4) for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention. (A) corresponds to the cross-sectional view of FIG. 4, and (b) corresponds to the cross-sectional view of FIG.

【図１０】本発明の実施例２に係る半導体装置の上方か
らの透視図（その１）である。FIG. 10 is a perspective view (part 1) of a semiconductor device according to a second embodiment of the present invention as seen from above.

【図１１】本発明の実施例２に係る半導体装置の上方か
らの透視図（その２）である。FIG. 11 is a perspective view (part 2) of the semiconductor device according to the second embodiment of the present invention as seen from above.

【図１２】本発明の実施例２に係る半導体装置の断面図
（その１）である。FIG. 12 is a sectional view (part 1) of a semiconductor device according to a second embodiment of the present invention;

【図１３】本発明の実施例２に係る半導体装置の断面図
（その２）である。FIG. 13 is a sectional view (part 2) of the semiconductor device according to the second embodiment of the present invention;

【図１４】本発明の実施例３に係る半導体装置の上方か
らの透視図（その１）である。FIG. 14 is a top perspective view (part 1) of a semiconductor device according to a third embodiment of the present invention;

【図１５】本発明の実施例３に係る半導体装置の上方か
らの透視図（その２）である。FIG. 15 is a perspective view (part 2) from above of a semiconductor device according to a third embodiment of the present invention.

【図１６】本発明の実施例３に係る半導体装置の製造方
法のフローチャート図である。FIG. 16 is a flowchart of the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

【図１７】従来の半導体装置の上方からの透視図であ
る。FIG. 17 is a perspective view from above of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１、４１、６１ 第２の主電極（ソース電極） ２、４２、６２ 制御電極（ゲート電極、ベース電極） ３、４３、６３ 第１の主電極（ドレイン電極、エミッ
タ電極） ４、４４、６４ 第１の主電極用の引き出し電極 ５、４５ 制御電極の第２の引き出し電極 ７ ｐ＋型半導体基板 ８ ボンディングワイヤ ９ リード １０ ペレット・マウント材 １１ ペレット実装基板 １２ 側壁 １３ 蓋 １４、５４ 制御電極の第１の引き出し電極 １５、１６、３５、３６、５５、５６ トランジスタ・
ユニット １７、１８、３７、３８、５７、５８ セル・トランジ
スタ １９ ｐ＋型ソース領域 ２０ ｐ型エピタキシャル成長層 ２１ ｎ型ドレイン領域 ２２、２３ ｎ型ソース領域 ２４ ゲート絶縁膜 ２５ 第１の層間絶縁膜 ２６ 第２の層間絶縁膜 ２７ パッシベーション膜 ２８ ユニット分離用絶縁膜 ２９ フォトレジスト ３１ ｎ＋型半導体基板（コレクタ領域） ３２ ｎ−型コレクタ領域 ３３ ｐ型ベース領域 ３４ ｎ＋型エミッタ領域 ６５、７５ 第１の主電極用ボンディングパッド ６６、７６ 制御電極用ボンディングパッド1, 41, 61 Second main electrode (source electrode) 2, 42, 62 Control electrode (gate electrode, base electrode) 3, 43, 63 First main electrode (drain electrode, emitter electrode) 4, 44, 64 Lead electrode for first main electrode 5, 45 Second lead electrode of control electrode 7 p + type semiconductor substrate 8 Bonding wire 9 Lead 10 Pellet mounting material 11 Pellet mounting substrate 12 Side wall 13 Lid 14, 54 Control electrode First extraction electrode 15, 16, 35, 36, 55, 56 Transistor
Unit 17, 18, 37, 38, 57, 58 Cell / transistor 19 p + type source region 20 p-type epitaxial growth layer 21 n-type drain region 22, 23 n-type source region 24 gate insulating film 25 first interlayer insulating film 26 Second interlayer insulating film 27 Passivation film 28 Unit separating insulating film 29 Photoresist 31 n + type semiconductor substrate (collector region) 32 n − type collector region 33 p type base region 34 n + type emitter region 65, 75 first Bonding pad for main electrode 66, 76 Bonding pad for control electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/73 Ｈ０１Ｌ 29/78 ３０１Ｘ Ｆターム(参考） 4M104 BB14 BB16 BB17 BB18 BB30 CC01 CC05 DD37 DD42 FF01 FF11 FF26 GG08 GG09 GG10 5F003 BA97 BF02 BH02 BH08 BH16 5F033 HH08 HH18 HH19 HH20 HH21 HH27 HH28 HH29 HH30 HH33 JJ01 JJ08 JJ33 KK01 KK08 KK18 KK19 KK20 KK27 KK28 KK29 KK30 KK33 MM05 MM13 NN03 NN07 PP15 PP16 QQ08 QQ09 QQ37 RR04 RR14 SS13 SS15 UU04 VV00 XX00 5F040 DA01 DA21 EC01 EC04 EC08 EC17 EH02 EH05 EJ01 EJ02 EJ07 EK01 FC05 5F044 AA02 EE02 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI theme coat ゛ (Reference) H01L 29/73 H01L 29/78 301X F-term (Reference) 4M104 BB14 BB16 BB17 BB18 BB30 CC01 CC05 DD37 DD42 FF01 FF11 FF26 GG08 GG09 GG10 5F003 BA97 BF02 BH02 BH08 BH16 5F033 HH08 HH18 HH19 HH20 HH21 HH27 HH28 HH29 HH30 HH33 JJ01 JJ08 JJ33 KK01 KK08 KK18 KK14 Q13 KK15 Q13 KK30 KK30 NN DA01 DA21 EC01 EC04 EC08 EC17 EH02 EH05 EJ01 EJ02 EJ07 EK01 FC05 5F044 AA02 EE02

Claims (11)

【特許請求の範囲】[Claims] 【請求項１】 第１導電型の第１の半導体領域と、 前記第１の半導体領域の表面の一部に面接触し、縦方向
に長い第２導電型の複数の第２の半導体領域と、 前記第２の半導体領域に面接触し縦方向に並ぶ複数の第
１の歯部と、前記第１の歯部に接続する第１の背部を有
する櫛状の第１の導体と、 前記第１の半導体領域の上に設けられ前記第１の歯部の
左右両側に縦方向に並ぶ複数の第２の歯部と、前記第２
の歯部に接続する第２の背部を有する櫛状の第２の導体
と、 前記第１の背部と裏面で接続して前記第１と前記第２の
導体の上方で横方向に並ぶ複数の第３の歯部と、前記第
３の歯部に接続し露出する第３の背部を有する櫛状の第
３の導体と、 前記第２の背部と裏面で接続して前記第１と前記第２の
導体の上方で前記第３の歯部と歯部の間に配置される第
４の歯部と、前記第４の歯部に接続し露出する第４の背
部を有する櫛状の第４の導体とを備える事を特徴とする
半導体装置。1. A first semiconductor region of a first conductivity type, and a plurality of second semiconductor regions of a second conductivity type, which are in surface contact with a part of the surface of the first semiconductor region and are elongated in the vertical direction. A plurality of first tooth portions which are in surface contact with the second semiconductor region and are arranged in a vertical direction; a first comb-shaped conductor having a first back portion connected to the first tooth portion; A plurality of second tooth portions provided on one semiconductor region and arranged vertically on both left and right sides of the first tooth portion;
And a plurality of comb-shaped second conductors having a second back portion connected to the tooth portions, and a plurality of the second conductors connected at the first back portion and the back surface and arranged laterally above the first and second conductors. A third tooth portion, a comb-shaped third conductor having a third back portion connected to and exposed to the third tooth portion; and the first and the second portions connected to the second back portion on a back surface. A fourth fourth tooth portion disposed between the third tooth portion and the second tooth portion above the second conductor, and a fourth comb-shaped portion having a fourth back portion connected to and exposed to the fourth tooth portion; A semiconductor device comprising: 【請求項２】 前記第１と前記第２の導体の上で、前記
第３と前記第４の導体の下に第１の絶縁膜を備える事を
特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, further comprising a first insulating film on the first and second conductors and below the third and fourth conductors. 【請求項３】 前記第１の背部を挿んで両側に前記第１
の歯部を有する事を特徴とする請求項１又は請求項２記
載の半導体装置。3. The first back portion is inserted and the first back portion is inserted on both sides.
3. The semiconductor device according to claim 1, wherein said semiconductor device has a tooth portion. 【請求項４】 前記第２の背部を挿んで両側に前記第２
の歯部を有する事を特徴とする請求項１乃至３のいずれ
か１つに記載の半導体装置。4. The second back portion is inserted and the second back portion is inserted on both sides.
The semiconductor device according to any one of claims 1 to 3, further comprising: 【請求項５】 前記第３の歯は、前記第３の背部に近い
部分ほど太い事を特徴とする請求項１乃至４のいずれか
１つに記載の半導体装置。5. The semiconductor device according to claim 1, wherein the third teeth are thicker at a portion closer to the third back. 【請求項６】 前記第４の歯は、前記第４の背部に近い
部分ほど太い事を特徴とする請求項１乃至５のいずれか
１つに記載の半導体装置。6. The semiconductor device according to claim 1, wherein the fourth teeth are thicker in a portion closer to the fourth back. 【請求項７】 露出した前記第３と前記第４の背部に接
続するワイヤーを備える事を特徴とする請求項１乃至６
のいずれか１つに記載の半導体装置。7. The apparatus according to claim 1, further comprising a wire connected to the exposed third and fourth backs.
The semiconductor device according to any one of the above. 【請求項８】 前記第２の歯部と前記第１の半導体領域
とに面接触し、互いの接触面が平行であり、前記第２の
半導体領域の端部と面接触する縦方向に長い第２の絶縁
膜と、 前記第１の半導体領域の表面の一部に面接触し、第２の
絶縁膜の端部と面接触する縦方向に長い第２導電型の複
数の第３の半導体領域を備える事を特徴とする請求項１
乃至７のいずれか１つに記載の半導体装置。8. A surface which is in surface contact with the second tooth portion and the first semiconductor region, their contact surfaces are parallel to each other, and is long in a longitudinal direction in surface contact with an end of the second semiconductor region. A second insulating film, a plurality of third semiconductors of a second conductivity type that are in surface contact with a part of the surface of the first semiconductor region and in surface contact with an end of the second insulation film; 2. An area having an area.
8. The semiconductor device according to any one of items 1 to 7, 【請求項９】 前記第２の歯部と前記第１の半導体領域
とが面接触し、前記第１の半導体領域の裏面と面接触す
る第２導電型の第４の半導体領域を備える事を特徴とす
る請求項１乃至７のいずれか１つに記載の半導体装置。9. The semiconductor device according to claim 9, wherein the second tooth portion and the first semiconductor region are in surface contact with each other, and a second conductivity type fourth semiconductor region is in surface contact with the back surface of the first semiconductor region. The semiconductor device according to claim 1, wherein: 【請求項１０】 第１導電型の第１の半導体領域の表面
の一部に面接触する縦方向に長い第２導電型の複数の第
２の半導体領域を形成する工程と、 前記第２の半導体領域に面接触し縦方向に並ぶ複数の第
１の歯部と、前記第１の歯部に接続する第１の背部を有
する櫛状の第１の導体を形成する行程と、 前記第１の半導体領域の上に設けられ前記第１の歯部の
左右両側に縦方向に並ぶ複数の第２の歯部と、前記第２
の歯部に接続する第２の背部を有する櫛状の第２の導体
を形成する工程と、 前記第１の背部と裏面で接続して前記第１と前記第２の
導体の上方で横方向に並ぶ複数の第３の歯部と、前記第
３の歯部に接続し露出する第３の背部を有する櫛状の第
３の導体を形成する工程と、 前記第２の背部と裏面で接続して前記第１と前記第２の
導体の上方で前記第３の歯と歯の間に配置される第４の
歯部と、前記第４の歯部に接続し露出する第４の背部を
有する櫛状の第４の導体を形成する工程とを有する事を
特徴とする半導体装置の製造方法。10. A step of forming a plurality of second semiconductor regions of a second conductivity type that are long in the longitudinal direction and are in surface contact with a part of the surface of the first semiconductor region of the first conductivity type; Forming a first comb-shaped conductor having a plurality of first teeth that are in surface contact with a semiconductor region and are arranged in a longitudinal direction, and a first back portion connected to the first teeth; A plurality of second teeth arranged on the left and right sides of the first teeth on the semiconductor region of
Forming a second comb-shaped conductor having a second back connected to the teeth of the first and second conductors, and connecting the first back and the back at a lateral direction above the first and second conductors Forming a third comb-shaped conductor having a plurality of third teeth arranged in a row and a third back connected to and exposed to the third teeth; and connecting the second back to the back surface A fourth tooth portion disposed between the third teeth above the first and second conductors, and a fourth back portion connected to and exposed to the fourth tooth portion. Forming a fourth conductor in the form of a comb. 【請求項１１】 前記第２の半導体領域を形成する工程
において、前記第２の半導体領域を配置するピッチを狭
める事と、 前記第１の導体を形成する行程において、前記第１の歯
部の幅を狭くし長さを短くし本数を増やす事と、 前記第２の導体を形成する行程において、前記第２の歯
部の幅を狭くし長さを短くし本数を増やす事と、 前記第３の導体を形成する行程において、前記第３の歯
部の本数を増やす事と、 前記第４の導体を形成する行程において、前記第４の歯
部の本数を増やす事を特徴とする請求項１０に記載の半
導体装置の製造方法。11. The step of forming the second semiconductor region, wherein the pitch at which the second semiconductor region is arranged is reduced, and the step of forming the first conductor includes the step of forming the first conductor. Narrowing the width and shortening the length to increase the number thereof; and in the process of forming the second conductor, narrowing the width and shortening the length of the second tooth portion to increase the number thereof, 3. The method according to claim 1, wherein the number of the third teeth is increased in a process of forming the third conductor, and the number of the fourth teeth is increased in a process of forming the fourth conductor. 11. The method for manufacturing a semiconductor device according to item 10.
JP2000080441A 2000-03-22 2000-03-22 Semiconductor device and method of manufacturing for semiconductor device Pending JP2001267564A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008053498A (en) * 2006-08-25 2008-03-06 Renesas Technology Corp Semiconductor device and manufacturing method thereof
JP2008140969A (en) * 2006-12-01 2008-06-19 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit and method of manufacturing the same
JP2009016686A (en) * 2007-07-06 2009-01-22 Toshiba Corp High frequency transistor
US7598521B2 (en) 2004-03-29 2009-10-06 Sanyo Electric Co., Ltd. Semiconductor device in which the emitter resistance is reduced
WO2022215319A1 (en) * 2021-04-05 2022-10-13 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device
US12154872B2 (en) 2021-03-15 2024-11-26 Sumitomo Electric Industries, Ltd. Semiconductor device and power amplifier

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7598521B2 (en) 2004-03-29 2009-10-06 Sanyo Electric Co., Ltd. Semiconductor device in which the emitter resistance is reduced
JP2008053498A (en) * 2006-08-25 2008-03-06 Renesas Technology Corp Semiconductor device and manufacturing method thereof
JP2008140969A (en) * 2006-12-01 2008-06-19 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit and method of manufacturing the same
JP2009016686A (en) * 2007-07-06 2009-01-22 Toshiba Corp High frequency transistor
US12154872B2 (en) 2021-03-15 2024-11-26 Sumitomo Electric Industries, Ltd. Semiconductor device and power amplifier
WO2022215319A1 (en) * 2021-04-05 2022-10-13 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device

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