JP2001251370A - Signal transmission system, signal transmitter, signal receiver and laser driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive signal transmission system that can transmit a pulse width modulation signal with excellent reproducibility over a wide duty range while suppressing electromagnetic wave radiation, to provide a signal transmitter and a signal receiver and to obtain an inexpensive laser driver that can drive a laser with high accuracy while suppressing electromagnetic wave radiation. SOLUTION: A pulse width modulation circuit 14 generates an on-signal ON having an edge corresponding to the on-timing of a pulse width modulation signal PWM and an off-signal OFF having an edge corresponding to off-timing delayed by the pulse width of the pulse width modulation signal PWM from the on-timing, transmits them to a demodulation circuit 16 via transmission lines L1, L2, and the demodulation circuit 16 generates a pulse width modulation signal PWM on the basis of each edge included in the received on-signal ON and off-signal OFF.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal transmission device, a signal transmission device, a signal reception device, and a laser driving device.
More specifically, based on a signal transmission device for transmitting a pulse width modulation signal, a signal transmission device for transmitting a pulse width modulation signal, a signal reception device for receiving a pulse width modulation signal, and a pulse width modulation signal And a laser driving device for driving the laser.

[0002]

2. Description of the Related Art In a laser beam printer capable of printing at an intermediate density, tone data corresponding to the density indicated by the image data of an image to be printed is generated by an image processing apparatus, and the tone data is pulse width modulated. The circuit is converted into a pulse width modulation signal and input to a laser driver, and the laser driver supplies a drive current corresponding to the pulse width modulation signal to the laser, thereby printing a target density. There is something.

Hereinafter, the operation of this type of laser beam printer will be briefly described with reference to FIGS. FIG. 16 is a block diagram showing a configuration example of this type of laser beam printer, and FIG. 17 is a time chart showing a signal state example and a printing state example of each part of the laser beam printer having the configuration shown in FIG. is there.

In this laser beam printer, first, from an image processing apparatus, gradation data corresponding to image density and 1
Control data indicating which position in the pixel is to be irradiated with the laser beam, etc., and input from a photodetector (the upper photodetector in FIG. 16) for generating a synchronization signal placed in a scanning optical path by a scanning means such as a polygon mirror. The clock signal synchronized with the synchronized signal is sent to the pulse width modulation circuit.

[0005] The pulse width modulation circuit generates a pulse width modulation signal based on control data and gradation data based on a clock signal, and supplies the pulse width modulation signal to a laser driver.

In a laser driver, a photodetector (FIG. 16) provided in the semiconductor laser for detecting the amount of light of the semiconductor laser is provided.
Adjusting the light amount of the semiconductor laser based on the light amount signal input from the lower light receiver (so-called APC (Auto Power Control)
ol)), a drive current is supplied to the semiconductor laser according to the pulse width modulation signal.

The semiconductor laser is turned on according to the supplied drive current, and forms an electrostatic latent image corresponding to the pulse width of the pulse width modulation signal as shown in the printing state of FIG. Form on top. Then, toner is attached to the electrostatic latent image to form a visible image, and the visible image (toner image) is transferred and fixed to a recording medium to perform printing.

As described above, the pulse width modulation signal which is pulse width modulated by the pulse width modulation circuit and the image density is expressed by the pulse width is sent to the laser driver in synchronization with the clock signal. Intermediate density printing is performed by driving the semiconductor laser (controlling the irradiation time of the semiconductor laser) according to the pulse width of the modulation signal.
That is, when the pulse width of the pulse width modulation signal is long, the density is high, and when the pulse width is short, the density is low.

There are several types of the pulse width modulation circuit. Typical ones are a triangular wave signal and
Generating a pulse width modulation signal having a pulse width corresponding to input digital image data by comparing a voltage reference value obtained by D / A (digital / analog) conversion (Japanese Patent Laid-Open No. Sho 62-39974) ) Or a device that generates a pulse width modulation signal using a delay element (Japanese Patent Application Laid-Open No. 56-15237).
No. 3, JP-A-2-294155 and the like are generally known.

[0010]

However, the above-mentioned prior art has the following problems. 1. Transmission of short pulses is difficult.

For example, 600 DPI (60 per inch)
In a printer capable of printing 50 sheets of A4 size paper per minute with a printer having a printing density of 0 dots, a video clock signal (a clock signal corresponding to one pixel in one cycle) is about 40M.
Hz. Also, when this is converted into a cycle, it is 25 nsec. Here, in order to accurately reproduce the highlights (low density portions) sensitive to the human eye, it is necessary to irradiate the photoreceptor with a laser at a time interval corresponding to a pulse width of 5% or less of the period of one pixel. For this purpose, a pulse width modulation signal having a pulse width of about 1 ns must be transmitted to the laser driver.

However, since the laser driver needs to drive the laser at a high speed, it is generally arranged close to the laser, and how to connect to the image processing apparatus has a short pulse width. This has been a problem in transmitting a modulated signal.

That is, when a high-speed pulse is simply transmitted to a cable, even if consideration is given to impedance matching to all of the cables, connectors, and wiring on the printed wiring board, the loss of the transmission path (resistance ) Causes the transmitted waveform to be rounded at the rising and falling edges.

FIG. 18 shows LVDS (Low Voltage Differential Signaling) which is a kind of high-speed signal transmission system.
3 shows an example of a simulation result of the transmission waveform in FIG. Here, the pulse width of the drive signal is 0.
A drive signal waveform at an input end of a transmission line and a drive at an output end of a transmission line when a signal generated at intervals of 0.5 nsec from 5 nsec to 4.0 nsec is input to a transmission line having a length of 0.5 m. This shows a simulation of a signal waveform.

In the example shown in FIG. 1, the pulse width of the drive signal at the output end of the transmission line is 3n due to the rounding of the transmission line.
In the case where the pulse width is less than 2 seconds, the pulse width starts to fall before the rising edge. Therefore, when the pulse width is 3 ns or less, the pulse width of the drive signal after transmission does not correspond to the pulse width before transmission, and as a result, Could not reproduce the highlights. 2. EMI (Electromagnetic Interf
erence, electromagnetic interference).

Since a short pulse such as 1 ns has a high frequency component, when a long cable is routed between a pulse width modulation circuit and a laser driver, there is a problem in terms of EMI. 3. Jitter is likely to occur.

The signal transmitted by the transmission line has a property that the rise and fall of the subsequent signal are affected by the previous signal, and jitter occurs due to this property, and a thin line is drawn. At this time, a problem such as disappearance of the thin line occurs.

For example, when an isolated short pulse signal is transmitted, if the off level (low level) continues for a long time before that, the rise of the pulse signal is delayed. However, the falling edge has a low level for a long time before it has a low level, so that the pulse width when output from the transmission line is shorter than the pulse width when input to the transmission line.

This phenomenon becomes a problem, for example, when drawing a halftone thin line in the paper feed direction in an image forming apparatus. That is, since a short pulse needs to be sent in the halftone, an isolated short pulse as shown in FIG. 31A is sent. However, the pulse is further shortened due to the isolation, and in the worst case, printing is performed. Disappears.

On the other hand, FIG. 31 (B) shows the state of the pulse in the case where the drawing of the fine line is repeated periodically. In this case, the high level and the low level are repeated before the short pulse. Since it is present, the rise is not delayed, and therefore the pulse width is not narrowed.
Thus, the pulse width varies due to the signal transmitted immediately before.

As techniques that can be applied to solve the above-mentioned problems, there are techniques described in JP-A-3-173661 and JP-A-3-71774.

In the technique described in Japanese Patent Application Laid-Open No. 3-173661, a signal is transmitted with a long pulse width, and the pulse width is corrected so that the signal received on the receiving side has a short pulse width.

In correcting the pulse width, ideally, when attention is paid only to short pulses, as shown in FIG. 19A, transmission is performed when the pulse width is short in the portion a where the density is low. On the receiving side, the pulse width is shortened as shown in FIG. 19 (B), and as a whole, the duty is reduced from 0% to 1 as shown in FIG. 19 (C).
The input / output pulse width is linearly associated with up to 00%.

As a method of easily realizing the conversion of the pulse width, for example, by using a diode or the like as shown in FIG. 20, only the rising time constant of the pulse is delayed as shown in FIG. There is a method to set the falling time constant earlier. However, in this case, FIG.
As shown in (B), there is a problem that the density is reduced in the high density portion. Therefore, when the pulse width is short, it is necessary to correct the pulse width so as to be short, and when the pulse width is long, it is necessary to correct the pulse width so that the pulse width is long. As in this technology, the method of transmitting with a longer pulse width shifts the frequency component of the pulse to the lower side.
This method is also advantageous in terms of electromagnetic interference (EMI).

However, in this method, the operation is switched between the case where the pulse width is shortened and the case where the operation is lengthened, and there is a problem that the pulse width characteristic for data tends to be discontinuous at the time of the switching. In order to prevent discontinuity, it is necessary to continuously control the pulse width. However, this point is not mentioned in the publication, and it is difficult to technically realize the pulse width.

On the other hand, in the technique described in Japanese Patent Application Laid-Open No. 3-71774, a circuit which receives gradation data from an image processing apparatus and generates a pulse width modulation signal is provided near a laser driving means (laser driver). This arrangement prevents the waveform of the pulse width modulation signal from deteriorating. In this technique, the pulse width modulation means and the laser driving means are configured as the same chip (IC, Integrated Circuit).

Although this technique is an ideal technique in terms of waveform transmission, the laser drive circuit is generally configured as an analog circuit, and when such an analog circuit is formed into an IC, it is necessary to operate at high speed. There are restrictions on IC layout, and it can be easily combined with other circuits such as digital circuits to easily use ASICs (Application Specific Integrated Circuits).
In addition, it is difficult to convert the grayscale data to a predetermined bit size (for example, 8 bits) representing the grayscale from the image processing apparatus as shown in FIG. And control data for controlling dot positions, etc., must be input. For this reason, a large number of digital signal lines must be routed in the apparatus, which is costly and requires a large number of digital signals. A digital signal must be supplied to the line, which is also a problem in terms of electromagnetic radiation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an inexpensive signal transmission method capable of transmitting a pulse width modulation signal with good reproducibility over a wide duty range while suppressing electromagnetic radiation. It is an object of the present invention to provide a low-cost laser driving device capable of driving a laser with high accuracy while suppressing electromagnetic radiation, while providing a device, a signal transmitting device, and a signal receiving device.

[0029]

According to a first aspect of the present invention, there is provided a signal transmission apparatus comprising: a first pulse having a first edge corresponding to an ON timing of a pulse width modulation signal to be transmitted; First generating means for generating a signal and a second pulse signal having a second edge corresponding to an off-timing that has elapsed from the on-timing by the pulse width of the pulse-width modulated signal; The second
Transmitting means for transmitting each of the pulse signals, receiving means for receiving the first pulse signal and the second pulse signal from the transmitting means, and receiving the first pulse signal and the second pulse signal. Second generating means for generating a pulse width modulation signal from the first edge and the second edge of the pulse signal.

According to the signal transmission apparatus of the first aspect, the first pulse signal having the first edge corresponding to the on-timing of the pulse width modulation signal to be transmitted and the pulse of the pulse width modulation signal from the on timing. A second pulse signal having a second edge corresponding to the off-timing that has passed by the width is generated by the first generation unit, and the first pulse signal and the second pulse signal are transmitted by different transmission units, respectively. Is done.

Here, the transmission means includes a transmission line used for transmission of each of the first pulse signal and the second pulse signal, and a driver circuit or the like according to a case where the transmission distance is long. Can be. The transmission line includes a transmission line outside the device in addition to a transmission line inside the device.

Further, in this signal transmission device, the first pulse signal and the second pulse signal from the transmission unit are received by the reception unit, and the received first pulse signal and the second pulse signal are received. From the first edge and the second edge, a pulse width modulation signal is created by the second creating means. Note that the second generation unit can generate the pulse width modulation signal such that the pulse width modulation signal is turned on in response to the first edge and the pulse width modulation signal is turned off in response to the second edge. Any means can be applied as long as it is a means.

As described above, according to the first aspect of the present invention, the first pulse signal having the first edge corresponding to the on-timing of the pulse width modulation signal to be transmitted and the on-timing are used to determine the pulse width modulation signal. And a second pulse signal having a second edge corresponding to the off-timing that has elapsed by the pulse width of the second pulse signal and transmitted by different transmission means, and the first pulse signal and the second pulse from the transmission means. Since the pulse width modulation signal is generated from the first edge and the second edge by receiving the signal, the pulse width of each of the first pulse signal and the second pulse signal transmitted through the transmission unit Can be increased, whereby a pulse width modulation signal with good reproducibility can be transmitted over a wide duty range at low cost while suppressing electromagnetic radiation.

Hereinafter, the effectiveness of the present invention will be described for each problem of the above-described conventional technology. 1. Effective for the problem that transmission of short pulses is difficult.

According to the present invention, the first pulse signal (hereinafter, referred to as “ON signal”) and the second pulse signal (hereinafter, referred to as “ON signal”)
Since the receiving side generates a pulse width modulation signal based on the transition timing of each signal, the waveforms of the ON signal and the OFF signal are distorted. Even if the difference between the transition timings of the ON signal and the OFF signal is determined, a short pulse can be easily transmitted as a result.

FIG. 22 shows an example of a simulation result of a transmission waveform in LVDS. Here, as the drive signal, the ON signal changes its state at a single timing, and the OFF signal shifts the state change timing by 0.5 nsec.
The figure shows a simulated waveform of each of the ON signal and the OFF signal at the output end of the transmission line when input to a 5 m transmission line.

As shown in the figure, although the waveform at the output end is distorted due to the transmission of the ON signal and the OFF signal through the transmission line, all the ON signals have substantially the same delay time. , And the OFF signal is transmitted in a state where the deviation of 0.5 ns is almost accurately maintained, and it can be seen that the pulse width can be maintained accurately. 2. Effective against the problem that EMI occurs during short pulse transmission.

When the present invention is applied to an image forming apparatus, when controlling the density, it is important to control the duty to turn on the laser within one pixel. Is turned on or off once or twice.

Therefore, there is a period of about one pixel from the transition of the ON signal to ON in the present invention to the transition to the next ON signal. The same applies to the OFF signal, in which case the fundamental frequency of the ON signal and the OFF signal passing through the transmission line is very low, ie, 1 to 1/2 of the clock frequency.

On the other hand, when a pulse width modulation signal is directly transmitted, when a short pulse of, for example, 1 ns is transmitted as the pulse width modulation signal, the basic frequency of the transmitted pulse width modulation signal is 500 MHz or more. Very high frequency components will be included.

FIGS. 23A and 23B show an ON signal and an OFF signal each having a pulse width of 1 ns, and a pulse generated by a demodulation circuit (XOR circuit) using these signals. An FFT (Fast Fourier Transform) result of the voltage waveform of the width modulation signal is shown.

As shown in the figure, the voltage level of the ON signal and the OFF signal and the pulse width modulation signal is 20 dB.
There is some difference. As can be seen from the results, the transmission of the signals indicating the on-timing and the off-timing as transitions on separate transmission lines is different from the case where the signals are transmitted directly as a pulse width modulation signal. Can be greatly reduced. 3. Effective against the problem that jitter is likely to occur.

According to the present invention, the ON signal and the OFF signal are transmitted by different transmission means, and the receiving side generates the pulse width modulation signal based on the transition timing of each signal. As shown in A), for example, an ON signal that transits at the rising edge of the isolated short pulse to a transmission line that transmits an ON signal and an OFF signal in order to generate, for example, an isolated short pulse as a pulse width modulation signal (laser drive signal). When an off signal that transitions at the falling edge of the isolated short pulse is transmitted, the transition of each signal is also delayed due to jitter, but since both the on signal and the off signal are similarly delayed, the pulse width of the isolated short pulse is reduced. It is not affected by jitter.

As shown in FIG. 24B, even when a continuous short pulse is generated, the pulse width does not change because the short pulse is generated by the transition time difference between the transmission lines.

At this time, there is a problem that the position of the pulse slightly shifts due to the jitter, but this is the same in the prior art. For example, A4 size paper is printed at a printing speed of 40 sheets per minute. When printing, even if the length of the transmission path is 1 m, the distance of the movement is 1 μm.
The degree is not at a level that deteriorates the image quality as a jaggy. It is more important that the reproducibility with respect to the density can be maintained than the movement of the pulse position, and the effect on the image quality is negligible.

When the signal transmission device of the present invention is applied to a laser driving device, the signal transmission device of the present invention and the second preparation means of the signal transmission device are provided as in the eighth aspect of the present invention. And a driving unit for driving a laser based on the pulse width modulation signal created by the above.

Therefore, in this laser driving device, the laser is driven based on the pulse width modulation signal obtained by the signal transmission device of the present invention, so that the laser can be driven at low cost and with high accuracy while suppressing electromagnetic radiation. can do.

FIG. 25 shows an example of the configuration of a laser driving device provided with the signal transmission device according to the first aspect. In the example shown in the figure, in the pulse width modulation circuit, an ON signal whose level changes in synchronization with the timing of turning on the laser and an OFF signal whose level changes in synchronization with the timing of turning off the laser are generated. The on signal and the off signal are transmitted to the demodulation circuit provided near the laser driving circuit through different transmission paths, and the demodulation circuit generates a pulse width modulation signal based on the on signal and the off signal and supplies the pulse width modulation signal to the laser driving circuit. are doing. That is, in this example, the pulse width modulation circuit corresponds to the first generating means of the present invention, the demodulation circuit corresponds to the second generating means of the present invention, the laser driving circuit corresponds to the driving means of the present invention, and the ON signal corresponds to the present invention. And the off signal corresponds to the second pulse signal of the present invention.

However, such a signal transmission device and a laser driving device have the following new problems when they are implemented. 1. The pulse width varies.

When two signals (ON signal and OFF signal) indicating ON timing and OFF timing are simply transmitted, there are eight possible combinations of transition of each signal as shown in FIG.

Usually, the transistors used for driving are different between the rise and fall of the signal (normally, the rise is driven by a P-channel transistor and the fall is driven by an N-channel transistor). , Transition times are different. Therefore, the pulse start delay time and the pulse width are slightly different for each combination of transitions.

When the laser driving apparatus of the present invention is applied to an image forming apparatus for forming an image by a laser beam typified by a laser beam printer or the like, the delay time is related to the beam spot position, and the pulse width is related to the density. However, since the density is visually more sensitive than the beam spot position, the pulse width must be kept unchanged by the combination of transitions of each signal.

The following two measures can be considered.

First, the W / L of each of the rising transistor and the falling transistor is set so that the rising transition time and the falling transition time are equal.
(Gate width W / length L of MOS transistor) is adjusted to manufacture each transistor. Here, if there is a variation in the manufacturing process, feedback control of the gate voltage of the MOS transistor may be considered so that the rise transition time and the fall transition time are equal.

The second is to reduce the number of combinations of transitions of the ON signal and the OFF signal. That is, if the laser is to be turned on while the off signal is at the low level, the on signal is set to the high level, and if the laser is turned on while the off signal is at the high level, the on signal is set to the low level. If the laser is to be turned off while the on signal is at the high level, the off signal is set to the high level. If the laser is turned off while the on signal is at the low level, the off signal is set to the low level. The ON signal and the OFF signal generated in this manner are transmitted to an exclusive OR circuit (hereinafter, “X”) after reception.
OR circuit ") to convert (demodulate) the signal into a pulse width modulated signal.

In this case, the combinations of transitions are limited to four types of 1, 2, 7, and 8 in FIG. Normally, it is required to improve by giving priority to short pulses in highlights. Therefore, the combination of transitions in short pulses is indicated by 1 and 2 in FIG.
If the pulse width is limited to the above, the pulse width is limited to the difference between the rising and falling edges of the ON signal and the OFF signal. At the same time, the demodulation circuit can be realized only by the XOR circuit.

In this case, however, the combination of transitions of the short-off pulses on the high-concentration side becomes 7 and 8 in FIG. 26, and the accuracy of the pulse width is reduced. To achieve high-precision pulse widths on both the highlight side and the high-density side, either design the rise and fall to be the same, or output the ON and OFF signals to limit the combination of transitions Need to be restricted. 2. The signal from the pulse width modulation circuit cannot be transmitted as it is.

As a pulse width modulation device applicable when transmitting ON timing and OFF timing separately,
JP-A-3-26661, JP-A-4-34236
No. 4, U.S. Pat. No. 5,109,283, U.S. Pat.
There is a method described in US Pat. No. 7,793,709 and US Pat. No. 5,903,522, which can control the on / off timing of the laser independently. However, simply applying these techniques as they are will cause the following problems.

According to the technique described in Japanese Patent Application Laid-Open No. 3-26661, as shown in FIG. 27, a minute pulse is generated from a clock signal, and a plurality of minute pulses at different timings are generated by delaying the minute pulse. Among them, those corresponding to the rising timing and the falling timing are selected and used.

In this technique, although nothing is mentioned in the publication, when a laser drive pulse is generated by driving a flip-flop with this minute pulse, the pulse width of the minute pulse is set to be smaller than the minimum pulse width of the laser drive pulse. Must also be shortened. However, such a small pulse has a high frequency component and a large waveform rounding, so that it is difficult to transmit it as it is.

In this technique, a method of generating a pulse having a short pulse width by performing an exclusive OR operation between outputs of adjacent delay gates by using an XOR circuit has been proposed. The operation speed is slow because of the gates, and it is difficult to generate a pulse having a pulse width of about 1 ns by inputting gate outputs of adjacent delay gates. Even if the pulse output can be generated, the pulse width is short. Therefore, the data may be lost during transmission between the circuits.

For this reason, it is conceivable to generate a pulse having a slightly longer pulse width by using the outputs of the delay gates that are not adjacent but separated from each other, but it is possible to generate a pulse having a slightly longer pulse width. In a system that automatically controls the delay amount of the clock signal, when the frequency of the clock signal is reduced, the pulse width is unnecessarily widened. Only controllability similar to frequency can be ensured.

On the other hand, in the technique described in Japanese Patent Application Laid-Open No. 4-342364, a small pulse is not generated immediately from a clock signal as in the technique described in Japanese Patent Application Laid-Open No. 3-26661, but as shown in FIG. In addition, a start trigger signal S-TRIG and an end trigger signal E-
After the TRIG is once generated, a pulse signal S-CLK and a pulse signal E-
CLK is generated, and the next stage flip-flop is operated to generate the laser drive signal Lon.

Using this technique, the signal S-TRIG and the signal E-TRIG having a long pulse width are transmitted, and after transmission, the signal S-CLK and the signal E-CLK are generated. If a laser drive signal is generated, no problem occurs even if the transmission line is slightly rounded.

However, the signal S-TRIG and the signal E
-Due to the long pulse width of TRIG,
Similarly to the technique described in Japanese Patent Application Publication No. 2668661, when it is necessary to repeatedly turn on a plurality of times within a short time as shown in the printing state of FIG.
The repetitive operation cannot be performed during a period shorter than the pulse width of -TRIG. In this case, if the pixel cannot be turned on twice or more in one pixel, for example, when the number of gray scales is increased by performing fine division in the beam scanning direction, controllability is significantly reduced.

Further, in the techniques of US Pat. No. 5,793,709 and US Pat. No. 5,903,522, a pulse which is toggled between the ON timing and the OFF timing of the laser is used, and the exclusive OR of these signals is calculated. A width modulation signal is generated.

In this case, the on timing or the off timing of the laser is determined by only one transition.
When the ON signal and the OFF signal are transmitted and the pulse width modulation signal is generated by the XOR circuit after the transmission, the frequency component of the signal on the transmission line is significantly reduced, which is preferable in terms of EMI, and is not necessarily required. Transmission is possible without using high-speed elements.

On the other hand, FIG. 29 shows US Pat.
FIG. 30 shows a configuration of a portion particularly related to the present invention in US Pat. No. 5,793,709 and US Pat.
No. 22 shows a configuration of a part particularly related to the present invention.

In each of the techniques of US Pat. No. 5,109,283, US Pat. No. 5,793,709 and US Pat. No. 5,903,522, the on-timing and the timing are improved by repeatedly using a circuit constituted by cascading a relatively small number of delay circuits. A delay pulse serving as a reference of a signal indicating the OFF timing is generated. To make the operation seamless (seamless state), ODD and EVEN are alternately operated as shown in FIGS. In this case, four transmission lines (five in consideration of the third transition in one pixel as shown in US Pat. No. 5,109,283) are required. In addition, the cost increases due to the increase in the number of wirings, and the output due to the characteristic deviation between the transmission lines on the ODD side and the EVEN side. Variations of jitter and pulse width is generated in the pulse.

In the technique of US Pat. No. 5,109,283, as shown in FIG. 29, in order to suppress the generation of unnecessary noise, the "cell clock", "cell clock", "ON" and "OFF" signals are supplied to the XOR circuit. Hlf clock ',' video kil
A control signal such as l bit 'must be supplied. 3. The pulse width varies due to the skew of the transmission line.

In the present invention, ideally, there is no skew (transmission time lag between the transmission lines) between the transmission lines transmitting the ON signal and the OFF signal. In addition, it is unavoidable that skew occurs due to different characteristics of each connector line.

For this reason, it is important to use a driver, a receiver (for example, DS90LV047A, DS90LV048A, etc., manufactured by National Semiconductor, etc.) which suppresses skew between channels, which is commercially available for transmitting a multi-phase clock signal. However, when skew occurs between channels due to differences in characteristics of each line such as a transmission line and a connector, the time difference between when the ON signal and the OFF signal transition from the low level to the high level is used. The pulse width is different between the case where the time difference when the signal and the OFF signal transition from the high level to the low level is used, which causes deterioration of the image quality.

In view of the above problems, the signal transmission device according to claim 2 is different from the signal transmission device according to claim 1 in that the first pulse signal and the second pulse signal received by the receiving unit are different from each other. It is characterized by further comprising a correcting means for correcting each time lag of the pulse signal.

According to the signal transmission device of the second aspect, in the invention of the first aspect, the time lag of each of the first pulse signal and the second pulse signal received by the reception unit is corrected by the correction unit. Is done.

According to a third aspect of the present invention, in the signal transmission device according to the second aspect of the present invention, the correcting means includes a transmitting means for transmitting the first pulse signal and a transmitting means for transmitting the second pulse signal. A pulse signal delay means provided on at least one of them and capable of changing a delay time for delaying and outputting an input pulse signal; and adjusting the delay time by the pulse signal delay means so as to reduce the time lag. And means.

According to a third aspect of the present invention, in the signal transmission apparatus according to the second aspect, at least one of the transmission means for transmitting the first pulse signal and the transmission means for transmitting the second pulse signal is provided. A pulse signal delay means for changing a delay time for delaying and outputting an inputted pulse signal, and a delay by the pulse signal delay means so as to reduce a time lag in the invention according to claim 2 by adjusting means. The time is adjusted.

Further, the signal transmission device according to claim 4 is the signal transmission device according to any one of claims 1 to 3,
The first generating means includes: a first edge of the first pulse signal; a second edge of the second pulse signal; and a second edge of the first pulse signal after the second edge. An edge opposite to the first edge occurs, and after the opposite edge occurs, the first pulse signal and the second pulse signal are generated such that an edge opposite to the second edge occurs in a second pulse signal. It is characterized in that a second pulse signal is created.

According to a fourth aspect of the present invention, a first edge is generated in a first pulse signal by the first generating means according to any one of the first to third aspects of the present invention. A second edge occurs in the second pulse signal after the second pulse occurs, and an edge opposite to the first edge occurs in the first pulse signal after the second edge occurs, and the opposite edge occurs The first pulse signal and the second pulse signal are generated such that an edge opposite to the second edge occurs later in the second pulse signal.
Is generated.

According to a fifth aspect of the present invention, there is provided the signal transmission device according to the first aspect of the present invention.
A first pulse generating means for delaying a clock signal for synchronizing the pulse width modulation signal by a period shorter than one cycle of the clock signal to generate a plurality of delayed pulses synchronized with the clock signal; And a delay pulse having a first edge corresponding to the on-timing and a delay pulse having a second edge corresponding to the off-timing from the plurality of delay pulses generated by the delay pulse generating means. Selecting means for selecting the first pulse signal and the second pulse signal.

According to the signal transmission device of the fifth aspect, in the invention of any one of the first to fourth aspects,
The clock signal for synchronizing the pulse width modulation signal is delayed by the delay pulse generation means for each time shorter than one cycle of the clock signal, and a plurality of delay pulses synchronized with the clock signal are generated. The delay pulse having a first edge corresponding to the on-timing and the delay pulse having a second edge corresponding to the off-timing are respectively obtained from the plurality of delay pulses.
And the second pulse signal.

Hereinafter, the effectiveness of the present invention will be described for each of the above-mentioned problems. 1. Effectiveness for the problem that the pulse width varies.

According to the fourth aspect of the present invention, after the state of the ON signal (first pulse signal) changes, the OFF signal (second pulse signal) changes.
Pulse signal), the state of the on signal returns to the original state after the state of the off signal transitions, and the state of the on signal and the state of the off signal returns to the original state after the state of the on signal returns. An off signal is being generated.

Thus, the pulse width of the pulse width modulation signal is limited to the difference between the rising edges or the falling edges of the ON signal and the OFF signal, so that the variation in the pulse width can be suppressed. 2. The problem that the transition of the ON signal or the OFF signal cannot be repeated within a short time (Japanese Unexamined Patent Publication No. 3-266681)
Of the technology described in Japanese Patent Application Laid-Open Publication No. 4-342364 and Japanese Patent Application Laid-Open No. 4-342364.

According to the fourth aspect of the invention, as described above, the state of the off signal transits after the state of the on signal transits, and the state of the on signal returns to the original state after the transition of the off signal. The ON signal and the OFF signal are generated so that the state of the OFF signal returns to the original state after the state of the ON signal returns to the original state.

Therefore, in the case where the first producing means is constituted by a circuit, if the speed of the gate element constituting the circuit is high, the driving pulse width for generating the ON signal and the OFF signal is consequently short, and the gate The slower the element, the longer the pulse width. For this reason, the pulse width is automatically determined according to the speed of the gate element, and the transition of the ON signal and the OFF signal can be repeated as long as the speed of the gate element permits. 3. A problem that a seamless pulse width modulation signal cannot be generated unless the number of transmission lines is increased for ODD, EVEN, and the like (US Pat. No. 5,109,283 and US Pat.
793709 problem).

According to the fifth aspect of the present invention, the reference delay pulse for generating the ON signal and the OFF signal is generated so as to be synchronized with the clock signal. For this reason, the means for generating the delay pulse is complicated. However, unlike the technique of US Pat. No. 5,793,709, a digital arithmetic circuit such as a lap counter is not included, so that there is no need to perform integrated control of the whole. Therefore, there is no need to separate ODD and EVEN, and the number of transmission lines can be reduced. 4. Effective against the problem that pulse width varies due to transmission line skew.

The skew of the cable constituting the transmission line does not fluctuate like a semiconductor element once the shape is fixed. Therefore, the influence of the skew can be avoided by designing the device in consideration of the skew. However, the skew may change due to a change over time or a change in environmental temperature.

In view of such a case, according to the second and third aspects of the present invention, the time lag of each of the first pulse signal and the second pulse signal received by the receiving means is corrected by the correcting means. Is done. As a result, even if the skew changes, the skew is corrected so that there is no skew, so that it is possible to prevent variations in pulse width due to skew in the transmission line.

As a specific correction method by the above-mentioned correction means, the correction means is provided on the receiving side of the ON signal and the OFF signal, and a known reference pulse is previously transmitted to the transmission path for the ON signal and the OFF signal. Transmitting over each of the transmission paths of
A method of correcting the time lag of the reference pulse received on the receiving side using a delay circuit, or providing a correcting means on the transmitting side of the ON signal and the OFF signal, transmitting the reference pulse in the same manner as described above, and For example, there is a method in which the received reference pulse is sent back to the transmitting side, and correction is performed on the transmitting side based on the time lag of the returned reference pulse.

If the transmitting side is not provided with the means for transmitting the reference pulse as described above, for example,
The synchronization signal output from the synchronization signal generation light receiver disposed in the scanning optical path of the laser beam can also be used for detecting the presence or absence of skew.

That is, for example, before the scanning of one line, the transition of the OFF signal is delayed with respect to the transition of the ON signal so as to make the laser emit light, and the transition of the OFF signal is gradually advanced. Since the transition of the ON signal is later than the OFF signal at the timing and the synchronization signal is no longer detected, the timing at which the detection is stopped is regarded as the timing without skew, and this timing is used as a reference. In an image forming apparatus that forms an image using a laser beam, such a synchronization signal is always supplied to an image processing apparatus or a pulse width modulation circuit, so that this method can be realized without increasing the cost. Can be.

In addition to this, a method in which different information is superimposed on the same transmission line by, for example, placing it on a carrier wave is also applicable.

On the other hand, according to the signal transmitting apparatus of the present invention, the first pulse signal having the first edge corresponding to the ON timing of the pulse width modulation signal and the pulse width of the pulse width modulation signal from the ON timing. First generating means for generating a second pulse signal having a second edge corresponding to the turned-off timing, and transmitting means for transmitting the first pulse signal and the second pulse signal, respectively. Have.

That is, since the invention according to claim 6 includes the first creation means and the transmission means according to the invention according to claim 1, the reproducibility over a wide duty range while suppressing electromagnetic radiation. Good pulse width modulation signals can be transmitted.

According to a seventh aspect of the present invention, in the signal receiving apparatus, a first pulse signal having a first edge corresponding to the ON timing of the pulse width modulation signal and a pulse width of the pulse width modulation signal from the ON timing. Receiving means for receiving a second pulse signal having a second edge corresponding to the turned-off timing, and a first edge and a second edge of the received first pulse signal and the received second pulse signal And a creating means for creating a pulse width modulation signal from

That is, since the invention of claim 7 includes the means corresponding to the receiving means and the second creation means of the invention of claim 1, a wide duty range while suppressing electromagnetic radiation. , A pulse width modulation signal with good reproducibility can be transmitted.

Further, the laser driving device according to claim 9 is
A signal receiving apparatus according to claim 7, and driving means for driving a laser based on the pulse width modulation signal created by the creating means of the signal receiving apparatus.

Therefore, according to the present invention, it is possible to drive a laser at low cost and with high accuracy while suppressing electromagnetic radiation.

[0099]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[First Embodiment] First, the configuration of the laser driving device 10 according to the first embodiment will be described with reference to FIGS.

As shown in FIG. 1, a laser driving device 10 according to the first embodiment includes an image processing circuit 12, a pulse width modulation circuit 14, a demodulation circuit 16, a laser driving circuit 18, a laser 20, a light receiver 22, It is configured to include the light receiver 24.

The output terminals of the image processing circuit 12 for outputting the signal ONdata and the signal OFFdata are connected to the pulse width modulation circuit 14, and the output terminals for outputting the ON signal ON and the OFF signal OFF of the pulse width modulation circuit 14 are respectively provided. The pulse width modulation signal PWM of the demodulation circuit 16 is connected to the demodulation circuit 16 via the transmission line L1 and the transmission line L2.
Is connected to the laser drive circuit 18 to which the laser 20 is connected.

On the other hand, the light receiver 22 is a light receiver for generating a synchronization signal placed in a scanning optical path by a scanning means such as a polygon mirror, and the synchronization signal BD output from the light receiver 22 is provided.
Is input to the pulse width modulation circuit 14. The light receiver 24 is a light receiver provided in the laser 20 for detecting the amount of light of the laser 20.
Is configured to be input to the laser drive circuit 18.

The laser drive circuit 18 drives the laser 20 in accordance with the pulse width modulation signal PWM input from the demodulation circuit 16 in a state where the light intensity of the laser 20 is adjusted based on the light intensity signal input from the light receiver 24. Supply.

As shown in FIG. 2, the demodulation circuit 16 includes a receiver 72, a receiver 74, and a two-input XOR circuit 76. The input terminals of the receiver 72 and the receiver 74 are connected to the transmission line L1 and the transmission line L1, respectively. The output terminals are connected to the input terminals of the XOR circuit 76, respectively, and the output terminals of the XOR circuit 76 are connected to the laser drive circuit 18.

On the other hand, the pulse width modulation circuit 14 includes a clock synchronization circuit 30, a delay circuit 32, a buffer 34, a control signal generation circuit 36, a delay pulse generation circuit 38, a minute delay control signal generation circuit 40, a phase comparator 42, and a delay circuit. 44, a phase comparator 46, a delay circuit 48, a delay circuit 50, a multiplexer 52, a driver 54, a delay circuit 56, a multiplexer 58, and a driver 60.

The clock synchronization circuit 30 is connected to the light receiver 22, the delay circuit 32, and the control signal generation circuit 36.
The delay circuit 32 is connected to the phase comparator 42 and to the delay pulse generation circuit 38 via the buffer 34.

The delay pulse generation circuit 38 is connected to the control signal generation circuit 36, the delay circuit 50 and the delay circuit 56, the phase comparator 42 is connected to the delay circuit 44, and the delay circuit 44 The delay circuit 48, the delay circuit 50, and the delay circuit 56 are connected via the device 46. The delay circuit 50 is connected to a multiplexer 52, and the multiplexer 52 is connected to an input terminal of a receiver 72 via a driver 54 and a transmission line L1 in this order. Similarly, the delay circuit 56 is connected to the multiplexer 58, and the multiplexer 58 is connected to the input terminal of the receiver 74 via the driver 60 and the transmission line L2 in this order.

Further, the minute delay control signal generation circuit 40 is connected to the multiplexers 52 and 58.

The clock synchronizing circuit 30 synchronizes the clock signal CK (see also FIG. 7) generated as a signal indicating the operation cycle of the laser driving device 10 with the synchronizing signal BD input from the light receiver 22 to generate a clock signal. The clock signal I is output to the control signal generation circuit 36 as ICK.
CK is further gated so as to be effective only during the driving period of the pulse width modulation circuit 14, and is output to the delay circuit 32 as a clock signal φ.

As shown in FIG. 3, the delay circuit 32 is configured as a cascade connection of 130 inverters (= 128 + 2 stages) of inverters INV. Pulse T
1, T2,..., T64 are connected to the buffer 34 as terminals for outputting the final stage inverter INV.
Are connected to the phase comparator 42, the delay circuit 44 and the delay circuit 48 as terminals for outputting the delay pulse T65.

The inverter IN used here
V is configured such that a PMOS transistor PT2 and an NMOS transistor NT2 are connected as a constant current circuit to a source side of each transistor, with respect to an inverter configured by a PMOS transistor PT1 and an NMOS transistor NT1 as shown in FIG. .

The inverter INV configured as described above
Shows that the lower the voltage of the PMOS transistor PT2, the sharper the rise of the output of the inverter INV,
The higher the voltage of the OS transistor NT2, the steeper the fall of the output. Also, a PMOS transistor PT
2, the output rises sharply as the W / L of the NMOS transistor NT2 increases, and the output fall sharpens as the W / L of the NMOS transistor NT2 increases.

In this embodiment, since the delay pulse is generated by using the inverter, the
Although a stage is required, if there is an inverter controlled by one inverter so as to have the same delay time as that of the two inverters, and if an inverted output can be used, the number of inverters is 65 (64 + 1). I'm done.

On the other hand, as shown in FIG. 4, the control signal generating circuit 36 includes flip-flops FF1 and FF2 for the ON signal and flip-flops FF3 and FF4 for the OFF signal. I have.

Clock terminal C of flip-flop FF1
The clock signal ICK synchronized with the synchronization signal BD by the clock synchronization circuit 30 is directly input to K, and the inverter I is connected to the clock terminal CK of the flip-flop FF2.
The clock signal ICK is input via the NV2, and the input terminal I of the flip-flop FF1 is
N is configured to receive a signal ONdata.

The output terminal OUT of the flip-flop FF1 is connected to the input terminal IN of the flip-flop FF2, and is connected to the delay pulse generating circuit 38 as a terminal for outputting the signals OND0-F to OND7-F. The output terminal OUT of the flip-flop FF2 is connected to the signal O
The terminal for outputting ND0-L to OND7-L is connected to the delay pulse generation circuit 38.

Similarly, the clock signal ICK is directly input to the clock terminal CK of the flip-flop FF3, and the clock signal ICK is input to the clock terminal CK of the flip-flop FF4 via the inverter INV3. The signal OFFdata is input to the input terminal IN of the flip-flop FF3.

The output terminal OUT of the flip-flop FF3 is connected to the input terminal IN of the flip-flop FF4, and is connected to the delay pulse generating circuit 38 as a terminal for outputting the signals OFFD0-F to OFFD7-F. The output terminal OUT of the flip-flop FF4 is connected to the delay pulse generation circuit 38 as a terminal for outputting the signals OFFD0-L to OFFD7-L.

Further, as shown in FIG. 5, the delay pulse generation circuit 38 has a latch L for an ON signal and a latch L for an OFF signal, respectively.
T, data selector DS and D-type flip-flop DF
Eight blocks each including F are provided for each of blocks 1 to 8.

The control signal generating circuit 36 is provided in the latch LT for the ON signal of each block from block 1 to block 4.
OND0-F to signal OND7-
F is input, and signals OFFD0-F to signals OFFD7-F are input to the off signal latch LT.
Is configured to be input.

On the other hand, the signals OND0-ON are supplied to the latches LT for the ON signals of the respective blocks from block 5 to block 8.
L to the signal OND7-L are inputted, and the signal OFFD0-L to
The signal OFFD7-L is configured to be input.

The data selector DS of each block includes delay pulses T1 to T1 generated by the delay circuit 32.
It is configured such that T64s are grouped for each block and input. Further, the output terminal of the latch LT in each block is connected to the corresponding data selector DS, and the output terminal of the data selector DS is connected to the clock terminal CK of the corresponding D-type flip-flop DFF.

Here, from the latch LT to the data selector D
The signal output to S is the signal 8 bits latched by the latch LT, of which 6-bit signals on the MSB side (for example, OND2-F to OND2-F in the ON signal block 1).
The 6 bits of OND7-F are used in the data selector DS, and the remaining 2 bits of the LSB side signal (for example, OND0-F and OND1-F in the ON signal block 1).
2 bits) is the output terminal p for the ON signal.
1, p2,..., P8, and for the off signal, the output terminals q1, q2,.

The output terminals Q of the D-type flip-flops DFF in each block for the ON signal are all connected to the clock terminal CK of the D-type flip-flop DFFA, and the reset input terminals R are all connected to the D-type flip-flop D.
It is connected to the reset output terminal R of the FFA. Similarly, the output terminals Q of the D-type flip-flops DFF in each block for the OFF signal are all D-type flip-flops DFF.
The reset input terminals R are all connected to the reset output terminal R of the D-type flip-flop DFFB.

On the other hand, a delay pulse (for example, delay pulse T33 in the case of block 1 and delay pulse T1 in the case of block 5) corresponding to the timing one half cycle before is input to the latch LT of each block. It is configured.

A constant (for example, “1” for block 1 and “8” for block 8) equal to the number of the block to which it belongs is input to the data selector DS of each block in binary format. , And a selection signal select is input as an input selection signal. Here, the data selector DS selects the selection signal se.
When Lect is at a low level, a delay pulse (one of delay pulses T1 to T8 in the case of block 1) selected based on a signal input from the latch LT is output. Delay pulses of the same order in each block (blocks) according to the data of the bit position indicated by the binary constant of the input signal (for example, bit 0 when the binary constant is 1 and bit 1 when the binary constant is 2) If the delay pulse T1 is 1, the delay pulse T25 is output in the block 4, and the delay pulse 33) is output in the block 5. When the select signal select is at the high level, the laser driving device 10 operates in the bit stream mode, which will be described later.

The output terminal Q of the D-type flip-flop DFFA is connected to the input terminal D of the D-type flip-flop DFFB.
And a terminal for outputting the reference ON signal ON1 to the delay circuit 50. The output terminal Q of the D-type flip-flop DFFB is connected to the reference off signal O.
The terminal for outputting the FF1 is connected to the delay circuit 56, and the output terminal QB (Q bar) is connected to the input terminal D of the D-type flip-flop DFFA.

On the other hand, as shown in FIG. 6, the minute delay control signal generation circuit 40 includes two data selectors DSA and DSB for an ON signal and an OFF signal.

The input terminals of the data selector DSA include the output terminals p1, p2,..., P8 of the latch LT in each block for the ON signal of the delay pulse generation circuit 38 and the output terminals r1, r2, ..., r
8 is connected to the data selector DSA, a 2-bit signal on the LSB side of the signal latched by the on-signal latch LT is input, and an output signal from the on-signal data selector DS is supplied to the data selector DSA. It is configured to be input. Further, the selection signal select is input to the input selection terminal of the data selector DSA. When the selection signal select is at a low level, the signal input from the output terminal of the corresponding data selector DS is selected. The 2-bit signal is output in synchronization with the rising edge of the signal, and when the select signal select is at a high level, the 2-bit signal is forcibly set as (0,
0) is output. Further, the output terminal of the data selector DSA is connected to the input selection terminal of the multiplexer 52.

Similarly, the input terminals of the data selector DSB are connected to the output terminals q1, q2,... Of the latch LT in each block for the OFF signal of the delay pulse generation circuit 38.
q8 and output terminals s1, s2,.
, S8 are connected, and the data selector DSB receives a 2-bit LSB-side signal of the signal latched by the off-signal latch LT, and outputs the signal from the off-signal data selector DS. It is configured to receive an output signal. Also, the data selector DSB
Is configured to receive the selection signal “select” at its input selection terminal. When the selection signal “select” is at a low level, the selection signal is synchronized with the rising edge of the signal input from the output terminal of the corresponding data selector DS. Then, the 2-bit signal is output, and the selection signal select
When t is at a high level, (0, 0) is forcibly output as the 2-bit signal. Further, the output terminal of the data selector DSB is connected to the input selection terminal of the multiplexer 58.

On the other hand, the delay circuits 50 and 56
As shown in FIG. 3, the inverter INV has 10 stages (= 8 +
2) cascade connection
The output terminals of the even-numbered inverters INV other than the last stage are connected to the corresponding multiplexer 52 or multiplexer 58 as terminals for outputting the delay pulses T'1, T'2, T'3, T'4, respectively. An output terminal of the last-stage inverter INV is connected to the phase comparator 46 as a terminal for outputting the delay pulse T'5.

The inverter IN used here
V is the same as that used in the delay circuit 32. With respect to the inverter constituted by the PMOS transistor PT1 and the NMOS transistor NT1, a PMOS transistor PT2 and an NMOS transistor NT2 are provided on the source side of each transistor as a constant current circuit. Are connected.

Here, in this embodiment, since the delay pulse is generated using the inverter, the number of inverter stages is required to be 8 + 2. However, one inverter has the same delay time as that of two inverters. Needless to say, if a controlled inverter is separately provided and an inverted output can be used, 4 + 1 stages of inverters are sufficient.

On the other hand, delay circuit 48 also includes delay circuits 50 and 5
6, except that a delay pulse T65 is input to the delay circuit 48 as a signal to be delayed, and a terminal for outputting the delay pulse T'5 is connected to the phase comparator 46.

The delay pulse T 'is output from the phase comparator 46.
5 is compared with the phase of the output of the delay circuit 44 composed of the inverter INV for one stage of the delay circuit 32, and the delay pulse T'5, which is a clock delayed by one cycle, is
The constant current value of each inverter constituting the delay circuit 48 is controlled so as to synchronize with the output of the inverter.

The pulse width modulation circuit 14 serves as the first creating means of the present invention, the transmission lines L1 and L2 serve as the transmitting means of the present invention, the driver 54 and the driver 60 serve as the transmitting means of the present invention, and the receiver 72 and The receiver 74 is used as the receiving means of the present invention, the XOR circuit 76 is used as the second creating means and the creating means of the present invention, and the delay circuit 32, the delay circuit 50 and the delay circuit 56 are used as the delay pulse generating means of the present invention. The generation circuit 38 and the minute delay control signal generation circuit 40 correspond to the selection unit of the present invention, and the laser drive circuit 18 corresponds to the drive unit of the present invention.

Next, the operation of the laser driving device 10 configured as described above will be described with reference to FIGS.
7 to 9 are time charts showing an example of the state of each signal in the laser driving device 10. FIG. Here, a case will be described in which modulation is performed using an image signal of 8 bits (256 gradations) and the scanning time of one pixel is 25 nsec.

When the driving of the laser driving device 10 is started, the clock synchronizing circuit 30 synchronizes the clock signal CK with the synchronizing signal BD input from the light receiver 22 to the control signal generating circuit 36 as the clock signal ICK. At the same time, the clock signal ICK is further gated so as to be effective only during the driving period of the pulse width modulation circuit 14, and is output to the delay circuit 32 as the clock signal φ.

On the other hand, the image processing circuit 12 generates a signal ONdata indicating the transition timing of the ON signal ON of the pulse width modulation signal to be transmitted and a signal OFFdata indicating the transition timing of the OFF signal to generate the pulse width modulation signal.
To the control signal generating circuit 36 of FIG.

The delay circuit 32 outputs the clock signal φ input from the clock synchronization circuit 30 and the delay pulse T65 generated by itself to the phase comparator 42, and the delay pulse T65 And the phase of the clock signal φ, and controlling the constant current value of each inverter INV constituting the delay circuit 32 so that the delay pulse T65 is synchronized with the clock signal φ.
The delay pulse T65 at the last stage is synchronized with the next clock signal.

At this time, as described above, by using the inverted output, the delay circuit 3 is formed by 65 stages of inverters.
2, the PMOS transistor and the NMO
Since it is necessary to independently control the delay of the S transistor and equalize the rising time and the falling time, the PMO
A separate control circuit must be provided for each of the constant current circuits of the S transistor and the NMOS transistor.

The delay circuit 32 operates under the above conditions.
The output signals of the inverters INV except the last stage are output as delay pulses T1, T2,.
To the delay pulse generation circuit 38 via

On the other hand, the control signal generation circuit 36 latches the signal ONdata at the rising edge of the clock signal ICK by the flip-flop FF1, and outputs the signals OND0-F to
OND7-F are generated, and the signals OND0-L to OND7-L shifted by a half cycle are generated by using an inverted signal of the clock signal ICK by the flip-flop FF2.

Similarly, the signal OFFdata is output by the flip-flop FF3 at the rise of the clock signal ICK.
Are latched to generate signals OFFD0-F to OND7-F, and further, flip-flop FF4 uses inverted signals of clock signal ICK to generate signals OFFD0-L to OFFD7-L shifted by a half cycle.

As described above, by shifting each signal by a half cycle, a sufficient setup and hold time for data can be ensured when each block is sequentially latched by the latch LT of the delay pulse generation circuit 38.

On the other hand, as described above, the delay pulse generation circuit 38 outputs a delay pulse selected based on a signal input from the latch LT or outputs a delay pulse based on a binary constant. Selector DS
Is selected, the selection signal Select is at a low level, and the delay pulse corresponding to the signal input from the latch LT is supplied to the D-type flip-flop DFF of the next stage. Output to clock terminal CK.

In the D-type flip-flop DFF of the ON signal block, the output terminal Q becomes high level by the rising trigger of the signal input to the clock terminal CK,
The signal is input to the clock terminal CK of the D-type flip-flop DFFA. In the D-type flip-flop DFFA, the state of the input terminal D of the D-type flip-flop DFFA is changed to the output terminal Q by the rising trigger of the clock terminal CK.
Is output to Here, the input terminal D has a D signal for an off signal.
Since the output terminal QB of the type flip-flop DFFB is connected, a signal obtained by inverting the reference off signal OFF1 is output from the output terminal Q as the reference on signal ON1.

The operation of the D-type flip-flop DFFB for the OFF signal is the same as that of the above-mentioned D-type flip-flop DFFA. Because of the connection, the reference ON signal ON1 is output from the output terminal Q as the reference OFF signal OFF1.

The signal input to the latch LT of each block is latched by a trigger pulse (delay pulse) about half a cycle before actually selecting a delay pulse, and is used to select a delay pulse after a half cycle. . Here, the reason for latching with the trigger pulse one half cycle before is the latch L as described above.
This is for securing the setup hold time of T. In addition, by using every eight delay pulses as a latch trigger pulse for each block,
All the latches LT are triggered almost half a cycle before the actual delay pulse is selected, so that a constant setup hold time is always secured.

D-type flip-flop DF in each block
F is because the output terminal Q is a wired OR,
The D-type flip-flop DFFA and the D-type flip-flop DFFB operate so that the rising pulse from any block operates.

The reset output terminal R of the D-type flip-flop DFFA and the D-type flip-flop DFFB is output from the output terminal Q after the rising pulse is input to the clock terminal CK.
Is a signal indicating that the state has been determined. When the state is determined, it becomes a high level. When this signal is input to the reset input terminal R of the D-type flip-flop DFF of each block, each D-type flip-flop DFF is reset, and the output terminal Q of the D-type flip-flop DFF returns to a low level. The D-type flip-flop DF of each block
The reset input terminal R of F is a rising trigger.

Repetition of turning on within a block or between adjacent blocks is meaningless in terms of image quality, and is not supported by the laser driving device 10 according to the present embodiment.

The reason why the transition to ON within a block or between adjacent blocks cannot be repeated is due to the control restriction of the minute delay control signal generation circuit 40, which will be described later. It is possible to cope with such a request as four channels.

In the delay pulse generation circuit 38 configured as described above, when the transition to the on level continues, if the transition to the off level is not in the middle, the reference on signal ON1
Does not flip. This is because the reference ON signal ON1 always inverts the reference OFF signal OFF1. Also,
When the transition to the off level occurs, the reference off signal OFF1 outputs the value of the reference on signal ON1 as it is. That is, when it is desired to make a transition to the on level, an inverted signal of the reference off signal OFF1 is transmitted as the reference on signal ON1, and when it is desired to make a transition to the off level, the reference on signal ON1 is transmitted as it is as the reference off signal OFF1. . This limits the combination of the transition to the on-level and the transition to the off-level,
The pulse width modulation signal can be generated by the XOR circuit. Further, in this circuit, the transition to the on level and the transition to the off level always occur alternately, so that it is possible to prevent the frequency band of the transmission signal from being unnecessarily widened.

The operation of the delay pulse generation circuit 38 will be described in more detail. As shown in FIG. 7, when attention is paid to, for example, the block 1 for the ON signal, the delay is caused by the rising trigger of the delay pulse T33 at the node (d). Pulse T5
Are output, a high level is output to the node (b) by the rising trigger of the delay pulse T5, and a low level is output to the node (c). You. As a result, the reference ON signal ON1 transitions to the high level at a timing slightly delayed from the rise of the delay pulse T5, and at the same time, the reset output terminal R of the D-type flip-flop DFFA goes to the high level to cause the ON signal in each block for the ON signal. Is reset, and the state of the node (b) and the node (c) returns to the original state.

Similarly, when attention is paid to, for example, the block 4 for the OFF signal, the delay pulse T57 is applied to the node (h).
When the signals OFFD2-F to OFFD7-F indicating the selection of the delay pulse T30 are output at the rising trigger of, the high level is output to the node (f) by the rising trigger of the delay pulse T30, and the node (g) is output. Outputs a low level. As a result, the reference off signal O
The FF1 transitions to the high level at a timing slightly delayed from the rise of the delay pulse T30, and at the same time, the reset output terminal R of the D-type flip-flop DFFB goes to the high level, and the D-type flip-flop DFF in each block for the off signal. Is reset, and the states of the node (f) and the node (g) return to the original state.

As shown in FIG. 2, the delay pulse generation circuit 3
The reference ON signal ON1 and the reference OFF signal OFF1 output from 8 are input to the delay circuit 50 and the delay circuit 56, respectively, and the delay is finely adjusted. In the present embodiment, the delay circuit 50 and the delay circuit 56 adjust the delay of each stage in phase so that the delay time per stage of the delay element (inverter INV) in the delay circuit 32 is further divided into four. The output of the delay circuit 50 and the delay circuit 56, that is, the delay pulse T ′ is controlled by the comparator 46.
1, T'2, T'3, and T'4 are output to a multiplexer 52 and a multiplexer 58 each having four inputs and one output.

Multiplexer 52 and Multiplexer 5
8, the signal OND0 from the minute delay control signal generation circuit 40;
-7 and 2-bit data on the LSB side of the signals OFFD0-7 are input, and one of the delay pulses generated by the delay circuits 50 and 56 is selected according to the input data. , And fine-tune the delay.

Next, the operation of the minute delay control signal generation circuit 40 will be described with reference to FIGS. As described above, the data selector DSA of the minute delay control signal generation circuit 40 supplies a signal (signal ON) of two bits on the LSB side of the signal latched by the ON signal latch LT.
D0, OND1) and the output signal from the data selector DS for the ON signal, and when the select signal select is at the low level, the signal is input from the output terminal of the corresponding data selector DS. The 2-bit signal is input to the input selection terminal of the multiplexer 52 in synchronization with the rise of the signal.

Similarly, the data selector DSB has the LSB of the signal latched by the off-signal latch LT.
2 bit signal (signal OFFD0, OFFD1)
And the data selector DS for the off signal
And the selection signal select
When t is at the low level, the 2-bit signal is input to the input selection terminal of the multiplexer 58 in synchronization with the rise of the signal input from the output terminal of the corresponding data selector DS.

As described above, the input selection signal to the corresponding multiplexer is input to the multiplexer at the same timing, and since the input selection signal is an edge trigger, the transition to the on level is performed every other block. Can be repeated.

The operation of the minute delay control signal generation circuit 40 will be described in more detail. As shown in FIG. 8, for example, a delay pulse T33 is applied to the node (d) of the ON signal block 1.
When the signals OND0-F to OND7-F indicating the selection of the delay pulse T1 are output by the rising trigger of the data selector DSA from the data selector DSA to the multiplexer 52 at a timing slightly delayed from the rising of the delay pulse T1. OND1 is output. The reference ON signal ON1 transits to a high level a little later than this, and the delay circuit 50 based on the reference ON signal ON1 is used as a reference.
Generates delay pulses T'1, T'2, T'3, T'4, and one of these delay pulses is selected by the multiplexer 52 based on the signals OND0 and OND1, and is set as the ON signal ON by the driver. It is output to 54.

Further, for example, a signal OFFD0-F indicating that the delay pulse T26 is selected by the rising trigger of the delay pulse T57 at the node (h) of the off signal block 4.
~ OFFD7-F is output, the delay pulse T
The signal OFB from the data selector DSB to the multiplexer 58 is slightly delayed from the rise
FD0 and OFFD1 are output. Slightly later than this, the reference off signal OFF1 transitions to the high level, and the delay circuit 56 generates delay pulses T′1, T′2, T′3, and T′4 based on the reference off signal OFF1. One of the delay pulses is OFF
The signal is selected by the multiplexer 58 based on D0 and OFFD1, and is output to the driver 60 as an OFF signal OFF.

The ON signal ON and the OFF signal OFF generated in this manner are supplied to the driver 54 and the driver 6 respectively.
The signal is transmitted to the transmission line L1 and the transmission line L2 via 0. At this time, since the frequency of the transmission signal (ON signal ON, OFF signal OFF) is low in the driver 54 and the driver 60, transmission can be performed at a conventional TTL level, or transmission can be performed by differential using LVDS. it can.

The ON signal ON and the OFF signal OFF transmitted by the transmission lines L1 and L2 are input to the XOR circuit 76 via the receiver 72 and the receiver 74 provided in the demodulation circuit 16, respectively. P
WM is generated and input to the laser drive circuit 18.

In the laser drive circuit 18, under the condition that the APC of the laser 20 is performed based on the light amount signal input from the light receiver 24 provided in the laser 20, the laser drive circuit 18 operates in accordance with the input pulse width modulation signal PWM. A driving current is supplied to the laser 20, and the laser 20 is turned on according to the supplied driving current.

Next, a bit stream mode executed by setting the select signal select to a high level will be described with reference to FIGS.

As described above, when the selection signal Select is set to the high level, the output of the data selector DS shown in FIG. 5 is based on a fixed binary constant. (For example, if the binary constant is 3, the signal OND2-
The control is performed by the value of the data line of bit 4 of F). If the signal is low, the delay pulse is not transmitted to the D-type flip-flop DFF, and if the signal is high, it is transmitted. As a result, the parallel data in the eight transmission lines is converted into serial data and output from the output terminal Q of the D-type flip-flop DFF.

That is, as shown in FIG. 9, for example, focusing on the ON signal block 1, the node (d)
At the rising trigger of the delay pulse T33 (1100
When the data “1100” is output, the node (b) has a high level with respect to “1” and becomes “0” at the rising trigger of the delay pulse of a predetermined order (the delay pulse T1 in the example shown in the figure). On the other hand, the low level is serially output. As a result, the reference ON signal ON1 is maintained at a high level according to the continuous period of “1”,
The low level is maintained according to the continuous period of “0”.

Similarly, focusing on the block 4 for the OFF signal, when the data (00110011) is output to the node (h) by the rising trigger of the delay pulse T57, the node (f) outputs the delay of the predetermined order to the node (f). A high level for "1" and a low level for "0" are serially output at the rising trigger of the pulse (the delay pulse T25 in the example shown in the figure). As a result, the reference OFF signal OFF1 is maintained at a high level according to the continuous period of “1” and is maintained at a low level according to the continuous period of “0”.

In a current image forming apparatus using a laser beam, a method of expressing the density indicated by the image data by a pulse width modulation signal as described above is mainly used. However, since this method has a large amount of data, In the future, it is expected that a digital control method for expressing density in the bit stream mode, which can reduce the amount of data, will be used. Therefore, the laser driving device 10 according to the present embodiment
Is configured to be compatible with this bit stream mode.

As described above in detail, in the laser driving device according to the first embodiment, the ON signal having the first edge corresponding to the ON timing of the pulse width modulation signal to be transmitted, and the pulse width from the ON timing. An off signal having a second edge corresponding to the off timing after the pulse width of the modulation signal is generated and transmitted on different transmission lines, and the first signal is received by receiving the on signal and the off signal from the transmission line. Since the pulse width modulation signal is generated from the edge and the second edge, the pulse width of each of the ON signal and the OFF signal transmitted through the transmission line can be made large, and as a result, the electromagnetic radiation , A pulse width modulation signal with good reproducibility can be transmitted over a wide duty range at low cost while suppressing noise.

In the laser driving device according to the first embodiment, the state of the off signal changes after the state of the on signal changes, and the state of the on signal returns to the original state after the change of the off signal. Since the on signal and the off signal are generated so that the state of the off signal returns to the original state after the state of the on signal returns to the original state, the pulse width of the pulse width modulation signal is such that the rising edges of the on signal and the off signal, or Since the pulse width is limited to the difference between the falling edges, variation in the pulse width can be suppressed.

[Second Embodiment] In the first embodiment,
Although one embodiment in which the laser driving device 10 is configured without considering the skew of the transmission line L1 and the transmission line L2 has been described, in the second embodiment, the laser driving device 10
An embodiment in which the function of correcting the skew is provided will be described.

There are two modes in which a function for correcting skew in the transmission line is provided, that is, a mode provided on the receiving side as shown in FIG. 10 and a mode provided on the transmitting side as shown in FIG. Conceivable.

Considering the ease of skew correction, it is desirable to provide it on the receiving side. In this case, the correction is performed by transmitting the ON signal ON and the OFF signal OFF when the pulse width of the pulse width modulation signal is zero from the pulse width modulation circuit 14 to the transmission lines L1 and L2 as reference pulses, respectively. The ON signal ON and OFF signal OFF waveforms transmitted to the skew correction circuit 15A and the skew correction circuit 15A detect the phase difference between the ON signal ON and the OFF signal OFF. Correction circuit 15
An example is shown in which a signal is input to at least one of B and is performed by at least one of the skew correction circuit 15A and the skew correction circuit 15B.

On the other hand, when a skew correction circuit is provided on the transmission side, a reference pulse is transmitted from the transmission side, a reference pulse is received on the reception side, and a phase difference is detected by a phase comparator (not shown). The skew correction circuit 15A and the skew correction circuit 1 on the transmitting side send the detection result of the phase difference by some method
It is necessary to feed back to at least one of 5B. For this reason, in this case, means for superimposing a signal indicating the detection result of the phase difference on the skew execution signal is required, but various existing techniques can be applied as a signal superimposition method.

FIG. 12 shows a specific circuit configuration example applicable to the skew correction circuit 15.

In the circuit shown in FIG. 12A, a plurality of inverters functioning as delay elements are arranged in a cascade, and a multiplexer MPX selects an inverter tap based on a detection result of a phase difference so that the skew is minimized. Is what you do. In this circuit, the correction delay amount is n times (n is an even number) the delay time per delay gate stage. Therefore, the skew correction circuit 15 to which this circuit is applied is provided in only one of the transmission line L1 and the transmission line L2. Or just

In the circuit shown in FIG. 12B, a plurality of inverters each having a different delay time are arranged, and one having the smallest skew is selected by the multiplexer MPX. In this case, the minimum delay amount of the control circuit tends to increase, and the transmission line L1 and the transmission line L2
However, it is also possible to adopt a configuration in which one of the transmission line L1 and the transmission line L2 is lengthened so as to be delayed more than the minimum delay amount, and only the other is adjusted.

A skew correction circuit 15 shown in FIG.
As shown in FIG. 12D, an inverter composed of a PMOS transistor PT1 and an NMOS transistor NT1 and having a gate width W of the transistor adjusted according to the delay time can be applied as the inverter in.

On the other hand, the circuit shown in FIG. 12C realizes different delay times by making the delay times of the respective inverters the same and adjusting the additional capacitance of the capacitors provided on the output side of each inverter. Things.

Further, as shown in FIG.
There is also a method in which a constant current circuit is added to the source side of each transistor in the inverter shown in (D), as shown in FIG. As a control method at this time, conP and con which are constant current source control signals of the PMOS transistor PT1 and the NMOS transistor NT1 are used.
A method of adjusting the amount of delay by controlling N for each inverter,
There is a method in which the delay amount is adjusted in advance for each inverter by adjusting the value of the gate width W, and the signal conP and the signal conN are controlled when it is desired to adjust the delay time as a whole. The control signal conP and the control signal conN at this time are shown in FIG.
It is preferable to use a current mirror circuit as shown in FIG.

FIG. 13 shows a configuration example of the skew correction circuit 15 configured by combining these.

This skew correction circuit 15 is shown in FIG.
1 is applied as a delay circuit 80A for an ON signal and a delay circuit 80B for an OFF signal.
The current mirror circuit shown in FIG. 2 (F) is used as a current setting circuit 88A and a current setting circuit 88B, respectively.

The skew correction circuit 15 includes, in addition to the delay circuit 80A and the delay circuit 80B, a flip-flop FF composed of two two-input NAND1 and NAND2, an up / down counter 82A for an ON signal,
It is configured to include an up / down counter 82B for an off signal and the like.

The ON signal ON (in) input to the skew correction circuit 15 is connected to the input terminals of all the inverters included in the delay circuit 80A.
The output terminal of the multiplexer MPX is a flip-flop F
F is connected to one input terminal of NAND1 and
It is connected to one input terminal of AND3. The output terminal of the multiplexer MPX of the delay circuit 80A is an output terminal of the ON signal ON (out).

The OFF signal OFF (in) input to the skew correction circuit 15 is connected to the input terminals of all the inverters included in the delay circuit 80B, and the output terminal of the multiplexer MPX of the delay circuit 80B is connected to a flip-flop. The flip-flop FF is connected to one input terminal of NAND2 and to the other input terminal of NAND3. Note that the output terminal of the multiplexer MPX of the delay circuit 80B is an output terminal of the off signal OFF (out).

Further, the output terminal of NAND1 is connected to the other input terminal of NAND2, the output terminal of NAND2 is connected to the other input terminal of NAND1, and the up / down switching terminal U / of the up / down counter 82A is connected. D and is connected to the up / down switching terminal U / D of the up / down counter 82B via the inverter INV1.

The output terminal of NAND3 is connected to delay element 84.
Are connected to the clock terminals CK of the up / down counters 82A and 82B.

On the other hand, the up / down counter 82A and the up / down counter 82B are provided with an output terminal zero that goes high when the count value is 0 (zero), and the output terminal ze of the up / down counter 82A.
ro is connected to the other input terminal of OR2 having one input terminal connected to the output terminal of NAND2, and the output terminal zero of the up / down counter 82B is connected to one input terminal of N.
The output terminal of AND2 is connected to the other input terminal of OR1 connected via inverter INV1.

The output terminal of OR1 has a signal desk which goes high when skew correction is performed on one input terminal.
ew is connected to the other input terminal of AND1 to which the signal de is input, and the output terminal of OR2 is connected to one input terminal of the signal de.
skew is connected to the other input terminal of AND2 to which the skew is input, and the output terminal of AND1 is connected to an up-down counter 8
The output terminal of AND2 is connected to the enable terminal EN of the up-down counter 82B, and the output terminal of AND2 is connected to the enable terminal EN of the up-down counter 82B.

Further, the output terminal OUT for outputting the count value of the up / down counter 82A is connected to the input selection terminal of the multiplexer MPX in the delay circuit 80A, and the output terminal OUT for outputting the count value of the up / down counter 82B is connected to the delay terminal. It is connected to the input selection terminal of the multiplexer MPX in the circuit 80B.

The operation of the skew correction circuit 15 will be described below with reference to a time chart shown in FIG.

As shown in FIG. 14, the ON signal ON (i
When n) is inputted, which rises slightly earlier than the OFF signal OFF (in), the ON signal ON is inputted to the flip-flop FF via the delay circuit 80A, and the OFF signal OFF is outputted to the delay circuit 80B. The signal is input to the flip-flop FF via the FF.

If the inverter t1 is selected as the output of the multiplexer MPX of each of the delay circuits 80A and 80B, the ON signal ON and the OFF signal O
The FF is input to the flip-flop FF while maintaining the phase difference. In this case, the state of the flip-flop FF is determined by the OFF signal OFF which has become high level later. That is, when the ON signal ON and the OFF signal OFF go to the high level, the output signal FFA of the NAND 1 is at the low level, and the output signal FFB of the NAND 2 is at the high level. The signal AND indicating this is sent to the clock terminal CK of the up-down counter 82A and the up-down counter 82B as a signal ANDdelay via the delay element 84.

Here, the OFF signal OFF is the ON signal O
N, the count value of the up / down counter 82B must be reduced so that the OFF signal OFF is earlier, but the multiplexer MPX of the delay circuit 80B
As described above, the output of the inverter t1 is selected, and in this state, the count value of the up / down counter 82B is zero and the output terminal zero is at the high level.

Therefore, the up / down counter 82A is enabled, the count value of the up / down counter 82A increases, and the operation is performed so that the ON signal ON is delayed to adjust the phase.

If the inverter selected by the delay circuit 80B is other than t1, the up / down counter 82B
Does not output the output signal zero signal, the up / down counter 82A is disabled, and only the up / down counter 82B decreases to operate to reduce the delay amount of the off signal OFF.

As described above, when adjusting the phase, priority is given to the operation of reducing the amount of delay added in common as much as possible, thereby preventing unnecessary accumulation of delay.
Thus, a relative error can be reduced when a plurality of pulse width modulation circuits are used as in a color laser printer.

Also, the delay amount adjustment function here can be used positively, for example, when adjusting registration between colors in a color printer.

As described above, the skew correction circuit 1 shown in FIG.
In FIG. 5, an example of digital control is described. However, in this method, the skew cannot be finely adjusted because the delay amount is predetermined.

On the other hand, the skew correction circuit 15 shown in FIG. 15 can adjust the skew with higher accuracy.

The basic algorithm is the same as that of the skew correction circuit 15 shown in FIG. 13. However, instead of the delay circuits 80A and 80B, a variable delay inverter capable of controlling the delay amount shown in FIG. Delay circuit 8 used
The difference is that the OC and the delay circuit 80D are applied. An up / down counter 82 similar to that shown in FIG. 13 is connected to control terminals of the delay circuits 80C and 80D via a current output type D / A converter 86.

The operation is almost the same as that shown in FIG. 13, and the value of the up / down counter 82 on the delayed side is increased or decreased.
Accordingly, the delay amount of the variable delay inverter changes, and the skew approaches zero. Needless to say, since the accuracy at this time is determined by the accuracy of the D / A converter 86, the bit width must be determined in accordance with the skew correction accuracy required together with the up / down counter 82.

The skew correction circuit 15 is the correction means of the present invention, the delay circuits 80A, 80B, 80C and 80D are the pulse signal delay means of the present invention, and the parts other than the delay circuit of the skew correction circuit 15 are the adjustment means of the present invention. Respectively.

In addition, as a method of reducing the skew to zero, there is also a system of an all-analog configuration using a phase comparator and an amplifier. However, it is necessary to perform calibration at least in units of pages, and the droop of the sample / hold circuit is required. However, the description is omitted here. The reason that calibration is required at least in units of pages is that if control is performed for each laser scan, the skew cannot be completely reduced to zero, so that the adjustment value slightly fluctuates for each calibration. This is because the registration between colors and the variation in pulse width are changed for each line of scanning.

As described in detail above, the laser driving apparatus according to the second embodiment can provide the same effects as those of the first embodiment, and can also receive the ON signal and the OFF signal, respectively. Since the time shift is corrected by the skew correction circuit, it is possible to prevent variations in pulse width due to skew in the transmission line.

[0210]

As described above in detail, according to the signal transmission apparatus of the present invention, the first pulse signal having the first edge corresponding to the on-timing of the pulse width modulation signal to be transmitted and the first pulse signal are turned on. A second pulse signal having a second edge corresponding to an off-timing that has passed by the pulse width of the pulse width modulation signal from the timing is created and transmitted by different transmission means, and the first pulse signal from the transmission means is transmitted. Since the pulse signal and the second pulse signal are received and the pulse width modulation signal is created from the first edge and the second edge, the first pulse signal and the second pulse signal transmitted via the transmission unit are generated. The pulse width of each pulse signal can be made large, thereby transmitting a pulse width modulation signal with good reproducibility over a wide duty range at a low cost while suppressing electromagnetic radiation. Can, effect that.

Further, according to the signal transmitting apparatus of the present invention, the first signal corresponding to the on-timing of the pulse width modulation signal can be obtained.
And a second pulse signal having a second edge corresponding to the off-timing that has elapsed from the on-timing by the pulse width of the pulse width modulation signal, and transmitting each of them. Therefore, the pulse width of each of the first pulse signal and the second pulse signal can be made large, and thereby the pulse width modulation signal having good reproducibility over a wide duty range at low cost while suppressing electromagnetic radiation. Can be transmitted.

Further, according to the signal receiving apparatus of the present invention, the first signal corresponding to the on-timing of the pulse width modulation signal can be obtained.
Receiving a first pulse signal having a second edge and a second pulse signal having a second edge corresponding to an off-timing having elapsed by the pulse width of the pulse width modulation signal from the on-timing, Since the pulse width modulation signal is generated from the second edge, the pulse width of each of the first pulse signal and the second pulse signal can be made large, and thereby, the electromagnetic radiation can be suppressed and the pulse width can be reduced. An effect is obtained that a pulse width modulation signal with good reproducibility can be transmitted over a wide duty range at a low cost.

Further, according to the laser driving device of the present invention, the laser is driven based on the pulse width modulation signal obtained by the signal transmitting device or the signal receiving device of the present invention. The advantage is that the laser can be driven at low cost and with high precision.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a laser driving device according to a first embodiment.

FIG. 2 is a block diagram illustrating a detailed configuration of a pulse width modulation circuit and a demodulation circuit of the laser driving device according to the first embodiment.

FIG. 3 illustrates a delay circuit 32 and a delay circuit 5 according to the embodiment.
It is a circuit diagram which shows the example of a structure of 0 and 56.

FIG. 4 is a circuit diagram showing a configuration example of a control signal generation circuit in the pulse width modulation circuit according to the embodiment.

FIG. 5 is a circuit diagram illustrating a configuration example of a delay pulse generation circuit in the pulse width modulation circuit according to the embodiment;

FIG. 6 is a circuit diagram illustrating a configuration example of a minute delay control signal generation circuit in the pulse width modulation circuit according to the embodiment;

FIG. 7 is a time chart for explaining the operation of the delay pulse generation circuit in the pulse width modulation circuit according to the embodiment;

FIG. 8 is a time chart for explaining the operation of the minute delay control signal generation circuit in the pulse width modulation circuit according to the embodiment;

FIG. 9 is a time chart for explaining an operation in a bit stream mode of the laser driving device according to the embodiment;

FIG. 10 is a block diagram illustrating a schematic configuration of a laser driving device according to a second embodiment.

FIG. 11 is a block diagram illustrating a schematic configuration of another laser driving device according to the second embodiment.

FIG. 12 is a circuit diagram illustrating a configuration example of a circuit applicable to a skew correction circuit according to a second embodiment.

FIG. 13 is a circuit diagram illustrating a configuration example of a skew correction circuit according to a second embodiment.

FIG. 14 is a time chart for explaining the operation of the skew correction circuit in FIG. 13;

FIG. 15 is a circuit diagram illustrating another configuration example of the skew correction circuit according to the second embodiment.

FIG. 16 is a block diagram illustrating a configuration example of a conventional laser beam printer.

FIG. 17 is a time chart showing a state of a main part signal and a printing state in FIG. 16;

FIG. 18 is a waveform chart for explaining a problem of the related art.

FIG. 19 is a graph showing an ideal pulse width conversion state.

FIG. 20 is a circuit diagram showing an example of a circuit configuration for simply implementing pulse width conversion.

FIG. 21 is a schematic diagram for explaining a problem when a pulse width is simply shortened in a conventional technique.

FIG. 22 is a waveform chart for explaining effects of the present invention.

FIG. 23 is a waveform chart for explaining effects of the present invention.

FIG. 24 is a waveform chart for explaining effects of the present invention.

FIG. 25 is a block diagram illustrating a basic configuration of a laser driving device according to the present invention, and a waveform diagram illustrating a state of a main part signal.

FIG. 26 is a schematic diagram showing a combination state of an ON signal and an OFF signal.

FIG. 27 is a time chart for explaining a conventional technique;

FIG. 28 is a time chart for explaining a conventional technique;

FIG. 29 is a circuit diagram for explaining a conventional technique;

FIG. 30 is a block diagram for explaining a conventional technique.

FIG. 31 is a time chart for explaining problems of the related art.

[Explanation of symbols]

Reference Signs List 10 laser drive device 12 image processing circuit 14 pulse width modulation circuit (first creation means) 15 skew correction circuit (correction means) 16 demodulation circuit 18 laser drive circuit (drive means) 20 laser 32 delay circuit (delay pulse generation means) 36 control signal generation circuit 38 delay pulse generation circuit (selection means) 40 minute delay control signal generation circuit (selection means) 50 delay circuit (delay pulse generation means) 54, 60 driver (transmission means) 56 delay circuit (delay pulse generation means) 72, 74 Receiver (receiving means) 76 XOR circuit (second creating means and creating means) 80A, 80B, 80C, 80D Delay circuit (pulse signal delay means) L1, L2 Transmission line (transmission means)

Claims (9)

[Claims] 1. A first pulse signal having a first edge corresponding to an ON timing of a pulse width modulation signal to be transmitted, and a first pulse signal corresponding to an OFF timing corresponding to a pulse width of the pulse width modulation signal from the ON timing. First generating means for generating a second pulse signal having two edges; different transmitting means for transmitting the first pulse signal and the second pulse signal, respectively; and 1 pulse signal and the second pulse signal
Receiving means for receiving the first pulse signal and second receiving means for generating a pulse width modulation signal from the first edge and the second edge of the received first pulse signal and the second pulse signal; A signal transmission device comprising: 2. The method according to claim 1, wherein said first means received by said receiving means.
The signal transmission device according to claim 1, further comprising a correction unit configured to correct a time lag between each of the pulse signal and the second pulse signal. 3. The transmitting device for transmitting the first pulse signal, and the second transmitting device transmits the first pulse signal.
Pulse signal delay means provided in at least one of the transmission means for transmitting the pulse signal, and capable of changing the delay time for delaying and outputting the input pulse signal; and the pulse signal so as to reduce the time lag. 3. The signal transmission device according to claim 2, further comprising adjusting means for adjusting a delay time by the delay means. 4. The method according to claim 1, wherein the first generating means generates a second edge in the second pulse signal after the first edge has occurred in the first pulse signal, and generates the second edge after the second edge has occurred. The first pulse signal generates an edge opposite to the first edge, and the first pulse signal causes the first pulse signal to generate an edge opposite to the second edge in a second pulse signal. The signal transmission device according to any one of claims 1 to 3, wherein the pulse signal and the second pulse signal are generated. 5. The method according to claim 1, wherein the first generating unit delays a clock signal for synchronizing the pulse width modulation signal at intervals of a time shorter than one cycle of the clock signal, and generates a plurality of delayed pulses synchronized with the clock signal. A delay pulse generating means for generating; a delay pulse having a first edge corresponding to the on-timing from a plurality of delay pulses generated by the delay pulse generating means; and a second edge corresponding to the off-timing. 5. The signal transmission device according to claim 1, further comprising: a selection unit that selects each of the delayed pulses as the first pulse signal and the second pulse signal. 6. . 6. A first pulse signal having a first edge corresponding to an on-timing of a pulse width modulation signal, and a second edge corresponding to an off-timing having elapsed from the on-timing by a pulse width of the pulse width modulation signal. A signal transmitting device, comprising: first generating means for generating a second pulse signal having: and transmitting means for transmitting each of the first pulse signal and the second pulse signal. 7. A first pulse signal having a first edge corresponding to an on-timing of a pulse width modulation signal, and a second edge corresponding to an off-timing having elapsed from the on-timing by a pulse width of the pulse width modulation signal. Receiving means for receiving a second pulse signal having: and generating means for generating a pulse width modulation signal from a first edge and a second edge of the received first pulse signal and the received second pulse signal. A signal receiving device comprising: 8. A drive for driving a laser based on the signal transmission device according to claim 1 and a pulse width modulation signal created by a second creation unit of the signal transmission device. Means, and a laser drive device comprising: 9. A laser driving apparatus comprising: the signal receiving apparatus according to claim 7; and driving means for driving a laser based on the pulse width modulation signal created by the creating means of the signal receiving apparatus.