JP2001249325A - Plasma-address liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma-address liquid crystal display device, which decreases the number of necessary compensation circuits by compensating a writing reference potential and is capable of reducing luminance unevenness. SOLUTION: This plasma address liquid crystal display device has a liquid crystal panel section, which consists of liquid crystal cells 1 having liquid crystal layers, plasma cells 2 having cathode electrodes 22 and anode electrodes 23 and a thin dielectric layer 31, disposed between both cells 1 and 2 and a drive section 4 which drives the liquid crystal panel section. The drive section 4 has means for increasing the amplitude of anode drive signals together with time within one vertical period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a plasma addressed liquid crystal display, and more particularly to a plasma addressed liquid crystal display in which the amplitude of an anode drive signal is controlled.

[0002]

2. Description of the Related Art A liquid crystal display device has attracted attention as a flat display device, and a plasma-addressed liquid crystal display device (PALC) is known as one of them. The PALC includes a display unit and a driving unit 4 that drives the display unit. As shown in FIG. 9, the display unit includes a liquid crystal cell 1 having a glass substrate 11, a color filter layer 12, a signal electrode 13, a liquid crystal layer 14, etc., a glass substrate 21, and an anode electrode 2.
2, cathode electrode 23, rib 24, plasma discharge space 2
5 and a thin dielectric layer 31 provided between the cells 1 and 2. Then, it can be described that the virtual electrode 26 and the plasma switch 27 of the plasma cell 2 operate and display is performed as shown in FIG. 10 by the applied anode drive current.

As shown in FIG. 11, a driving circuit which is a driving section 4 of a conventional PALC includes a timing signal generating circuit 42.
', Switching control circuit 43', switching circuit 4
6 ', etc. The timing signal generation circuit 42 '
Based on the input vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync), a reference control signal serving as an operation reference of the switching control circuit 43 'is generated. The switching control circuit 43 'generates alternate drive control signals Vhigh and Vlow for alternately turning on the two types of transistors of the switching circuit 46'. Vhigh, V
low is the high level of the anode signal, l
This is a potential giving an ow level. Switching circuit 46
'Generates an anode signal by switching between Vhigh and Vlow from the switching control circuit 43'.

Japanese Patent Application Laid-Open No. 5-119748 discloses a technique for compensating an execution voltage value applied to a liquid crystal. However, this is a method for compensating a data signal. For example, when RGB data is sent in parallel, three compensating circuits are required.

As a typical driving method of PALC, 1H
Inversion driving is known. In this driving method, as shown in FIG. 12, the writing polarity of the liquid crystal signal is switched every row, and the polarity of the liquid crystal signal is further switched every frame. This makes it possible to convert the applied voltage into an alternating current, suppress flicker, and prevent deterioration of the liquid crystal. However,
In this drive method, when the liquid crystal is used in normally black, problems such as a decrease in contrast and a decrease in white luminance occur. This is a problem peculiar to the PALC driving method,
If the charged particle annihilation time after the occurrence of the plasma discharge is long, a part of the next row data signal is written, thereby making it impossible to write a desired data signal amplitude, lowering the contrast,
A decrease in white luminance occurs.

As a driving method for solving the problems of lowering the contrast and lowering the white luminance, 1F (initial of Frame or Field) inversion driving has been proposed. In this driving method, as shown in FIG. 13, the polarity of a signal to be written to the liquid crystal is switched every 1F. All lines (all screens) have the same polarity. According to this driving method, the polarity of the data signal to be written to the liquid crystal does not change every 1H, so that the charged particle annihilation time after the plasma discharge increases, and even if a part of the signal of the next row data is written. 1H
There is no large deviation from the desired data signal level as compared with the inversion driving. The applied voltage is converted to an alternating current to prevent the liquid crystal from deteriorating.

However, even in the 1F inversion driving method, a new problem such as a luminance change in the vertical direction occurs. This is a particular problem due to the PALC structure. FIG. 14 shows an equivalent circuit per pixel of PALC. At the time of selection, the plasma switch 27 is turned on, and a desired voltage is written to the liquid crystal capacitance Clc19. Since the plasma switch 27 is off at the time of non-selection, Vlc49 at the time of non-selection is written as crosstalk through the dielectric sheet and the coupling capacitance Cpz29 formed by the cathode electrode and the anode electrode in the plasma cell. Since the liquid crystal responds to the effective voltage value of the applied signal, the liquid crystal is affected by this crosstalk, and the effective voltage value actually applied to the liquid crystal is different from a desired value. Since the amount of crosstalk differs depending on the position in the vertical direction of the panel, brightness unevenness occurs. FIG. 15 shows how the crosstalk differs, corresponding to the timing chart image.
The liquid crystal signal 51 'to be applied is shown in FIG.
As shown in FIG. 15B, the voltage level 53 'held by the liquid crystal layer on the upper part of the panel is affected by the voltage ΔV after the passage of the liquid crystal writing voltage application period 55' at the time of selection. on the other hand,
As shown in FIG. 15 (c), the voltage level 54 'held by the liquid crystal layer at the bottom of the panel is affected by the voltage ΔV after the passage of the liquid crystal writing voltage application period 56' at the time of selection, and the liquid crystal layer at the top of the panel is When the voltage to be held is applied, it is affected by the reverse voltage ΔV. The voltage level in the non-selection period is shifted by ΔV with respect to the voltage level in the selection period because the liquid crystal signal in the non-selection period is written as crosstalk through the plasma layer. The effective voltage value applied to the liquid crystal can be expressed by the following equation. Vrms = 1 / T√ (∫V ² dt) The difference between the effective voltage values at the upper part and the lower part of the panel is shown in FIG.
It is clear from the comparison between the waveforms 53 'and 56' shown in (b) and (c). Since the execution voltage value applied to the liquid crystal layer differs depending on the location in the vertical direction of the panel, it occurs as uneven brightness.

[0008]

SUMMARY OF THE INVENTION The present invention solves the problems of the prior art, in which the number of necessary compensation circuits is reduced by compensating the write reference potential, and
An object of the present invention is to provide a plasma addressed liquid crystal display device capable of reducing uneven brightness.

[0009]

SUMMARY OF THE INVENTION The present invention provides a liquid crystal panel comprising a liquid crystal cell having a liquid crystal layer, a plasma cell having a cathode electrode and an anode electrode, and a thin dielectric layer provided between the cells. A driving unit for driving the panel unit,
Wherein the driving unit is configured to increase the amplitude of the anode drive signal with time within one vertical period.

The present invention also provides a liquid crystal panel comprising a liquid crystal cell having a liquid crystal layer, a plasma cell having a cathode electrode and an anode electrode, and a thin dielectric layer provided between the two cells, and driving the liquid crystal panel. And a driving unit that performs a multiple horizontal period inversion driving method, wherein the driving unit increases the amplitude of the anode driving signal with time within a period obtained by dividing one vertical period into a plurality. It is a plasma addressed liquid crystal display device having means.

The present invention comprises a liquid crystal cell having a liquid crystal layer, a plasma cell having a cathode electrode and an anode electrode, and a thin dielectric layer provided between both cells, wherein the anode electrode and the data signal electrode are parallel. LCD panel,
A driving unit for driving the liquid crystal panel unit, wherein the anode electrode is divided into two groups in a frame inversion driving type plasma addressed liquid crystal display device. ,
This is a plasma-addressed liquid crystal display device having means for increasing the polarity with the polarity reversed in different groups and with time.

Further, the present invention comprises a liquid crystal cell having a liquid crystal layer, a plasma cell having a cathode electrode and an anode electrode, and a thin dielectric layer provided between both cells, wherein the anode electrode and the data signal electrode are parallel. LCD panel,
A driving unit for driving the liquid crystal panel unit, wherein the anode electrode is divided into two groups, and the driving unit outputs an anode driving signal. about,
The polarity is reversed for the different groups and the amplitude is 1
A plasma addressed liquid crystal display device having means for increasing with time in a period obtained by dividing a vertical period into a plurality.

The present invention is also a plasma addressed liquid crystal display device, wherein the driving section has a voltage amplitude control circuit and a variable voltage generation circuit.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described. First, an outline of the present invention will be described. The reference potential for writing the liquid crystal signal is an anode signal. In the present invention, the amplitude of the anode signal is changed according to the position of the write selection line to compensate for the execution voltage value applied to the liquid crystal. Then, with the configuration in which the voltage amplitude control circuit and the variable voltage generation circuit are newly added, the amplitude of the anode signal can be changed depending on the position of the write selection line. According to the present invention, it is only necessary to provide a compensation circuit for only the anode signal serving as a writing reference for all pixels.

FIG. 1 shows an example of compensation by the amplitude of the anode signal in the present invention. The amplitude of the corrected anode signal 52 with respect to the liquid crystal signal 51 is increased with time, as shown in FIG. As a result, the voltage level held by the liquid crystal layer at the upper part of the panel becomes a signal waveform 53 as shown in FIG. 1B, and the voltage level held by the liquid crystal layer at the lower part of the panel becomes as shown in FIG. As shown,
A signal waveform 54 is obtained. Thus, by optimizing the amplitude change of the anode signal, it becomes possible to equalize the effective voltage values applied to the liquid crystal layers in the upper and lower parts of the panel, and to reduce the luminance difference between the upper and lower parts of the panel due to crosstalk. It can be suppressed.

Embodiment 1 will be described. The plasma addressed liquid crystal display (PALC) of the present embodiment includes a display unit and a drive unit 4 for driving the display unit, as in the conventional example. The display unit is, as shown in FIG.
1, color filter layer 12, signal electrode 13, liquid crystal layer 1
4, a liquid crystal cell 1 having a glass substrate 21, an anode electrode 22, a cathode electrode 23, a rib 24, a plasma discharge space 25, etc.
It is composed of a thin dielectric layer 31 provided therebetween. Then, it can be described that the virtual electrode 26 and the plasma switch 27 of the plasma cell 2 operate and display is performed as shown in FIG. 9 by the applied anode drive current.

The PALC of the first embodiment is a frame inversion drive system having means for increasing the amplitude of the anode drive signal with time within one vertical period. FIG. 2A is a block diagram showing the configuration of the anode signal drive circuit. FIG. 2B shows a timing chart of input / output signals of each block. The anode signal drive circuit includes a timing signal generation circuit 42a, a switching control circuit 43a, a voltage amplitude control circuit 44a, a variable voltage generation circuit 45a, and a switching circuit 46a. Timing signal generation circuit 42a
The switching control circuit 43a is operated by the input vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync).
And a reference control signal serving as an operation reference of the power supply voltage control circuit 44a. The switching control circuit 43a generates an alternate drive control signal for alternately turning on the two types of transistors of the switching circuit 46a. The voltage amplitude control circuit 44a generates an amplitude change control signal Dv for changing the voltage amplitude of the variable voltage generation circuit 45a. Since the amount of crosstalk generated during the non-selection period varies depending on panel characteristics, the slope of the amplitude change control signal Dv,
Adjustment of non-linearity is possible. Variable voltage generation circuit 45a
Are Vhigh and Vlow according to the amplitude change control signal Dv.
Occurs. Vhigh and Vlow are potentials that provide the high and low levels of the anode signal. The switching circuit 46a generates an anode signal by switching between Vhigh and Vlow from the variable voltage generation circuit 45a. This makes it possible to equalize the effective voltage values applied to the liquid crystal layers in the upper and lower portions of the panel, and to suppress the difference in luminance between the upper and lower portions of the panel due to crosstalk.

Embodiment 2 will be described. In the plasma addressed liquid crystal display device of the present embodiment, the amplitude of the anode drive signal is 1
This is a multiple horizontal period inversion driving method having means for increasing with time in a period obtained by dividing a vertical period into a plurality. P
FIG. 3A is a configuration block diagram of the anode signal drive circuit of the ALC. The basic configuration is the same as that of the first embodiment, but differs from the first embodiment in that an Hsync counter 41b is provided.
Is added. The Hsync counter 41b is a circuit for measuring a plurality of horizontal periods, and thus, a multi-horizontal period inversion driving method can be used. For example, when the polarity of the liquid crystal signal and the polarity of the anode signal are inverted every 13 horizontal periods, the correction control signal H is output every time 13H is measured.
syncb is output to the timing generation circuit 42b. H
Modified control signal H output from sync counter 41b
Each circuit is based on the syncb timing shown in FIG.
And the anode drive waveform shown in FIG. This makes it possible to equalize the execution voltage values applied to the liquid crystal layer within a period obtained by dividing the vertical period into a plurality of periods, and to suppress a luminance difference due to crosstalk.

Embodiment 3 will be described. The plasma addressed liquid crystal display of this embodiment has a configuration in which the anode electrode is parallel to the data signal electrode, and the anode electrode is divided into two groups. Then, the driving circuit according to the first embodiment
4 (see FIG. 2), as shown in FIG. 4, the switching circuit includes a circuit A 461c and a circuit B 462c.
It has two. This is a frame inversion driving method having means for reversing the polarity of the signal input to each of them and increasing the amplitude gradually with time.

A driving method according to the third embodiment will be described. Examples of the driving method of the liquid crystal panel include a method of inverting the polarity of the signal applied to the liquid crystal layer at fixed time intervals (the above-described frame inversion drive and 1H inversion drive) and a method of inverting the polarity for each space. In, the polarities of the output signals of the liquid crystal signal drive circuit are all the same when focusing on a certain time. In the third embodiment, for example, as shown in FIG. 5, the driving circuits are arranged so that the output polarity of the liquid crystal signal driving circuit spatially alternates between positive and negative. In this case, it is not limited to the positive / negative alternation, but may be repeated, for example, positive / negative / negative. The liquid crystal signal is AC-driven to prevent the liquid crystal from deteriorating. In principle, in Embodiment 3, the anode electrode is orthogonal to the cathode electrode. Also, the anode electrode must be electrically separated into two groups. The grouping of the anode electrodes is performed by the anode electrodes corresponding to the picture elements in which the liquid crystal signals are written with the same polarity at a certain time.

FIG. 4 is a block diagram showing the configuration of the anode signal drive circuit according to the third embodiment, and FIG. 6 is a timing chart of input / output signals of each block. The timing signal generation circuit 42c outputs the vertical synchronizing signal (Vsyn
c) and a horizontal synchronizing signal (Hsync) to generate a control signal serving as an operation reference of the switching control circuit 43c and the voltage amplitude control circuit 44c. Switching control circuit 43c
Generates a control signal for alternately turning on the two types of transistors shown in the switching circuits 461c and 462c. The voltage amplitude control circuit 44c has a control signal Dv for changing the voltage amplitude of the variable voltage generation circuit 45c.
Occurs. Since the amount of crosstalk occurring during the non-selection period varies depending on the panel characteristics, the slope of Dv and the nonlinearity can be adjusted. The variable voltage generation circuit 45c uses the control signal of the voltage amplitude control circuit 44c to control Vhigh and Vl.
ow is generated. Vhigh and Vlow are potentials for providing high and low levels of the anode signal. The switching circuits 461c and 462c generate an anode signal by alternately switching between Vhigh and Vlow output from the variable voltage generation circuit 45c according to a switching control signal from the switching control circuit 43c. When the output of the switching circuit 461c is Vhigh, the output of the switching circuit 462c is Vlow, and when the output of the switching circuit 461c is Vlow, the output of the switching circuit 462c is Vhigh. This makes it possible to equalize the effective voltage values applied to the liquid crystal layers in the upper and lower portions of the panel, and to suppress the difference in luminance between the upper and lower portions of the panel due to crosstalk.

Embodiment 4 will be described. The plasma addressed liquid crystal display device of this embodiment has a configuration in which the anode electrode is parallel to the data signal electrode, the anode electrode is divided into two groups, and the polarity of the amplitude of the signal input to each of the two groups is different. On the contrary, this is a driving method of a plurality of horizontal period inversions having means for increasing the amplitude of each signal with time in a period obtained by dividing the vertical period into a plurality. FIG. 7 is a block diagram showing a configuration of the anode signal drive circuit of the PALC, and FIG. 8 is a timing chart of input / output signals of each block. The basic configuration is the same as that of the third embodiment. The difference from the third embodiment is that an Hsync counter 41d is added. Since it is a multiple horizontal period inversion drive method, it has a circuit for measuring multiple horizontal periods. For example, when the polarity of the liquid crystal signal and the polarity of the anode signal are inverted every 13 horizontal periods, the control signal Hsyncd is output to the 42d timing generation circuit every time 13H is measured. Each circuit outputs a control signal and an anode drive waveform based on the timing of the control signal output from the Hsync counter 41d. This allows
The execution voltage value applied to the liquid crystal layer can be equalized within a period obtained by dividing the vertical period into a plurality of periods, and a luminance difference due to crosstalk can be suppressed.

[0023]

According to the present invention, it is possible to obtain a plasma addressed liquid crystal display device capable of reducing the number of necessary correction circuits and reducing luminance unevenness by adjusting the write reference potential.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an example of compensation by the amplitude of an anode signal in the present invention.

FIG. 2 is a configuration block diagram of an anode signal driving circuit and an explanatory diagram of a timing chart of input / output signals of each block according to the first embodiment.

FIG. 3 is a configuration block diagram of an anode signal drive circuit and a timing chart of input / output signals of each block according to a second embodiment.

FIG. 4 is an explanatory diagram of a configuration block of an anode signal drive circuit according to a third embodiment.

FIG. 5 is a diagram illustrating an output polarity of a liquid crystal signal drive circuit according to a fifth embodiment.

FIG. 6 is an explanatory diagram of a timing chart of input / output signals of each block according to the third embodiment.

FIG. 7 is an explanatory diagram of a configuration block of an anode signal drive circuit according to a fourth embodiment.

FIG. 8 is an explanatory diagram of a timing chart of input / output signals of each block according to the fourth embodiment.

FIG. 9 is an explanatory sectional view of a plasma addressed liquid crystal display (PALC).

FIG. 10 is an operation explanatory view of a plasma addressed liquid crystal display device.

FIG. 11 is an explanatory diagram of a configuration block of an anode signal drive circuit in a conventional example.

FIG. 12 is an explanatory diagram of the output polarity of a liquid crystal signal drive circuit in Conventional Example 1.

FIG. 13 is an explanatory diagram of the output polarity of a liquid crystal signal drive circuit in Conventional Example 2.

FIG. 14 is an explanatory diagram of an equivalent circuit per pixel of PALC.

FIG. 15 is an explanatory diagram of a timing chart in a conventional example.

[Explanation of symbols]

Reference Signs List 1 liquid crystal cell 11 glass substrate 12 color filter layer 13 signal electrode 14 liquid crystal layer 19 liquid crystal capacitance 2 plasma cell 21 glass substrate 22 anode 23 cathode 24 rib 25 plasma discharge space 26 virtual electrode 27 plasma switch 29 plasma cell capacitance 31 microsheet 39 micro Sheet capacity 4 Drive circuit 41b, 41d Hsync counter 42a-42d Timing generation circuit 43a-43d Switching control circuit 44a-44 Voltage amplitude control circuit 45a-45 Variable voltage generation circuit 46a, 46b, 461c, 461d, 462c, 46
2d switching circuit 49 liquid crystal applied voltage 51 liquid crystal signal 52 adjusted anode signal 53 upper liquid crystal layer holding voltage level 54 lower liquid crystal layer holding voltage level

Continued on front page F-term (reference) 2H089 HA36 QA13 TA02 TA07 2H093 NA20 NA33 NA43 NC33 ND09 ND49 NG20 NH15 5C006 AA16 AC22 AC28 AF44 AF50 BB18 BC22 BF33 BF42 FA22 5C080 AA05 AA10 BB05 CC03 DD05 EE29 JJ03 JJ09 JJ09 JJ03 JJ29 JJ03

Claims (5)

[Claims] 1. A liquid crystal panel comprising a liquid crystal cell having a liquid crystal layer, a plasma cell having a cathode electrode and an anode electrode, and a thin dielectric layer provided between the two cells; and a driving unit for driving the liquid crystal panel. A plasma addressed liquid crystal display device of a frame inversion drive method, comprising: means for increasing the amplitude of an anode drive signal with time within one vertical period. . 2. A liquid crystal panel comprising a liquid crystal cell having a liquid crystal layer, a plasma cell having a cathode electrode and an anode electrode, and a thin dielectric layer provided between the cells, and a driving unit for driving the liquid crystal panel. Wherein the driving unit has means for increasing the amplitude of the anode driving signal with time within a period obtained by dividing one vertical period into a plurality of periods. A plasma addressed liquid crystal display device characterized by the above-mentioned. 3. A liquid crystal panel comprising a liquid crystal cell having a liquid crystal layer, a plasma cell having a cathode electrode and an anode electrode, and a thin dielectric layer provided between both cells, wherein the anode electrode and the data signal electrode are parallel to each other. And a driving unit for driving the liquid crystal panel unit, wherein the anode electrode is divided into two groups, wherein the anode electrode is divided into two groups.
The driving unit has means for increasing the polarity of the anode drive signal in the opposite group in different groups and increasing the amplitude with time. 4. A liquid crystal panel comprising a liquid crystal cell having a liquid crystal layer, a plasma cell having a cathode electrode and an anode electrode, and a thin dielectric layer provided between both cells, wherein the anode electrode and the data signal electrode are parallel to each other. A driving unit for driving the liquid crystal panel unit, wherein the anode electrode is divided into two groups, and the driving unit comprises an anode driving unit. A plasma addressed liquid crystal display device comprising: means for increasing the polarity of a signal with time in a group in which the polarity is different in a different group, and increasing the amplitude with time in a period obtained by dividing one vertical period into a plurality. 5. The plasma addressed liquid crystal display device according to claim 1, wherein said driving section has a voltage amplitude control circuit and a variable voltage generation circuit.