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JP2001244299A - Wiring board and method of manufacturing the same - Google Patents

Wiring board and method of manufacturing the same

Info

Publication number
JP2001244299A
JP2001244299A JP2000053907A JP2000053907A JP2001244299A JP 2001244299 A JP2001244299 A JP 2001244299A JP 2000053907 A JP2000053907 A JP 2000053907A JP 2000053907 A JP2000053907 A JP 2000053907A JP 2001244299 A JP2001244299 A JP 2001244299A
Authority
JP
Japan
Prior art keywords
substrate
chip
resin
semiconductor element
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000053907A
Other languages
Japanese (ja)
Inventor
Nobuhiro Hanai
信洋 花井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2000053907A priority Critical patent/JP2001244299A/en
Publication of JP2001244299A publication Critical patent/JP2001244299A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which can prevent deviation in position of a chip before soldering is completed by keeping force for holding a mounted chip while maintaining a gap necessary between the chip and the substrate, and also provide a method of manufacturing the same. SOLUTION: A fine solder paste is screen-printed on lands 12 of a substrate 11. The screen-printed substrate 11 is reflowed and heated to supply solder 14 onto the lands 12. After printing a thermosetting epoxy resin paste in a part of the substrate 11 inside the lands 12, a heat treatment is performed to form resin columns 15. On this substrate 11, a bare chip 17 having solder bumps 18 is mounted. Thereafter, the substrate 11 mounted with the bare chip 17 is reflowed and heated to solder the bare chip 17 on the lands 12 and mount the bare chip 17 on the substrate 11. Then, underfill resin 20 is supplied between the bare chip 17 and the substrate 11 and then a heat treatment is performed to cure the resin 20.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、表面実装プロセス
において使用される配線基板及びその製造方法に関す
る。
[0001] 1. Field of the Invention [0002] The present invention relates to a wiring board used in a surface mounting process and a method of manufacturing the same.

【0002】[0002]

【従来の技術】共晶半田バンプを用いたフィリップチッ
プ実装としては、リフロー半田付け方法や、加熱ヘッド
でマウントしながらチップと基板間のギャップを調整す
る方法がある。加熱ヘッドを用いた方法では、加熱ヘッ
ドでマウントだけでなく、加熱半田付けから冷却までを
行うために、マシンタクトがリフロー半田付け方法に比
べて格段に長くなる。また、加熱ヘッドを用いた方法で
は、必要とする設備台数が多く、設備コストが非常に高
くなる。
2. Description of the Related Art As a flip chip mounting method using eutectic solder bumps, there are a reflow soldering method and a method of adjusting a gap between a chip and a substrate while mounting with a heating head. In the method using the heating head, since the heating head performs not only mounting but also heating soldering to cooling, the machine tact becomes much longer than the reflow soldering method. Further, in the method using the heating head, the number of required equipment is large, and the equipment cost is extremely high.

【0003】したがって、フィリップチップ実装には、
リフロー半田付け方法を採用することが望ましい。しか
しながら、このリフロー半田付け方法を用いてフィリッ
プチップ実装を行う場合、高融点半田バンプを用いると
まったく問題なく実装を行うことができるが、共晶半田
バンプを用いると以下のような問題を生じる。
[0003] Therefore, for the flip chip mounting,
It is desirable to adopt a reflow soldering method. However, in the case of performing the flip chip mounting using this reflow soldering method, the mounting can be performed without any problem by using the high melting point solder bump. However, the use of the eutectic solder bump causes the following problems.

【0004】[0004]

【発明が解決しようとする課題】すなわち、例えば、図
5に示すように、基板21に形成されたランド22上に
半田バンプ23を介してチップ24を実装する場合にお
いては、半田付けのための加熱により半田バンプ23が
溶融し、チップ24の自重により潰れてしまい、チップ
24と基板21との間のギャップが減少する(20〜3
5μm)。
That is, for example, as shown in FIG. 5, when a chip 24 is mounted on a land 22 formed on a substrate 21 via a solder bump 23, a soldering process is required. The solder bumps 23 are melted by the heating, are crushed by the weight of the chip 24, and the gap between the chip 24 and the substrate 21 is reduced (20-3).
5 μm).

【0005】これにより、基板21とチップ24との間
に供給するアンダーフィル樹脂が注入できなくなる。半
田付けの際に使用するフラックスの粘度の選定によって
は、さらにこの現象が顕著になって、半田バンプ23間
でブリッジが発生することもある。
As a result, the underfill resin supplied between the substrate 21 and the chip 24 cannot be injected. Depending on the selection of the viscosity of the flux used at the time of soldering, this phenomenon becomes more remarkable, and a bridge may occur between the solder bumps 23.

【0006】フラックスの粘度を低くすれば、この傾向
を回避することができるが、逆に粘度が低いと、実装し
たチップ24を保持する力が弱くなり、半田付けが完了
する前にチップ24が位置ずれを起こしてしまうという
問題がある。
[0006] If the viscosity of the flux is reduced, this tendency can be avoided. However, if the viscosity is low, the holding force of the mounted chip 24 becomes weaker, and the chip 24 becomes weaker before the soldering is completed. There is a problem that a position shift occurs.

【0007】本発明はかかる点に鑑みてなされたもので
あり、チップと基板との間に必要とされるギャップを維
持し、しかも実装したチップを保持する力を保って、半
田付けが完了する前のチップの位置ずれを防止すること
ができる配線基板及びその製造方法を提供することを目
的とする。
The present invention has been made in view of the above circumstances, and maintains a required gap between a chip and a substrate, and also maintains a force for holding a mounted chip, thereby completing soldering. An object of the present invention is to provide a wiring board and a method for manufacturing the wiring board, which can prevent the displacement of the previous chip.

【0008】[0008]

【課題を解決するための手段】本発明は、素子実装用ラ
ンドが形成された基板本体と、前記素子実装用ランド上
に実装された半導体素子と、前記基板本体と前記半導体
素子との間に設けられ、前記基板本体と前記半導体素子
との間の所定のギャップを保持する柱状部材と、前記基
板本体と前記半導体素子との間に充填された樹脂部材
と、を具備することを特徴とする配線基板を提供する。
According to the present invention, there is provided a substrate body having element mounting lands formed thereon, a semiconductor element mounted on the element mounting lands, and a semiconductor device mounted between the substrate body and the semiconductor element. A columnar member provided to maintain a predetermined gap between the substrate main body and the semiconductor element; and a resin member filled between the substrate main body and the semiconductor element. Provide a wiring board.

【0009】この構成によれば、柱状部材が半導体素子
を支持するので、半導体素子の重量を基板と半導体素子
の接合部分に集中させないようにすることができる。こ
れにより、基板と半導体素子の接合部分の接合部材が潰
れることがなく、半導体素子と基板との間に必要とされ
るギャップを維持することができる。また、実装した半
導体素子を保持する力を保って、半田付けが完了する前
の半導体素子の位置ずれを防止することができる。
According to this configuration, since the columnar member supports the semiconductor element, it is possible to prevent the weight of the semiconductor element from being concentrated on the joint between the substrate and the semiconductor element. Thereby, the bonding member at the bonding portion between the substrate and the semiconductor element is not crushed, and the required gap between the semiconductor element and the substrate can be maintained. In addition, it is possible to maintain the force for holding the mounted semiconductor element and prevent the semiconductor element from being displaced before soldering is completed.

【0010】本発明の配線基板においては、前記柱状部
材は、前記樹脂部材と同種の樹脂で構成されていること
が好ましい。この構成によれば、樹脂部材と柱状部材と
の間の相性が良くなり、十分な信頼性を確保することが
できる。
In the wiring board according to the present invention, it is preferable that the columnar member is made of the same kind of resin as the resin member. According to this configuration, compatibility between the resin member and the columnar member is improved, and sufficient reliability can be secured.

【0011】本発明は、素子実装用ランドを有する基板
本体の前記素子実装用ランド以外の部分に柱状部材を形
成する工程と、前記柱状部材に支持させる状態で、半導
体素子を前記素子実装用ランド上に実装する工程と、前
記基板本体と前記半導体素子との間に樹脂部材を充填す
る工程と、を有することを特徴とする配線基板の製造方
法を提供する。
According to the present invention, there is provided a step of forming a columnar member on a portion other than the element mounting land of the substrate body having the element mounting land, and the step of mounting the semiconductor element on the element mounting land while supporting the columnar member. A method for manufacturing a wiring board, comprising: a step of mounting on a substrate; and a step of filling a resin member between the substrate body and the semiconductor element.

【0012】この方法によれば、半導体素子と基板との
間に必要とされるギャップを維持し、しかも実装した半
導体素子を保持する力を保って、半田付けが完了する前
の半導体素子の位置ずれを防止できる配線基板を得るこ
とができる。
According to this method, the gap required between the semiconductor element and the substrate is maintained, and the force for holding the mounted semiconductor element is maintained, so that the position of the semiconductor element before soldering is completed. A wiring board that can prevent displacement can be obtained.

【0013】[0013]

【発明の実施の形態】以下、本発明の実施の形態につい
て、添付図面を参照して詳細に説明する。図1(a)〜
(c)及び図2(a)〜(c)は、本発明の一実施の形
態に係る配線基板の製造方法を説明するための断面図で
ある。
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 (a)-
2C and 2A to 2C are cross-sectional views illustrating a method for manufacturing a wiring board according to an embodiment of the present invention.

【0014】本実施の形態では、直径80μm、高さ7
0μmの共晶半田(融点183℃)バンプをアルミパッ
ド上に有するチップサイズ8mm角×0.3mm厚みの
100ピンのベアIC(半導体素子)をフィリップチッ
プ実装する場合について説明する。
In this embodiment, the diameter is 80 μm and the height is 7
A case will be described in which a 100-pin bare IC (semiconductor element) having a chip size of 8 mm × 0.3 mm and having a 0 μm eutectic solder (melting point: 183 ° C.) bump on an aluminum pad is mounted on a flip chip.

【0015】図1(a)に示すように、基板11上に形
成されたランド12上に微粒子半田ペーストをスクリー
ン印刷し、印刷後の基板11をリフロー加熱してランド
12上に半田プリコートを行って半田14を供給した。
なお、基板11上において、ランド12以外の部分に
は、レジスト13が形成されている。
As shown in FIG. 1A, a fine particle solder paste is screen-printed on a land 12 formed on the substrate 11, and the printed substrate 11 is reflow-heated to perform solder pre-coating on the land 12. Solder 14 was supplied.
A resist 13 is formed on a portion other than the land 12 on the substrate 11.

【0016】次いで、図1(b)に示すように、ランド
12の内側に熱硬化型エポキシ樹脂ペーストを印刷し
た。このとき使用したメタルスクリーンは、厚さ40μ
mでφ1mmの開口部を2mmピッチで4箇所有するも
のであった。なお、印刷パターンは、ベアチップを安定
して支えることができる広がりを有し、かつ印刷がずれ
てもランド12に絶対にかからないように設定する。
Next, as shown in FIG. 1B, a thermosetting epoxy resin paste was printed inside the land 12. The metal screen used at this time has a thickness of 40μ.
It had four openings of 1 mm in diameter and 2 mm pitch. The print pattern is set so as to have a spread capable of stably supporting the bare chip, and not to touch the land 12 even if the printing is shifted.

【0017】そして、印刷した後に、基板11に対して
100℃で10分間の熱処理を施してエポキシ樹脂ペー
ストを硬化させて樹脂柱15を形成した。この樹脂柱1
5の高さは、レジスト13の表面から40±5μmであ
った。このようにして、図3に示すように、ベアチップ
を実装するランド12の内側に4つの樹脂柱15を設け
た。
After printing, the substrate 11 was subjected to a heat treatment at 100 ° C. for 10 minutes to harden the epoxy resin paste to form the resin pillar 15. This resin pillar 1
The height of No. 5 was 40 ± 5 μm from the surface of the resist 13. In this manner, as shown in FIG. 3, four resin pillars 15 were provided inside the land 12 on which the bare chip was mounted.

【0018】この樹脂柱15の高さは、搭載するベアチ
ップから基板11までの間のギャップ以下に設定するこ
とが好ましく、具体的には、ベアチップのバンプの高さ
を最大とする。また、樹脂柱15の形状は、ベアチップ
のチップサイズによるが、ベアチップのアクティブ面に
対面する領域にベアチップが傾かずに安定するような形
とすることが望ましい。また、樹脂柱15のサイズは、
後述するアンダーフィル樹脂の信頼性を低下させないよ
うに、ベアチップを支持するために必要最小限に設定す
ることが望ましい。
The height of the resin pillar 15 is preferably set to be equal to or less than the gap between the bare chip to be mounted and the substrate 11, and specifically, the height of the bump of the bare chip is maximized. Although the shape of the resin pillar 15 depends on the chip size of the bare chip, it is preferable that the resin pillar 15 be shaped such that the bare chip is not tilted to a region facing the active surface of the bare chip and is stable. The size of the resin pillar 15 is
In order not to lower the reliability of the underfill resin described later, it is desirable to set the minimum necessary for supporting the bare chip.

【0019】次いで、図1(c)に示すように、乳剤厚
30μmのメッシュスクリーンを用いて、ランド12を
完全に覆うように粘度50Pa・sのフラックス16を
オフコンタクト印刷した。印刷後のフラックス16の高
さは25±5μmであった。
Next, as shown in FIG. 1C, a flux 16 having a viscosity of 50 Pa · s was printed off-contact using a mesh screen having an emulsion thickness of 30 μm so as to completely cover the lands 12. The height of the flux 16 after printing was 25 ± 5 μm.

【0020】次いで、図2(a)に示すように、この基
板11上に、上述した半田バンプ18を有するベアチッ
プ17を半田バンプ18がランド12と接触するように
位置合わせした状態で搭載した。その後、図2(b)に
示すように、ベアチップ17を搭載した基板11をリフ
ロー加熱して、ベアチップ17をランド12に半田付け
してベアチップ17を基板11に実装した。このとき、
樹脂柱15は、ベアチップ17を支持して半田19部分
が潰れることを防止する。
Next, as shown in FIG. 2A, a bare chip 17 having the above-mentioned solder bumps 18 was mounted on the substrate 11 in such a manner that the solder bumps 18 were aligned with the lands 12. Thereafter, as shown in FIG. 2B, the substrate 11 on which the bare chip 17 was mounted was subjected to reflow heating, the bare chip 17 was soldered to the land 12, and the bare chip 17 was mounted on the substrate 11. At this time,
The resin pillar 15 supports the bare chip 17 and prevents the solder 19 from being crushed.

【0021】次いで、半田接合部分のフラックスを洗浄
により除去した後に乾燥した。その後、図2(c)に示
すように、アンダーフィル樹脂20として粘度15Pa
・sのエポキシ樹脂ペーストをベアチップ17と基板1
1との間に充填し、150℃×4時間の熱処理を行っ
て、エポキシ樹脂を硬化させた。
Next, the flux at the solder joint was removed by washing and then dried. After that, as shown in FIG.
S epoxy resin paste to bare chip 17 and substrate 1
1 and heat-treated at 150 ° C. for 4 hours to cure the epoxy resin.

【0022】このようにベアチップ17を実装した基板
11について、実装後のオープン・ショートチェックを
行ったところ、このような樹脂印刷を行わなかった従来
の配線基板の場合に5〜20%も発生していた半田ブリ
ッジがまったく発生していないことが確認された。さら
に、半田接合部分の断面を観察したところ、図4に示す
ようになり、ベアチップ17と基板11との間のギャッ
プが50〜60μmと適正値になり、しかもアンダーフ
ィル樹脂20のボイドも見られなかった。
When the open / short check is performed on the board 11 on which the bare chip 17 is mounted as described above, the conventional wiring board without such resin printing produces as much as 5 to 20%. It was confirmed that no solder bridge had occurred. Further, when the cross section of the solder joint portion was observed, it became as shown in FIG. 4, the gap between the bare chip 17 and the substrate 11 became an appropriate value of 50 to 60 μm, and voids of the underfill resin 20 were also observed. Did not.

【0023】このように本発明の配線基板では、予め基
板側にチップを支持する柱を設けたため、リフロー温度
によりバンプが溶融しても潰れることなくギャップを確
保することができ、半田ブリッジやアンダーフィル樹脂
の未充填といったトラブルの発生を回避することができ
る。
As described above, in the wiring board according to the present invention, since the pillar for supporting the chip is provided on the board side in advance, even if the bump is melted by the reflow temperature, the gap can be secured without being crushed, and the solder bridge and the underside can be secured. It is possible to avoid occurrence of troubles such as unfilling of the fill resin.

【0024】また、樹脂ペーストの印刷はメッシュスク
リーンではなく、メタルスクリーンで行ったため、印刷
後に髭状の突起の発生も無く、ベアチップのアクティブ
面を傷つけることもなかった。さらに、樹脂柱には、ア
ンダーフィル樹脂と同種のエポキシ樹脂を用いたため、
−25℃〜125℃のヒートサイクル試験においても2
000サイクルまで不良の発生はなく、十分な信頼性が
確保できた。
In addition, since the printing of the resin paste was performed using a metal screen instead of a mesh screen, no beard-like projections were generated after printing, and the active surface of the bare chip was not damaged. Furthermore, since the same type of epoxy resin as the underfill resin was used for the resin pillar,
Even in the heat cycle test at -25 ° C to 125 ° C, 2
No defects occurred up to 000 cycles, and sufficient reliability was secured.

【0025】本発明は上記実施の形態に限定されず種々
変更して実施することが可能である。例えば、各部材の
材質、寸法などについては上記実施の形態に限定されず
種々変更することができる。
The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example, the material, dimensions, and the like of each member are not limited to the above embodiment, and can be variously changed.

【0026】[0026]

【発明の効果】以上説明したように本発明の配線基板
は、基板本体の素子実装用ランド上に実装された半導体
素子と基板本体との間に、基板本体と半導体素子との間
の所定のギャップを保持する柱状部材を設けているの
で、半導体素子と基板との間に必要とされるギャップを
維持し、しかも実装した半導体素子を保持する力を保っ
て、半田付けが完了する前の半導体素子の位置ずれを防
止することができる。
As described above, the wiring board of the present invention is provided between the semiconductor element mounted on the element mounting land of the substrate main body and the substrate main body, with a predetermined distance between the substrate main body and the semiconductor element. Since the columnar member that holds the gap is provided, the gap required between the semiconductor element and the substrate is maintained, and the force that holds the mounted semiconductor element is maintained. The displacement of the element can be prevented.

【0027】また、本発明の配線基板の製造方法は、素
子実装用ランド以外の部分に柱状部材を形成し、柱状部
材に支持させる状態で、半導体素子を素子実装用ランド
上に実装し、その後基板本体と半導体素子との間に樹脂
部材を充填するので、半導体素子と基板との間に必要と
されるギャップを維持し、しかも実装した半導体素子を
保持する力を保って、半田付けが完了する前の半導体素
子の位置ずれを防止できる配線基板を得ることができ
る。
Further, according to the method of manufacturing a wiring board of the present invention, a columnar member is formed in a portion other than the element mounting land, and the semiconductor element is mounted on the element mounting land while being supported by the columnar member. Since the resin material is filled between the board body and the semiconductor element, the necessary gap between the semiconductor element and the board is maintained, and the soldering is completed while maintaining the holding force of the mounted semiconductor element. Thus, it is possible to obtain a wiring board that can prevent the semiconductor element from being displaced before the wiring.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(c)は、本発明の一実施の形態に係
る配線基板の製造方法の前半の工程を説明するための断
面図である。
FIGS. 1A to 1C are cross-sectional views illustrating a first half of a method of manufacturing a wiring board according to an embodiment of the present invention;

【図2】(a)〜(c)は、本発明の一実施の形態に係
る配線基板の製造方法の後半の工程を説明するための断
面図である。
FIGS. 2A to 2C are cross-sectional views illustrating the latter half of a method for manufacturing a wiring board according to an embodiment of the present invention;

【図3】本発明の配線基板において、樹脂柱を形成した
状態を示す図である。
FIG. 3 is a view showing a state in which resin columns are formed on the wiring board of the present invention.

【図4】本発明の配線基板の半田接合部分を示す図であ
る。
FIG. 4 is a view showing a solder joint portion of the wiring board of the present invention.

【図5】従来の配線基板の半田接合部分を示す図であ
る。
FIG. 5 is a view showing a solder joint portion of a conventional wiring board.

【符号の説明】[Explanation of symbols]

11…基板、12…ランド、13…レジスト、14,1
9…半田、15…樹脂柱、16…フラックス、17…ベ
アチップ、18…半田バンプ、20…アンダーフィル樹
脂。
11: substrate, 12: land, 13: resist, 14, 1
9 solder, 15 resin pillar, 16 flux, 17 bare chip, 18 solder bump, 20 underfill resin.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】素子実装用ランドが形成された基板本体
と、 前記素子実装用ランド上に実装された半導体素子と、 前記基板本体と前記半導体素子との間に設けられ、前記
基板本体と前記半導体素子との間の所定のギャップを保
持する柱状部材と、 前記基板本体と前記半導体素子との間に充填された樹脂
部材と、を具備することを特徴とする配線基板。
A substrate body on which an element mounting land is formed; a semiconductor element mounted on the element mounting land; and a semiconductor element provided between the substrate body and the semiconductor element; A wiring board, comprising: a columnar member for maintaining a predetermined gap between the semiconductor element and a resin member filled between the substrate body and the semiconductor element.
【請求項2】 前記柱状部材は、前記樹脂部材と同種の
樹脂で構成されていることを特徴とする請求項1記載の
配線基板。
2. The wiring board according to claim 1, wherein the columnar member is made of the same kind of resin as the resin member.
【請求項3】素子実装用ランドを有する基板本体の前記
素子実装用ランド以外の部分に柱状部材を形成する工程
と、 前記柱状部材に支持させる状態で、半導体素子を前記素
子実装用ランド上に実装する工程と、 前記基板本体と前記半導体素子との間に樹脂部材を充填
する工程と、を有することを特徴とする配線基板の製造
方法。
3. A step of forming a columnar member on a portion other than the element mounting land of a substrate body having an element mounting land, and a step of mounting a semiconductor element on the element mounting land while supporting the columnar member. A method for manufacturing a wiring board, comprising: a step of mounting; and a step of filling a resin member between the substrate body and the semiconductor element.
JP2000053907A 2000-02-29 2000-02-29 Wiring board and method of manufacturing the same Pending JP2001244299A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000053907A JP2001244299A (en) 2000-02-29 2000-02-29 Wiring board and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000053907A JP2001244299A (en) 2000-02-29 2000-02-29 Wiring board and method of manufacturing the same

Publications (1)

Publication Number Publication Date
JP2001244299A true JP2001244299A (en) 2001-09-07

Family

ID=18575234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000053907A Pending JP2001244299A (en) 2000-02-29 2000-02-29 Wiring board and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2001244299A (en)

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JP2007335653A (en) * 2006-06-15 2007-12-27 Alps Electric Co Ltd Circuit board, method of manufacturing the same, and circuit module using the same
JP2009110992A (en) * 2007-10-26 2009-05-21 Panasonic Corp Part built-in printed wiring board, and manufacturing method of part built-in printed wiring board
US8252195B2 (en) 2005-08-19 2012-08-28 Houghton Technical Corp. Methods and compositions for acid treatment of a metal surface
JP2012174484A (en) * 2011-02-22 2012-09-10 Olympus Corp Cable connection structure and cable connection method
WO2016022375A1 (en) * 2014-08-06 2016-02-11 Invensas Corporation Device and method for localized underfill
WO2022113186A1 (en) * 2020-11-25 2022-06-02 株式会社Fuji Electric circuit forming method
CN117912963A (en) * 2024-03-13 2024-04-19 荣耀终端有限公司 Ball planting tool, ball planting equipment and ball planting method

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8252195B2 (en) 2005-08-19 2012-08-28 Houghton Technical Corp. Methods and compositions for acid treatment of a metal surface
US8518286B2 (en) 2005-08-19 2013-08-27 Houghton Technical Corp. Methods and compositons for acid treatment of a metal surface
US9732428B2 (en) 2005-08-19 2017-08-15 Houghton Technical Corp. Methods and compositions for acid treatment of a metal surface
US10260153B2 (en) 2005-08-19 2019-04-16 Houghton Technical Corp. Methods and compositions for acid treatment of a metal surface
JP2007335653A (en) * 2006-06-15 2007-12-27 Alps Electric Co Ltd Circuit board, method of manufacturing the same, and circuit module using the same
JP2009110992A (en) * 2007-10-26 2009-05-21 Panasonic Corp Part built-in printed wiring board, and manufacturing method of part built-in printed wiring board
JP2012174484A (en) * 2011-02-22 2012-09-10 Olympus Corp Cable connection structure and cable connection method
WO2016022375A1 (en) * 2014-08-06 2016-02-11 Invensas Corporation Device and method for localized underfill
US9349614B2 (en) 2014-08-06 2016-05-24 Invensas Corporation Device and method for localized underfill
US9673124B2 (en) 2014-08-06 2017-06-06 Invensas Corporation Device and method for localized underfill
WO2022113186A1 (en) * 2020-11-25 2022-06-02 株式会社Fuji Electric circuit forming method
CN117912963A (en) * 2024-03-13 2024-04-19 荣耀终端有限公司 Ball planting tool, ball planting equipment and ball planting method

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