JP2001135744A - Method of manufacturing ic package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the possibility of missing external terminals and wirings in the resin etching process by forming the wiring of IC package, without having to use solder masks. SOLUTION: In this method, wiring and solder pad are formed without using solder masks, namely after a wiring pattern forming resist is formed, a buffer metal layer or wiring by electrolytic plating is formed in direct, moreover, a buffer metal layer by the electrolytic plating method, or wiring by electrolytic plating, further a buffer metal layer by the electrolytic plating and solder layer by the electrolytic plating are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an I / O
The present invention relates to a method for manufacturing single-layer and multi-layer circuit boards for mounting C packages, MCMs, and electronic components.

[0002]

2. Description of the Related Art A built-up multilayer board using a printed wiring board as a core board, a resin material as an interlayer insulating material, and using Cu plating for wiring formation is a high-density IC package for MPU mounting, MCM, and high-density mounting for electronic components. Attention has been paid to mounting boards, and printed board manufacturers, IC package manufacturers, semiconductor manufacturers, and the like have been vigorously developing them. The manufacturing method is roughly classified into a photolithography method in which a wiring is formed by plating using a photosensitive resin for an insulating layer, and a press lamination method in which a prepreg resin and a metal foil are laminated by hot pressing. Furthermore, the photolithography method is classified into a subtractive method, a semi-additive method, and a full-additive method from the difference in a wiring forming method. As a typical example of the subtractive method, SLC of IBM is well known, and as a typical example of the full additive method, IBSS of Ibiden is well known. In recent years, attention has been paid to a semi-additive method which is advantageous for fine wiring. The manufacturing process of the built-up multilayer substrate by the semi-additive method is described below with reference to the drawings.

(1) A wiring pattern 2 is formed on a copper foil surface of a core substrate (PWB) 1. (FIG. 5) (2) An interlayer insulating layer 3 is formed by applying a photosensitive resin.
(FIG. 6) (3) Via holes 4 are formed in the insulating layer by ultraviolet exposure and development. (FIG. 6) (4) The surface of the insulating layer is roughened with an oxidizing agent (desmear).

(5) Electroless Cu (~ 2μ)
m) Precipitate 5. (Fig. 7) (6) Electroless C by coating, exposing and developing photosensitive resin
Pattern resist 6 is formed on u5. (FIG. 8) (7) Electrolytic Cu plating 7 is deposited to increase the thickness of Cu in the wiring portion (Cu thickness: 10 to 30 μm).

(8) Pattern resist peeling. (FIG. 10) (9) Electroless Cu between wirings is removed by etching. Since Cu in the wiring portion is thick, only the wiring portion remains. (FIG. 11) (10) The surface of the Cu wiring is roughened by plating or etching.

(11) Steps (2) to (10) are repeated to form a desired built-up layer. (12) A solder resist is applied to the outermost wiring surface, exposed and developed to form a solder mask layer 8. (Figure 1
1) (13) Electroless Ni, Au plating 9 is performed. (Figure 1
1) (14) The solder ball 10 is formed on the electroless Ni / Au plating 9. (FIG. 12) Through the above steps, a build-up multilayer substrate is obtained. Currently L / S = 40 / 40-100 / 100 μm, via diameter =
The total number of laminations is 4 ~ with the design rule of about 50 ~ 100μm
An eight-layer build-up substrate has been manufactured.

[0007]

It is expected that the pitch of the terminal portions on the outermost layer will decrease in the future as the wiring in the IC package substrate becomes finer. In the case of flip-chip mounting, since the diameter of the external terminal is required to be about 120 μm from the reliability of the m-junction, a smaller pitch means a smaller space for the external terminal. It is expected that the space will be reduced to 50 μm or less in the future, and it is becoming difficult to form a solder mask layer from the resolution of the solder resist.

Therefore, a method of not forming a solder mask between external terminals has been considered. In the case of flip mounting, since an underfiller is always filled between a chip and an IC package after bonding, a solder mask layer is not necessarily required between pads. However, when the semi-additive method is used, chemical C
The contact layer of Pd, Ag, etc. of u plating pretreatment remains,
When electroless plating of Ni or Au is performed, Ni and Au adhere to the resin surface between the external terminals and short-circuits. Therefore,
In the step of omitting the solder mask, a step of removing Pd or the like is required. However, since Pd or the like is removed by removing the surface resin such as Cr acid or permanganate together with Pd or the like, external terminals and wiring may be lost in the process of etching the resin.

Accordingly, the present invention has developed a method that does not use a solder mask in order to solve such problems in the prior art.

[0010]

The present invention has the following constitution. (1) A method for forming a wiring and a solder pad without using a solder mask, wherein after forming a resist for forming a wiring pattern, a buffer metal layer is formed as it is without removing the resist. IC to do
Package manufacturing method.

(2) A method of forming a wiring and a solder pad without using a solder mask. After forming a wiring pattern forming resist, a wiring is formed by electrolytic plating, and the resist is not removed. A method for manufacturing an IC package, wherein a buffer metal layer is formed by electrolytic plating as it is, and a solder layer is further formed by electrolytic plating.

(3) A method of forming a wiring and a solder pad without using a solder mask. After forming a wiring pattern forming resist, forming a wiring by electrolytic plating, and without removing the resist. A method of manufacturing a package, wherein a solder layer is formed by direct electrolytic plating.

The present invention has the above-described structure,
By using a plating resist used at the time of electrolytic plating for forming a circuit of the outermost layer of a multilayer substrate as a resist mask for a solder buffer metal film or a solder plating film to be formed on a pad, Cu plating can be performed as in the prior art.
A buffer metal film or a solder plating film can be formed without removing Pd or the like in a pre-plating process, and then a circuit on the outermost layer can be formed. Therefore, plating can be performed without exposing a resin surface between wirings. It is possible to eliminate the need for removing Pd and the like.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. In the present invention, the method of mounting an IC is not limited, but a case where solder bumps are used in general flip mounting will be described as an example.

First, as shown in FIG. 6, a via hole 4 is formed at the stage of forming the outermost layer of a built-up substrate. The interlayer insulating layer 3 is preferably made of a highly reliable epoxy or polyamide photosensitive resin or thermosetting resin. If the resin is photosensitive, the via hole 4 can be formed by photolithography. Also, via holes can be formed using a laser. In the case of a photo via, processing up to a via hole diameter of 10 μm is possible. After the formation of the via hole, roughening is performed for the purpose of cleaning the via bottom and roughening the resin surface. Next, electroless Cu plating 5 is applied to the surface of the interlayer insulating layer 3 as shown in FIG. In the semi-additive method, chemical copper is mainly used, but a conductive thin film (up to 2 μm thick) such as Ni plating can be used instead. Next, as shown in FIG. 8, a pattern resist 6 for a circuit on the outermost layer is formed using a photosensitive resin layer. Next, as shown in FIG. 9, a current is supplied to the underlying electroless Cu 5, and a portion not covered with the pattern resist 6 is subjected to electrolytic Cu plating 7.

In the present invention, the pattern resist 6
As shown in FIG. 1, a buffer metal (Ni or Au) plating 9 ′ as a solder diffusion preventing film is formed on the surface of the circuit pattern thickened by electrolytic Cu plating 7 without removing
And solder plating 10 '. Since there is an electroless Cu5 plating layer on the base, electrolytic plating can be used for plating of buffer metal and solder. The pattern resist 6 is peeled off as shown in FIG. As a result, the layer of electroless Cu 5 is exposed after the pattern resist 6 is peeled off, so that etching is performed using an etching solution such as hydrogen peroxide-sulfuric acid etching as shown in FIG. At this time, it is also possible to roughen the side surface of the wiring by using a roughening treatment solution manufactured by MEC.
By roughening the side surface of the wiring, it is possible to increase the adhesion strength with the underfiller.

Finally, if the solder is melted in a reflow furnace,
As shown in FIG. 4, the formation of the solder bump is completed.

[0018]

According to the present invention, electrolytic Cu for forming a circuit on the outermost layer is provided.
By using the plating resist used during plating as a buffer metal film of solder formed on the pad or a resist mask of the solder plating film, the buffer metal film and the solder plating film can be removed without removing the underlying electroless plating layer. Alternatively, it is possible to manufacture an IC package having fine external terminals by forming a solder plating film and then forming a circuit on the outermost layer. According to the second aspect, the solder layer can be formed simultaneously with the formation of the buffer layer at the same time as the formation of the buffer metal layer, and there is no need to separately provide a solder layer forming step. In the third aspect, the step of forming the buffer metal layer can be omitted.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a step different from the conventional one of the present invention.

FIG. 2 is an explanatory diagram of a next step of FIG. 1;

FIG. 3 is an explanatory view of the next step of FIG. 2;

FIG. 4 is an explanatory view of a step subsequent to FIG. 3;

FIG. 5 is an explanatory view of a first step of a conventional example.

FIG. 6 is an explanatory diagram of a step subsequent to FIG. 5;

FIG. 7 is an explanatory diagram of the next step of FIG. 6;

FIG. 8 is an explanatory diagram of a step subsequent to FIG. 7;

FIG. 9 is an explanatory diagram of a step subsequent to FIG. 8;

FIG. 10 is an explanatory diagram of a step subsequent to FIG. 9;

FIG. 11 is an explanatory diagram of a step subsequent to FIG. 10;

FIG. 12 is an explanatory view of a step subsequent to FIG. 11;

[Explanation of symbols]

 Reference Signs List 1 core substrate 2 wiring pattern 3 interlayer insulating layer 4 via hole 5 electroless Cu 6 pattern resist 7 electrolytic Cu plating 8 solder mask layer 9 electroless Ni, Au plating layer 10 solder ball

Claims (3)

[Claims] 1. A method for forming a wiring and a solder pad without using a solder mask, comprising forming a wiring pattern forming resist, forming a wiring by electrolytic plating, and removing the resist without removing the resist. A method for manufacturing an IC package, comprising forming a buffer metal layer. 2. A method for forming a wiring and a solder pad without using a solder mask, comprising forming a wiring pattern forming resist, forming a wiring by electrolytic plating, and removing the resist without removing the resist. An IC characterized in that a buffer metal layer is formed by electrolytic plating and a solder layer is further formed by electrolytic plating.
Package manufacturing method. 3. A method for forming a wiring and a solder pad without using a solder mask, comprising: forming a wiring pattern forming resist, forming a wiring by electrolytic plating, and removing the resist without removing the resist. A method for manufacturing a package, wherein a solder layer is formed by direct electrolytic plating.