JP2001117546A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To let a single CPU execute a time counting operation and a physical signal processing while saving the electric power, and also to unitize them. SOLUTION: A single CPU is driven by clock pulse generators of different frequencies, and when the CPU is in a sleep state, the CPU performs time counting processing or the like with a low frequency clock pulse generator, and when the CPU is in a wake-up state, the CPU performs the time counting processing and other signal processing based on the clock pulses from a high frequency clock pulse generator. When the CPU is changed over from the sleep state to the wake-up state, outputting to a display means is inhibited for a predetermined period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device having a CPU for performing signal processing by selectively selecting two types of clock pulses.

[0002]

2. Description of the Related Art First, a conventional timepiece drive circuit will be described with reference to FIG. 5, and a vehicle speed display device will be described with reference to FIG. First, the timepiece driving circuit performs a timekeeping operation by counting the clock pulses from the clock pulse generation circuit 3 by the timekeeping IC 2 which is always supplied with power from the vehicle-mounted battery 1. It is displayed on the display device 5. Therefore, the power of the vehicle-mounted battery 1 is constantly consumed.

[0003] The vehicle speed display device is configured as follows. That is, the vehicle-mounted battery 12 is connected to the interface circuit 10 via the ignition switch 11 and the vehicle speed sensor 13 is connected, and the interface circuit 10 is connected to the ignition switch 11.
Is turned on, a trigger signal is supplied to the CPU 14 to switch from the sleep state to the wake-up state, and a signal from the vehicle speed sensor 13 is supplied to the CPU 14.

The CPU 14 always receives power from the vehicle battery 12 via a power supply circuit 15 and receives a clock pulse from a clock pulse generator 16 (clock pulse generator 3 shown in FIG. 5).
Has a clock frequency that is at least 100 times higher than the frequency of the clock pulse from the interface circuit 10), monitors the output from the interface circuit 10, and if no signal is supplied for a predetermined time,
Go to sleep.

On the other hand, when receiving a trigger signal from the interface circuit 10, the CPU 14 switches from a sleep state to a wake-up state, processes a signal from the vehicle speed sensor 13, processes the signal from the vehicle speed sensor 13, and drives the liquid crystal display device 18 via a drive circuit 17. Is supplied with a display processing signal for display. More specifically, when the CPU 14 is in the sleep state, the CPU 14 periodically wakes up to monitor whether or not the trigger signal is supplied from the interface circuit 10. enter.

Here, when each of the clock drive circuit and the vehicle speed display device is constituted by separate units as described above, the number of parts is large, the cost is high, and the management becomes complicated, so that one unit is required. Can be considered.

[0007]

In this case, however, an ignition switch (power supply) shown in FIG.
The following problems are conceivable at the time of turning on and off of the crystal resonator, that is, at the time of starting and stopping the operation of the crystal unit. That is, as shown in FIG. 7B, the high frequency crystal oscillator of the clock pulse generation circuit used in the vehicle speed display device is almost turned on or off (see FIG. 7A) with the ignition switch (power supply). While having the characteristic of starting or stopping the operation at the same time, the crystal oscillator for low frequency of the clock pulse generation circuit used in the clock drive circuit is shown in FIG.
As shown in (C), the output does not stabilize unless a certain time T0 elapses immediately after the ignition switch (power supply) is turned on, and the vibration does not stop instantaneously even when the ignition switch is turned off. It was found that the time required for stabilizing the output at the time of turning on was almost the same as the time required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a first object of the present invention is to allow a single CPU to execute both a timekeeping operation and physical signal processing while performing power saving, and to execute them both in a single CPU. It is to unitize. The second purpose is
It is an object of the present invention to provide a function equivalent to various conventional functions of a clock drive circuit and a vehicle speed display device, and not to reduce the functions.

[0009]

A display device according to the present invention comprises a sensor, a first clock pulse generating circuit, and a first clock pulse generating circuit.
A second clock pulse generation circuit that oscillates at a frequency lower than the clock pulse output from the clock pulse generation circuit; and a time-counting process based on the clock pulse from the second clock pulse generation circuit in a sleep state. When switching from the sleep state to the wake-up state by receiving a trigger signal from the switch, the clock pulse timing process is switched to the clock pulse from the first clock pulse generation circuit, a time signal is output, and the clock signal is output from the sensor. Control means for performing signal processing on the detection output of and outputting a display processing signal, and display means for displaying a time signal and a display processing signal from the control means,
The control means prohibits output of a time signal and a display processing signal to the display means for a predetermined time when the sleep state is switched to the wake-up state.

[0010] In the display device according to the present invention, the predetermined time for prohibiting the output of the time signal and the display processing signal to the display means is set based on a point in time when the control means receives a trigger signal from the outside. The output of the display processing signal is started as a predetermined time elapses from the reference time.

In the display device according to the present invention, the predetermined time during which the output of the time signal and the display processing signal to the display means is prohibited is set by the transient characteristics of the clock pulse output from the second clock pulse generation circuit. Things.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments will be described below. Embodiment 1 FIG. 1, the same or equivalent components as those already described with reference to FIGS. 5 and 6 are denoted by the same reference numerals, detailed description thereof will be omitted, and only different portions will be described below. That is, only the timer circuit 20, the switching circuit 21, and the CPU 22 (control means) will be described below. In FIG. 1, the subclock pulse generation circuit denoted by reference numeral 3 is substantially the same as the clock pulse generation circuit 3 described with reference to FIG. The main clock pulse generation circuit indicated by reference numeral 16 is substantially the same as the clock pulse generation circuit 16 described with reference to FIG. Further, what is indicated by reference numeral 23 is a microcomputer,
It comprises a timer circuit 20, a switching circuit 21 and a CPU 22.

The timer circuit 20 activates a timer for a predetermined time T0 when the ignition switch 11 is turned on and receives a signal output from the interface circuit 10 to the CPU 22, and when the predetermined time T0 elapses, a switching signal is output. Is supplied to the switching circuit 21 and the switching circuit 2
1 is switched. That is, the switching circuit 21
When the PU 22 is in the sleep state, the clock pulse from the sub clock pulse generation circuit 3 is supplied to the CPU 22. When the PU 22 is switched to the wake-up state by receiving the switching signal from the switching circuit 21, the clock pulse from the main clock pulse generation circuit 16 is supplied. Supply to CPU22.

That is, as shown in FIG. 2, in the sleep state (section S1), the CPU 22 operates based on the low frequency clock pulse from the sub clock pulse generation circuit 3 to save power (1) (2)
(3) monitoring the presence or absence of an input signal from the interface circuit 10;
When the input signal is supplied from the sub-clock pulse generating circuit 3 at time t1 in FIG. 2, the oscillation of the crystal oscillator of the subclock pulse generation circuit 3 is stopped, and the electrical connection with the crystal oscillator is turned off.

Then, at a time t2 when a set time S2 at which it can be determined that the crystal oscillator has substantially stopped vibrating is activated, the main main clock pulse generating circuit 16 is operated, and based on the clock pulse, the CPU 22 executes the above (1). ) A watchdog function, (2) timekeeping processing, (3) monitoring for the disappearance of an input signal from the interface circuit 10, and (4) vehicle speed signal processing.

In addition to the functions of the CPU 22, the CPU 22 includes: (1) a watchdog function for monitoring runaway of the CPU 22; resetting when the runaway occurs; 3 has a timing process for prohibiting the output of the display signal to the display device 18 for a fixed time T0 after being switched to the main clock pulse generating circuit 16.

Next, the operation of the above configuration will be described with reference to the flowchart shown in FIG. The CPU 22
When power is constantly supplied from the vehicle battery 12 via the power supply circuit 15, the process proceeds from step 100 to step 101, where it is determined whether or not the ignition switch 11 is on. Go to 103, turn off the display device 18, and go to step 10
Proceed to 4. If it is determined in step 101 that the ignition switch 11 is on,
The display data generated based on the vehicle speed signal is supplied to the display device 18 for display, and the flow proceeds to step 104.

In step 104, it is determined again whether or not the ignition switch 11 is on, and if it is determined that the ignition switch 11 is off, the process proceeds to step 105, where the subclock pulse generating circuit 3 is started to operate and the timer circuit 2 is started.
Waiting for the lapse of the time T1 at which the clocking operation of 0 ends, the main clock pulse generating circuit 1 waits until the crystal oscillator of the subclock pulse generating circuit 3 stably oscillates.
6 is deactivated. If it is determined in step 104 that the ignition switch 11 is on, the process proceeds to step 108.

Step 107 is repeated until the ignition switch 11 is turned on in step 106 (until the apparatus is switched to the wake-up state). That is, it performs the watchdog function, the timekeeping process, and the monitoring of the supply of the input signal from the interface circuit 10.

If it is determined in step 106 that the ignition switch 11 has been turned on, step 108
To start the operation of the main clock pulse generation circuit 16 and wait for the lapse of the time T1 at which the clocking operation of the timer 20 ends, until the crystal oscillator of the sub clock pulse generation circuit 3 becomes in a state where it can be determined that the oscillation has stopped. Wait step 1
Return to 01.

[0021]

As described above, according to the present invention, there is an effect that the clocking operation and the physical signal processing can be executed by one CPU while saving power, without deteriorating the quality.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a circuit block used in a first embodiment according to the present invention.

FIG. 2 is an operation explanatory diagram illustrating an operation of two clock pulse generation circuits shown in FIG. 1;

FIG. 3 is a flowchart showing an operation of the microcomputer 23 in FIG.

FIG. 4 is another flowchart showing the operation of the microcomputer 23 in FIG.

FIG. 5 is a circuit block diagram illustrating a conventional timepiece circuit.

FIG. 6 is a circuit block diagram illustrating a conventional vehicle speed display device.

FIG. 7 is an explanatory diagram for explaining a difference in a transient characteristic between a high frequency crystal oscillator and a low frequency crystal oscillator constituting the clock pulse generation circuit.

[Explanation of symbols]

 Reference Signs List 10 interface circuit 11 ignition switch 12 vehicle-mounted battery 13 vehicle speed sensor 16 main clock pulse generation circuit 17 drive circuit 18 display device 20 timer circuit 21 switching circuit 22 CPU (control means)

Claims (3)

[Claims] 1. A sensor, a first clock pulse generation circuit, a second clock pulse generation circuit that oscillates at a lower frequency than a clock pulse output from the first clock pulse generation circuit, The first clock pulse generation circuit performs time measurement processing based on a clock pulse from a second clock pulse generation circuit, and performs time measurement processing of the clock pulse when switching from a sleep state to a wake-up state by receiving a trigger signal from the outside. A control means for outputting a time signal, processing a detection output from the sensor and outputting a display processing signal, and displaying the time signal and the display processing signal from the control means. Display means for switching from a sleep state to a wake-up state. A display device for prohibiting the output of the time signal and the display processing signal to the display means for a predetermined time when received. 2. The method according to claim 1, wherein the predetermined time for prohibiting the output of the time signal and the display processing signal to the display means is set based on a time when the control means receives a trigger signal from the outside. The output of the display processing signal is started as the predetermined time elapses.
The display device according to the above. 3. The method according to claim 1, wherein the predetermined time during which the output of the time signal and the display processing signal to the display means is prohibited is set by a transient characteristic of a clock pulse output from the second clock pulse generation circuit. The display device according to claim 2.