JP2001102524A - Integrated semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated semiconductor device, where with a ring current generated inside a substrate suppressed, a frequency characteristics is improved with a high inductance value and Q-value. SOLUTION: An MOS transistor 2, diode element 3, and inductor element 4 are formed on a P-type silicon substrate 1, by patterning in spiral a low- resistance silicon wiring pattern 5 where phosphorus is heavily doped via an electrical insulating layer 6 of a silicon oxide film before both end parts of the pattern 5 are led out with a metal film wiring pattern 8 via an electrical insulating layer 7. An N-type impurity diffused layer 9 connected to a conductor film pattern 11 comprising a contact hole 10 is formed, with a structure where a voltage can be applied from the surface of the silicon substrate 1 directly under the inductor element 4 to the inside to form a depletion layer 12. Thus, occurrence of ring current, where the magnetic flux generated by the inductor element 4 passes the depletion layer 12 to cancel the magnetic flux, is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated semiconductor device mounted on various devices mainly in the field of electronic communication and provided with an inductor element.

[0002]

2. Description of the Related Art Conventionally, in this type of integrated semiconductor device, a wiring formed by a diffusion layer, a silicon wiring doped with a high concentration of impurities, a wiring formed by a metal film, and the like are formed directly on a semiconductor substrate. Alternatively, it has a structure in which an inductor element (a so-called coil) having a spiral shape or the like is provided by being formed through an insulating layer such as a silicon oxide film.

[0003]

In the case of the above-described integrated semiconductor device, since the resistivity of a generally used semiconductor substrate is as low as about several tens of Ωcm or less, the magnetic flux generated by the inductor element is canceled. An annular current is generated inside the substrate to reduce the inductance value, and in the frequency characteristics, the Q value, which is a constant indicating the capability of the coil, is reduced due to the eddy current loss of the current generated at a high frequency. There is a problem that it becomes low.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and its technical problems are to suppress the annular current generated inside the substrate, to improve the frequency characteristics and to increase the inductance value and the Q value. An object of the present invention is to provide an integrated semiconductor device provided with an inductor element having a value.

Another technical object of the present invention is to provide an integrated semiconductor device which can obtain a desired inductance value.

[0006]

According to the present invention, there is provided an integrated semiconductor device in which a plurality of electric circuit elements are integrally formed on the same semiconductor substrate and which has at least one inductor element for obtaining an inductance. An integrated semiconductor device having a structure in which a depletion layer can be formed by applying a voltage to a local portion directly below the inductor element on the substrate is obtained.

According to the present invention, in the integrated semiconductor device, the inductor element is provided as a variable inductor element capable of obtaining a desired inductance value by adjusting the applied voltage to change the size of the depletion layer. Integrated semiconductor device is obtained.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An integrated semiconductor device according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a side sectional view of a main part showing a basic structure of an integrated semiconductor device according to one embodiment of the present invention.
FIG. 2 is a plan view showing the same integrated semiconductor device in a state where an upper surface portion is partially removed.

Referring to FIGS. 1 and 2, this integrated semiconductor device comprises a plurality of MOS transistors on a silicon substrate 1 of one conductivity type.
The transistor 2 and the diode element 3, as well as the inductor element 4 for obtaining an inductance, are formed by spirally patterning a low-resistance silicon wiring pattern 5 doped with phosphorus at a high concentration via an electrical insulating layer 6 made of a silicon oxide film. It is formed by drawing out both ends of the low-resistance silicon wiring pattern 5 with the metal film wiring pattern 8 via the electrical insulating layer 7 and from the surface of the silicon substrate 1 directly below the inductor element 4 to the inside. A reverse conductivity type impurity diffusion layer 9 connected to a conductor film pattern 11 having a contact hole 10 is formed as a structure capable of forming a depletion layer 12 by applying a voltage.

Here, a P-type silicon substrate 1 is used, and impurities (As) are ion-implanted into the low-resistance silicon wiring pattern 5 and the conductive film pattern 11 as a high-concentration N-type pattern of silicon or the like of the same material. A high-concentration N-type impurity diffusion layer 9 in which an annular current loop is unlikely to be formed is formed. Incidentally, the low-resistance silicon wiring pattern 5 is a MOS
The conductive film pattern 11 is electrically connected to the impurity diffusion layer 9 from the contact hole 10 by using the gate electrode material in the transistor 2. In FIGS. 1 and 2,
Portions not directly related to the main parts such as the wiring of the MOS transistor 2 and the diode element 3 and the upper wiring layer, the insulating layer, the protective layer, and the packaging are omitted.

In the integrated semiconductor device having such a structure, the generation of an annular current (eddy current) for canceling the magnetic flux by passing the magnetic flux generated by the inductor element 4 through the depletion layer 12 having a high resistivity is suppressed. Thus, the inductor element 4 has a higher inductance value and a high Q value capable of improving the frequency characteristics. In other words, in the case of the inductor element 4 here, there is no carrier in the depletion layer 12 that carries the conductivity of the impurity-doped semiconductor, the intrinsic semiconductor has a very high resistivity, and the magnitude of the eddy current with respect to the magnetic flux passing therethrough is large. As a result, a high inductance value is obtained, and a high Q value and an excellent frequency characteristic with no deterioration of the inductance value up to higher frequencies are obtained.

FIGS. 3A and 3B specifically show a modification of the formation pattern of the impurity diffusion layer 9 in the integrated semiconductor device, wherein FIG. 3A relates to the formation pattern 1 and FIG. FIG. 4C shows the pattern 2, FIG. 4C shows the pattern 3, and FIG. 4D shows the pattern 4.

As shown in FIGS. 3 (a) to 3 (d), the impurity diffusion layer 9 can be deformed into various shapes. , It is difficult to form an annular current loop.

FIG. 4 is a schematic view for explaining the basic operation of the inductor element 4 in the above-mentioned integrated semiconductor device.

Here, in the inductor element 4 disposed on the silicon substrate 1, when a current i is applied, the magnetic flux Φ
Are generated from the center toward the outside.

FIG. 5 is a schematic view for explaining an operational problem (generation of a ring current) that may occur locally in the inductor element 4 portion.

Here, in the inductor element 4 disposed on the silicon substrate 1, when the magnetic flux Φ is generated by the application of the current i described above, the silicon substrate 1 surrounds the magnetic force lines of the magnetic flux Φ so as to cancel the magnetic flux. This shows how an annular current i ', which is a so-called eddy current, is generated. Incidentally, the magnitude of the eddy current depends on the resistivity of the generated material, and the eddy current generated in the material having a low resistivity is a magnetic flux Φ passing through the material.
And the inductance value of the inductor element 4 is reduced, the frequency characteristic is degraded, and the Q value indicating the characteristic performance of the coil of the inductor element 4 is significantly reduced.

FIG. 6 is a cross-sectional side view for explaining the change in the operation of the formation pattern of the depletion layer 12 formed locally on the silicon substrate 1 immediately below the inductor element 4 in the integrated semiconductor device described above. is there.

Here, in the inductor element 4, the voltage applied to the impurity diffusion layer 9 connected thereto via the conductive film pattern 11 having the contact hole 10 by the power supply is adjusted (the magnitude of the applied voltage is controlled). The depletion layer 1 formed in the silicon substrate 1
2 shows that the inductor element 4 itself can be made a variable inductor element that can obtain a desired inductance value by changing the size of the inductor element 2. In this case, since the generation of the annular current can be suppressed more stably and accurately, as a result, a high inductance value, a high Q value, and an improvement in frequency characteristics are stably secured.

Incidentally, the constituent materials of the integrated semiconductor device of the above-described embodiment are merely examples, and the form is not particularly limited. For example, although a silicon film doped with phosphorus at a high concentration is used as the material of the gate electrode of the MOS transistor 2, a metal film such as aluminum or another conductive material may be used instead. It is. In one embodiment, a P-type silicon substrate 1 is used as a semiconductor substrate. However, an N-type substrate may be used instead, or a well-type substrate formed by ion implantation or the like may be used. Even if it is applied, the diffusion pattern for forming the depletion layer 12 only needs to be of the opposite conductivity type to the semiconductor substrate of one conductivity type, and any of them can be modified. Further, the structure of the inductor element 4 is formed in a spiral shape by the low-resistance silicon wiring pattern 5 in one embodiment. Instead, for example, a meander-shaped pattern structure as shown in FIG. Alternatively, as shown in FIG. 8, a one-turn loop pattern structure is also possible.

[0022]

As described above, according to the integrated semiconductor device of the present invention, the depletion layer can be formed by applying a voltage to a local portion of the semiconductor substrate immediately below the inductor element. The generation of an annular current (eddy current) that cancels the magnetic flux by passing the magnetic flux generated by the above through a depletion layer having a high resistivity is suppressed. As a result, a high inductance value is obtained, and a high Q value and a higher frequency are obtained. An excellent frequency characteristic without deterioration of the inductance value can be obtained. Also, in this inductor element,
By adjusting the applied voltage, the size of the depletion layer formed in the substrate can be changed, and the inductor element itself can be a variable inductor element capable of obtaining a desired inductance value. Be able to be enhanced.

[Brief description of the drawings]

FIG. 1 is a side sectional view of a main part showing a basic configuration of an integrated semiconductor device according to one embodiment of the present invention.

FIG. 2 is a plan view showing the integrated semiconductor device shown in FIG. 1 in a state where an upper surface portion is partially removed.

FIG. 3 specifically shows a modification of the formation pattern of the impurity diffusion layer 9 in the integrated semiconductor device shown in FIG.
(A) relates to the formation pattern 1, (b) relates to the formation pattern 2, (c) relates to the formation pattern 3, and (d) relates to the formation pattern 4.

FIG. 4 is a schematic diagram shown for explaining a basic operation of an inductor element portion in the integrated semiconductor device shown in FIG. 1;

FIG. 5 is a schematic diagram shown to explain an operational problem (generation of a ring current) that can occur locally in the inductor element portion described in FIG. 4;

6 is a side cross-sectional view shown for explaining an operational change of a depletion layer formation pattern formed locally on a silicon substrate immediately below an inductor element in the integrated semiconductor device shown in FIG. 1;

FIG. 7 is a schematic diagram showing a meandering pattern structure as a modification of the inductor element in the integrated semiconductor device shown in FIG. 1;

8 is a schematic diagram showing a once-turned loop-shaped pattern structure which is another modified example of the inductor element in the integrated semiconductor device shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 MOS transistor 3 Diode element 4 Inductor element 5 Low resistance silicon wiring pattern 6, 7 Electrical insulating layer 8 Metal film wiring pattern 9 Impurity diffusion layer 10 Contact hole 11 Conductive film pattern 12 Depletion layer

Claims (2)

[Claims] 1. An integrated semiconductor device in which a plurality of electric circuit elements are integrally formed on the same semiconductor substrate and which has at least one inductor element for obtaining an inductance, a local portion of the semiconductor substrate immediately below the inductor element. Is a structure capable of forming a depletion layer by applying a voltage. 2. The integrated semiconductor device according to claim 1, wherein the inductor element is provided as a variable inductor element that obtains a desired inductance value by adjusting an applied voltage to change a size of the depletion layer. Integrated semiconductor device characterized by the above-mentioned.