JP2001102599A - Variable capacitance semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a variable capacitance semiconductor device in which the size of a chip is reduced while sustaining the capacitance by forming an anode region while enlarging the area of PN junction in the depth direction, and to provide a chip part of smaller size by fabricating a plurality of variable capacitance semiconductor devices, in which the area of PN junction is reduced while sustaining the capacitance, in the same chip. SOLUTION: The variable capacitance semiconductor device has a large number of trenches 3 made in the upper surface of an epitaxial layer 2 grown on a semiconductor substrate 1 of the same conductivity, and a lightly doped anode region 4 of the opposite conductivity type formed on the upper surface of the epitaxial layer 2 and the side and bottom faces of the trenches 3. The area of a PN junction defined by the anode region 4 and the epitaxial layer 2 is increased in the depth direction along the inner wall of the trench in order to sustain the capacitance thus reducing the chip size.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable capacitance semiconductor device, and more particularly to a variable capacitance semiconductor device capable of reducing a chip size while maintaining a capacitance value.

[0002]

2. Description of the Related Art A variable capacitance semiconductor device is also called a varactor diode, and is widely used as a tuning variable capacitance in a tuner section of a radio receiver, a television receiver, or the like. The varactor diode is assembled as a chip component because of the simplicity and miniaturization of these devices and the ease of assembling.

FIG. 5 is a cross-sectional view illustrating a conventional variable capacitance semiconductor device. An N− type epitaxial layer 22 is laminated on an N + type semiconductor substrate 21, and a P type anode is formed on the upper surface of the epitaxial layer 22. Region 23 and anode region 2
3, a P + type contact region 24 is formed so as to surround the region 3, and an anode electrode 27 which is in contact with both regions 23 and 24 via a contact hole 26 provided in an oxide film 25 is provided. Although not shown, the cathode electrode is formed on the back surface of the semiconductor substrate 21. In such a variable capacitance semiconductor device, the anode region 23 and the epitaxial layer 22
The PN junction region on the plane formed by the above becomes a variable capacitance according to the voltage applied between the anode electrode 27 and the cathode electrode as a super step junction. In the conventional variable capacitance semiconductor device, the PN junction region formed by the anode region and the epitaxial layer is formed in a plane as shown by the oblique line 30 in FIG. 6, so that it is not possible to increase the size unless the chip area is increased. Can not.

[0004]

However, in such a conventional variable capacitance semiconductor device, since the area of the PN junction region determines the capacitance value, a chip size proportional to the capacitance value is required. For this reason, there has been a problem that it is impossible to maintain the capacitance value and reduce the size of the chip. In addition, there is a strong demand that a plurality of variable capacitance semiconductor devices be incorporated into the same chip to be supplied as smaller chip components. However, if a plurality of variable capacitance semiconductor devices are incorporated, there is a problem that the chip components become proportionally larger.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned various problems, and has a structure in which a plurality of trenches are formed on the surface of an epitaxial layer while being separated from each other, and a PN junction region is extended to a side wall surface of the trench. This has solved the problems so far by greatly increasing the area.

[0006]

FIG. 1 shows one embodiment of the present invention. An N− type epitaxial layer 2 is laminated on an N + type semiconductor substrate 1 to a thickness of about 15 to 25 μm. A large number of trenches 3 are provided on the upper surface of the epitaxial layer 2 and are spaced apart in a matrix, and a P-type anode region 4 of low impurity concentration is formed on the upper surface of the epitaxial layer 2 and the inner surface of the trench 3. Therefore, since the anode region 4 is formed on the upper surface of the epitaxial layer 2 and on the side and bottom surfaces of the trench 3, the shape becomes uneven in the depth direction of the epitaxial layer 2 as shown in FIG. Further, a P + type contact region 5 is formed so as to surround the anode region 4, and an anode electrode 7 which is in contact with both regions 4 and 5 via a contact hole 6 provided in an oxide film is formed. The cathode electrode 8 is formed on the back surface of the semiconductor substrate 1.

FIGS. 2 and 3 are plan views illustrating the arrangement of the PN junction region. The PN junction region is a region where the epitaxial layer 2 and the anode region 4 which is uneven along the surface of the trench 3 are in contact with each other, and is a portion where a variable capacitance is formed.
In FIG. 2, four PN junction regions are arranged in a cross in the same chip, and a large number of trenches 3 are formed in each PN junction region in a matrix. In FIG. 3, four PN junction regions are arranged in a stripe shape, and a plurality of trenches 3 are similarly formed in a matrix in each PN junction region. Therefore, in the arrangement shown in FIG. 2, an even number of variable capacitance semiconductor devices can be arranged, and in the arrangement shown in FIG. 3, even or odd number of variable capacitance semiconductor devices can be arranged. Here, the size of the area of the PN junction region is specifically calculated. Since the size of the conventional flat PN junction region is 676 μm × 321 μm, the area is 216,
996 square μm.

If a trench having a cross section of 50 μm × 50 μm is formed here, it is necessary to take a space between the trenches of about 40 μm or more, so that 18 trenches in 3 columns and 6 rows can be formed. When the depth of the trench is 10 μm, the area of the PN junction region formed on the side surface of the trench is increased by 50 μm × 10 μm × 4 planes × 18 = 36,000 square μm, and the total area is 252,996 square. μm, which is increased by about 16.5%. 20μ trench depth
In the case of m, the calculation is performed in the same manner and the number is increased by a factor of 72,000 square μm, and the total area is 288,996 square μm, which is increased by about 33.1%. 40μm × 40μ
When a trench having a cross section of m is formed, 4 columns and 8 rows of 32
Individual trenches can be formed. 10 μm trench depth
In this case, the area of the PN junction region formed on the side surface of the trench is 40 μm × 10 μm × 4 planes × 32 = 51,
With an increase of 200 square μm, the total area becomes 268,196 square μm, an increase of about 23.6%. When the depth of the trench is set to 20 μm, the calculation is performed in the same manner and the value is doubled to 72,
2,000 square µm, for a total area of 319,396 square µ
m, which is increased by about 47.2%. Therefore, the conventional P
Even if the N-junction region is reduced from 16% to 47%, the conventional capacitance value can be maintained, so that the chip area can be reduced or two or three chips can be incorporated in the same chip area. Next, a method of forming a trench will be specifically described with reference to FIG. In FIG. 4A, a P + type contact region 5 is already formed in the N− type epitaxial layer 2 laminated on the N + type semiconductor substrate 1 by the selective diffusion method, and the silicon oxide film 11 on the epitaxial layer 2 is formed. And a photoresist film 12 except for a region to be the trench 3 to be formed. Subsequently, the silicon oxide film 11 is dry-etched using the photoresist film 12 as a mask to expose the surface of the epitaxial layer 2. In FIG. 4B, the trench 3 is formed by etching the epitaxial layer 2 to a depth of about 10 μm to 20 μm by anisotropic plasma etching using the photoresist film 12 as a mask. For example,
HBr, NF3, He + O2 was used as an etching gas using a dry etching apparatus P-5000 of AMJ.
Etch using. In FIG. 4C, the trench 3
A PSG film 13 heavily doped with phosphorus is adhered to the inside and the surface of the epitaxial layer 2, and an anode region 4 is formed on the surface of the epitaxial layer 2 and the inner side surface and the bottom surface of the trench 3 by thermal diffusion. After that, the PSG film 13 is removed, aluminum is adhered as shown in FIG. 1 and the anode electrode 7 is formed by etching into a predetermined shape.

[0009]

According to the present invention, a large number of trenches 3 are formed in the PN junction region where the anode region 4 and the epitaxial layer 2 are in contact with each other. The area of the bonding area is from 16% to 4
It can be increased up to 7%. Therefore, if the capacitance value is maintained, there is an advantage that the area of the PN junction region can be reduced by an amount corresponding to the increase in the capacitance value. Also, while maintaining the capacitance value, P
Since the area of the N junction region can be reduced, for example, 33%
If the capacitance value can be increased, two varactor diodes have conventionally been incorporated in the same chip area.
There is an advantage that a smaller number of chip components can be supplied.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a variable capacitance semiconductor device according to the present invention.

FIG. 2 is a plan view illustrating an arrangement of a variable capacitance semiconductor device according to the present invention.

FIG. 3 is a plan view illustrating another arrangement of the variable capacitance semiconductor device according to the present invention.

FIGS. 4A, 4B, and 4C are cross-sectional views illustrating a method of manufacturing a trench used in the present invention.

FIG. 5 is a cross-sectional view illustrating a conventional variable capacitance semiconductor device.

FIG. 6 is a plan view illustrating an arrangement of a conventional variable capacitance semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 epitaxial layer 3 trench 4 anode region 5 contact region 6 contact hole 7 anode electrode 8 cathode electrode 11 silicon oxide film 12 photoresist film 13 PSG film

Claims (4)

[Claims] 1. A semiconductor substrate of one conductivity type having a high impurity concentration, an epitaxial layer of the same conductivity type grown on the semiconductor substrate, a number of trenches provided on an upper surface of the epitaxial layer, and an upper surface of the epitaxial layer. An anode region of opposite conductivity type and low impurity concentration formed on the side and bottom surfaces of the trench, wherein the area of the PN junction region formed by the anode region and the epitaxial layer is increased in the depth direction along the inner wall of the trench. A variable capacitance semiconductor device characterized by having been increased in number. 2. The variable capacitance semiconductor device according to claim 1, wherein said PN junction region is divided into a plurality of parts in the same chip. 3. The variable capacitance semiconductor device according to claim 2, wherein the PN junction region is divided into four in a cross shape in the same chip. 4. The variable capacitance semiconductor device according to claim 1, wherein the PN junction region is divided into a plurality of stripes in the same chip.