JP2001197028A - Transmission device and reception device for frequency multiplex data transmission - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission device and a reception device for frequency multiplex data transmission which effectively transmit a large amount of digital data by broadcasting or communication by using a radio transmission channel such as a satellite and the ground or a wired transmission line such as cable television. SOLUTION: Original data are obtained by separating digital data and sending them out to a transmission line after frequency multiplexing by plural digital modulating means, and putting together pieces of digital data obtained by plural selective demodulating means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency for multiplexing and transmitting digital data in broadcasting or communication using a radio transmission line such as a satellite or a ground or a cable transmission line such as a cable television (hereinafter referred to as CATV). The present invention relates to a transmission device and a reception device for multiplex data transmission.

[0002]

2. Description of the Related Art For digital transmission of CATV, 1
"Technical Report of the Institute of Television Engineers of Japan (vol. 19, No. 42) published on September 21, 995, pp. 19 to 24" I have. According to this report,
A transport stream in which digital data such as an image compressed by a digital image compression technique called MPEG2 (MPEG2) is multiplexed with a transport stream (hereinafter, referred to as TS) is a data series in a format called 29.16 per second.
2 megabits (29.162 Mbps) digital data is subjected to signal processing such as Reed-Solomon error correction,
The signal is modulated by a digital modulation technique called 4QAM (64-level quadrature amplitude modulation) and transmitted to a CATV transmission line at a transmission rate of 31.644 megabits per second (31.644 Mbps).

As a method of distributing multi-channel digitized video as an input of a digital CATV, there is satellite digital television broadcasting, which is described in Nikkei Electronics, September 2, 1996, 149.
As described in the paper "The First Digital Satellite Broadcasting to Achieve Near 70 Multi-Channels" in this page, a plurality of digitally compressed (MPEG2) programs and data are packet-multiplexed, scrambled, and corrected and encoded. The transmitted single TS is transmitted by QPSK digital modulation. A remultiplexing apparatus that remultiplexes digital data composed of a plurality of bit streams such as a digital broadcasting service using a single TS is disclosed in Japanese Patent Application Laid-Open No. H10-41909.
Is shown in According to this publication, a single TS is 18
It is composed of an 8-byte TS packet.
It is shown that it consists of 84 bytes of packet data and 4 bytes of packet header. By re-editing and transmitting program control information etc. in the packet header in re-multiplexing, it is possible to receive data from multiple broadcasters at the receiving terminal. At the same time.

On the other hand, in a newly planned BS digital broadcast, transmission channel 1 of the conventional BS analog broadcast is used.
It plans to transmit not only a plurality of conventional standard television broadcasts but also high-definition television broadcasts to channels. Regarding the transmission of BS digital broadcasting, see the journal of the Visual Media Society of Japan (vol.
52 No. 11 1998) "B
S Digital Broadcasting System and Equipment ". BS
Digital broadcasting has a transmission capacity of about 60 Mbps,
Multiple transponders (one transponder) can use a plurality of modulation schemes, and a TS for video, audio, data, etc. has a frame configuration to allow a plurality of TSs (hereinafter, a plurality of T
S) is sent in a new data format so that it can be transmitted. In this data format, a transmission multiplex control signal (hereinafter, referred to as a TMCC signal) is used for transmitting modulation information in a frame and control information of a configuration of a plurality of TSs. According to the Ministry of Posts and Telecommunications Ordinance No. 57, the TMCC signal is divided and transmitted for each frame (= 48 slots, 1 slot = 204 bytes) before the main signal using the synchronization signal portion of the TS, and one superframe (= 8 frames) ) Is transmitted as a cycle. The configuration is shown in the Ministry of Posts and Telecommunications Notice No. 260, and the transmission mode / slot information is used for selecting the digital demodulation means.
The correspondence between the S / slot information and the relative TS / TSID is used for selecting and outputting a desired TS ID (TSID). In addition, there are transmission / reception control information such as a change instruction number and emergency information and an extended information area.

In the conventional digital CATV technology described above, B
Since the transmission and reception of multiple TS transmissions planned for S digital broadcasting were not considered, July 27, 1999
Technical Report of the Institute of Image Information and Television Engineers (vo
l. 23, no. 48), "Proposal of Multiple MPEG-TS Cable TV Multiplexing System" on pages 7 to 12 and "Experiment on Cable TV Transmission of Multiple MPEG-TS" on pages 13 to 18 of the same report. In these reports, N 188-byte TS packets are collected to form a multiplexed frame, and the T
A TSMF header that describes S arrangement information and the like has been proposed. According to this proposal, a plurality of TS signals can be efficiently transmitted to a cable television through BS digital broadcasting. In this proposal, a BS digital broadcast data with a transmission rate of 52.17 Mbps is transmitted as two digital CATV signals using a 6 MHz band 64QAM with a transmission rate of 29.162 Mbps, and a 12 Mbps signal with a transmission rate of 57.607 Mbps.
Digital CATV signal 1 using 64QAM in Hz band
There is a proposal to transmit by using a wave, and in both cases, a null TS is inserted for synchronization to match the difference between the transmission speeds of BS digital broadcasting and digital CATV, and program clock information (hereinafter, referred to as “reproducing system clock” on the receiving side). , PCR information).

[0006] As a method of cable transmission for BS digital broadcasting, a technical report of the Institute of Image Information and Television Engineers (vol.23, No.4) published on July 27, 1999.
8), page 19 to page 24, "frequency conversion PSK transmission system for joint reception facilities of BS digital broadcasting". In this report, the PSK transmission on the cable transmission line is performed only by frequency conversion without converting the modulation method of the BS digital broadcast signal, and a relatively wide transmission band of 34.5 MHz is required. It is a suitable method.

[0007]

Among these reports, in the 6-MHz band 64QAM system, the transmission rate is 2
Since transmission is performed using two signals of 9.162 Mbps digital CATV, in the proposal according to the report, BS digital broadcasting with a transmission rate of 57.607 Mbps constituted by a plurality of TSs is used as an example. A case is shown in which repeater information is transmitted by two TSs each using two 64QAM signals. The number of packets and the transmission speed of 188 bytes of each TS are 24.210 Mbps for TS1 for 44 packets and 4.4 for TS2 for 8 buckets.
02 Mbps, TS3 is 15.406M with 28 packets
bps, TS4 is 8.804 Mbps with 16 buckets, and the total transmission speed of TS1 and TS2 is 28.612.
Mbps, the total transmission speed of TS3 and TS4 is 24.
210, and the transmission speed for inserting a TSMF header of one packet into a total of 52 packets of TS1 and TS2 is 64.
In the example where the transmission rate of the QAM coincides with the transmission rate of 29.162 Mbps, a TSMF header of one packet is inserted into a total of 44 packets of TS3 and TS4, and a null packet of eight packets is inserted.
An example of matching with 9.162 Mbps is shown.

However, in the frame configuration in the multiplexing, since the TSMF header is inserted, 28.61 is used.
2 Mbps is the maximum transmission rate of 1 TS in the 6-MHz band 64 QAM system.
6MHz band 64QAM for transmitting to the receiving device
There was no proposal for the method.

[0009] In those reports, the transmission rate 2
A system capable of transmitting a TS of 8.612 Mbps or more includes a PSK transmission system and a 12 MHz band 64QAM.
However, the PSK transmission method has a wide transmission bandwidth and is difficult to operate in a company that provides cable television services. The method of 12 MHz band 64QAM is as follows.
In CATV transmission in which the frequency is assigned in units of 6 MHz, an empty channel is required in the band of two adjacent waves, and there is a difficulty in frequency allocation. In addition, the current CATV retransmits analog terrestrial television. The frequency arrangement is such that the residual sideband modulation is performed using a frequency higher by 1.25 MHz from the lower frequency end of the channel of the 6 MHz band as a video carrier. In the television receiver that receives the signal, the oscillation frequency of the local oscillator for selecting the reception frequency is set to 58.75 MHz higher than the video carrier to be received. Even if the leakage of the local oscillator of the television receiver returns on the CATV transmission line, the frequency setting occurs at the boundary of the channel in units of 6 MHz.
The frequency is allocated so as not to damage the transmitted signal. Therefore, 12
In the case of the 64 QAM system in the MHz band, further measures for channel arrangement were required.

[0010] The present invention relates to a BS digital broadcast having a plurality of transport streams and a transmission rate of 28.612M.
For example, broadcasting and communication using a radio transmission line such as a satellite or a terrestrial or a cable transmission line such as a cable television, for example, transmitting a TS of bps or more by CATV transmission in a channel of 6 MHz by digital modulation such as multi-level QAM such as 64 values. Provided are a transmission device and a reception device for frequency multiplex data transmission for effectively transmitting a large amount of digital data.

[0011]

According to a first aspect of the present invention, there is provided a transmission apparatus for frequency multiplexed data transmission, which converts digital data into frequency in broadcast or communication using a radio transmission line such as a satellite or a ground or a cable transmission line such as a cable television. In a transmission apparatus for frequency-multiplexed data transmission for multiplexing and transmitting, a separating unit that separates the digital data into a plurality of digital data, and a plurality of digital data outputs of the separating unit, the wireless transmission line or the wired transmission line. A plurality of digital modulating means for digitally modulating by a modulation method of the transmission method, and a signal synthesizing means for frequency-multiplexing a plurality of modulated waves including outputs of the plurality of digital modulating means and transmitting the multiplexed waves to a transmission path. It is characterized by.

According to a second aspect of the present invention, there is provided a transmitting apparatus for frequency multiplexed data transmission, which transmits digital data by frequency multiplexing in broadcasting or communication using a radio transmission line such as a satellite or a terrestrial transmission line or a cable transmission line such as a cable television. In a transmission device for multiplex data transmission, the digital data is separated into a plurality of digital data, and null digital data for matching is multiplexed to match the digital transmission data rate of the transmission system of the wireless transmission line or the wired transmission line. A multiplexing means for outputting a plurality of transport stream format digital data, and a plurality of digital data outputs of the multiplexing / demultiplexing means being digitally modulated by a modulation method of a transmission system of the wireless transmission line or the wired transmission line. A plurality of digital modulation means for modulating, and a plurality of outputs including outputs of the plurality of digital modulation means It is characterized in that a signal synthesizing means for delivering to the transmission line by frequency multiplexing the modulated wave.

According to a third aspect of the present invention, there is provided a transmission apparatus for frequency-division multiplexed data transmission which transmits digital data by frequency multiplexing in broadcasting or communication using a radio transmission line such as a satellite or a terrestrial transmission line or a cable transmission line such as a cable television. In a transmission device for multiplex data transmission, a packet header is multiplexed so as to separate the digital data into a plurality of digital data to obtain a transport stream type digital data, and a transmission method of the wireless transmission line or the wired transmission line is used. Separation header multiplexing means for multiplexing null digital data for matching to match the digital transmission data rate and outputting a plurality of digital data in a transport stream format, and outputting a plurality of digital data outputs of the separation header multiplexing means to the radio Transmission line or the transmission method of the wired transmission line And a signal synthesizing unit for frequency-multiplexing a plurality of modulated waves including outputs of the plurality of digital modulation units and transmitting the modulated waves to a transmission path. .

According to a fourth aspect of the present invention, there is provided the transmission apparatus for frequency multiplexing data transmission according to the first, second or third aspect of the invention, wherein the plurality of digital modulating means have a digital transmission data rate. It is characterized in that the reference clock frequency is synchronized with the network clock frequency of another broadcasting system or communication system.

According to a fifth aspect of the present invention, there is provided a transmission apparatus for frequency multiplexing data transmission according to the first, second, third or fourth aspect of the present invention, When the method is multi-level modulation, the multi-level is made variable and the multi-level is selected and transmitted according to the signal quality of the frequency multiplexed and transmitted frequency of the wireless transmission path or the wired transmission path. It is characterized by:

According to a sixth aspect of the present invention, there is provided the transmission apparatus for frequency multiplexed data transmission according to the first, second, third, fourth, or fifth aspect of the invention.
The wireless transmission path or the wired transmission path is a cable-based cable television transmission, and the plurality of digital modulating means are transmitted by digital modulation of multi-level QAM such as 64-value, so that digital transmission such as satellite or terrestrial transmission is possible. It is characterized in that digital data in a transport stream format is selected from the broadcast and transmitted according to the digital transmission data rate of the cable television.

According to a seventh aspect of the present invention, there is provided the transmission apparatus for frequency multiplexed data transmission according to the third, fourth or fifth aspect of the present invention, wherein the wireless transmission line or the wired transmission line is provided. In the case of cable-based cable television transmission, the digital data output from the plurality of digital data of the separation header multiplexing means is used to separate the plurality of transport stream format digital data and the plurality of transport stream format digital data on the receiving side. And transmitting the digital data in the form of a transport stream from digital broadcasting such as satellite or terrestrial broadcasting and transmitting the digital data in accordance with the digital transmission data rate of cable television.

The receiving apparatus for frequency multiplexed data transmission according to the eighth invention is a frequency multiplexing and transmitting digital data for broadcasting or communication using a radio transmission line such as a satellite or a terrestrial transmission line or a cable transmission line such as a cable television. In the receiving apparatus for multiplex data transmission, a desired plurality of digital modulated waves are selected from a plurality of modulated waves transmitted by frequency multiplexing on the wireless transmission line or the wired transmission line, and the wireless transmission line is selected. Alternatively, a plurality of selective demodulation means for performing digital demodulation in accordance with the digital modulation method of the transmission method of the wired transmission path, and a plurality of digital data output from the plurality of selective demodulation means are combined to obtain digital data before transmission. And a digital data synthesizing means for returning to.

According to a ninth aspect of the present invention, there is provided a frequency multiplexing data transmission receiving apparatus for transmitting digital data by frequency multiplexing in broadcasting or communication using a radio transmission line such as a satellite or a terrestrial transmission line or a cable transmission line such as a cable television. In the receiving apparatus for multiplex data transmission, a desired plurality of digital modulated waves are selected from a plurality of modulated waves transmitted by frequency multiplexing on the wireless transmission line or the wired transmission line, and the wireless transmission line is selected. Alternatively, a plurality of selective demodulation means for performing digital demodulation conforming to the digital modulation method of the transmission method of the wired transmission line, and the wireless system transmission from a plurality of transport stream format digital data output from the plurality of selective demodulation means. Null digital data for matching to the digital transmission data rate of the transmission system of the transmission line or the wired transmission line. A plurality of digital data separating means for removing is characterized by comprising a digital data combining means for a plurality of digital data combined back into digital data before transmission, which is the output of said plurality of digital data separating means.

According to a tenth aspect of the present invention, there is provided a frequency multiplexing data transmission receiving apparatus for transmitting frequency-multiplexed digital data in broadcast or communication using a radio transmission line such as a satellite or a terrestrial transmission line or a cable transmission line such as a cable television. In the receiving apparatus for multiplex data transmission, a desired plurality of digital modulated waves are selected from a plurality of modulated waves transmitted by frequency multiplexing on the wireless transmission line or the wired transmission line, and the wireless transmission line is selected. Alternatively, a plurality of selective demodulation means for performing digital demodulation conforming to the digital modulation method of the transmission method of the wired transmission line, and the wireless system transmission from a plurality of transport stream format digital data output from the plurality of selective demodulation means. Digital data for matching to the digital transmission data rate of the transmission system of the transmission line or the wired transmission line A plurality of data header separating means for removing a packet header multiplexed to be a transport stream format digital data; and a plurality of digital data output from the plurality of data header separating means, and the digital data before transmission are synthesized. And a digital data synthesizing means for returning to.

According to an eleventh aspect of the present invention, there is provided the frequency multiplexing data transmission receiving apparatus according to the eighth, ninth, or tenth aspect of the present invention, wherein the plurality of selective demodulating means have multiple digital demodulation systems. It is characterized in that digital demodulation is performed according to a modulation signal of a signal transmitted as a variable value level.

According to a twelfth aspect of the present invention, in the frequency multiplexing data transmission receiving apparatus according to the eighth, ninth, tenth or eleventh aspect,
The wireless transmission line or the wired transmission line is a cable-based cable television transmission, and the digital demodulation methods of the plurality of selective demodulation means are digitally demodulated according to a digital modulation signal of a multi-level QAM such as a 64-level. It is characterized by.

According to a thirteenth aspect of the present invention, in the frequency multiplexing data transmission receiving apparatus according to the ninth, eleventh, or twelfth aspect, the radio transmission line or the wired transmission line is provided. The cable is a cable-based cable television transmission, and the digital data synthesizing means includes a plurality of digital data input from the plurality of digital data separating means, a plurality of transport stream format digital data, and an output of the plurality of digital data separating means. And a plurality of digital data in a transport format are synthesized.

According to a fourteenth aspect of the present invention, there is provided the frequency multiplexing data transmission receiving apparatus according to the tenth, eleventh, or twelfth aspect of the present invention, wherein the radio transmission line or the wired transmission line is provided. The cable-based cable television transmission, wherein the digital data synthesizing unit converts the plurality of digital data input from the plurality of data header separating units into a plurality of transport stream format digital data and the plurality of transport stream format digital data. A plurality of transport stream format digital data composed of headers for separating the plurality of transport format digital data output from the plurality of data header separating means, and then combining the header information and the like. By a single transport stream It is characterized by separating and outputting the beam format digital data.

According to the above-mentioned means, in broadcasting or communication using a wireless transmission line such as a satellite or a terrestrial transmission line or a cable transmission line such as a cable television, digital data is separated and frequency-multiplexed by a plurality of digital modulating means and transmitted to the transmission line. The transmitting and receiving sides can obtain the original data by synthesizing a plurality of digital data obtained by the plurality of selective demodulation means, so that a large amount of digital data can be effectively transmitted.

Further, since data can be transmitted in the form of a transport stream in which digital data such as images compressed by the MPeg 2 are multiplexed, a large capacity required for future digital broadcasting such as three-dimensional video is required. Digital data can be effectively transmitted.

Further, since transmission can be performed based on a reference oscillation frequency synchronized with an integral multiple of 8 kHz which is a synchronous clock frequency of a telephone public line network, matching with communication becomes possible.
It is possible to provide a transmitting device and a receiving device for large-capacity digital data transmission capable of integrating broadcasting and communication.

Further, the multi-level is changed according to the signal quality of the frequency multiplexed and transmitted frequency of the radio transmission line or the wired transmission line by using digital modulation means for changing the multi-level of the multi-level modulation. Since the data can be selectively transmitted, large-capacity digital data can be utilized to the fullest extent of the performance of the transmission path.

Further, when transmitting to a cable television, since transmission is performed in a plurality of 64 MHz QAM bands, the leakage of the local oscillator of the television receiver due to the current analog terrestrial television retransmission in the cable television is caused on the CATV transmission path. Even if it returns to, it is not affected and the bandwidth of the transmission path can be used to the maximum.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a transmitting apparatus and a receiving apparatus for frequency multiplex data transmission according to an embodiment of the present invention. In FIG. 1, 1 is a transmitting device, 2 is a receiving device,
3 is a transmission line, 11 is a data input terminal, 12 is a data separation circuit, 13a, 13b, 13n are digital modulation circuits,
4 is a frequency multiplexing circuit, 21a, 21b and 21n are frequency selection circuits, 22a, 22b and 22n are digital demodulation circuits, 24 is a data synthesis circuit, and 25 is a data output terminal. In one embodiment of the present invention, only main functional units are shown, and peripheral circuit blocks such as a control microcomputer are omitted.

FIG. 2 is a conceptual diagram of frequency multiplexing on a transmission line according to the present invention, and shows a signal transmitted to the transmission line 3 in FIG.
Is the modulated wave output from the digital modulation circuit 13a,
003 indicates a modulated wave output from the digital modulation circuit 13b.

In the transmitting apparatus 1 shown in FIG. 1, the digital data from the data input terminal 11 is separated by the data separating circuit 12 into digital data, whereby the transmission speed of one digital data string is reduced and the transmission speed is reduced. A plurality of delayed digital data are applied to a plurality of digital modulation circuits 13a, 13b or 13n. The digital modulation circuit 13a,
The modulated wave digitally modulated by 13b or 13n is frequency-multiplexed by the frequency multiplexing circuit 14 and transmitted to the transmission line 3.

In the receiving apparatus 2 shown in FIG. 1, a plurality of digitally modulated waves transmitted to the transmission line 3 are input, and a plurality of frequency selection circuits 21a and 21b are obtained from the plurality of digitally modulated waves. Alternatively, a required modulated wave is selected by 21n, and the selected modulated wave is digitally demodulated by the digital demodulation circuits 22a, 22b or 22n. The original data can be obtained by synthesizing a plurality of digital data obtained by digital demodulation by the data synthesizing circuit 24.

As a result, it is possible to transmit more data than can be transmitted by each carrier. For example, C
In the case of ATV, the transmission speed in 64 QAM in a 6 MHz band is 31.644 Mbit / sec, and the transmission capacity excluding redundant data for error correction is 29.162 / sec.
Megabit, but as shown in the present invention, its 6 MH
If a 64QAM signal in the z band is frequency-multiplexed with a plurality of 34 waves, data of about 1 giga (1000 megabits) per second can be transmitted. In other words, it is possible to construct a gigabit transmission line and a giga network using the CATV transmission line.

In the case of BS digital broadcasting, 3
5 per second with one transponder with 4.5 MHz bandwidth
2. High-definition video compressed by MPeg 2 is about 20 Mbits / sec with a transmission capacity of 2.17 megabits, so if it is a current video, one transponder can transmit two programs of high-definition video. It is. Here, when a three-dimensional image is considered using multi-view digital data, the capacity of an image captured by 20 eyes is about 20 times, and a high-definition three-dimensional image is considered to require about 400 megabits per second. There is a lot of correlation between the images captured by the eyes.
If it is assumed to be reduced by a factor of 1, it will be about 80 megabits per second. If the present invention is applied to BS digital broadcasting in the 34.5 MHz band, it will be possible to broadcast high-definition three-dimensional video with two transponders. However, assuming that it can be reduced to about one tenth by using digital image compression technology, it becomes about 40 megabits per second, which is 34.5M.
This is a calculation that can broadcast a high-definition three-dimensional video with one transponder having a Hz band.

FIG. 3 is a block diagram showing a transmitting apparatus and a receiving apparatus for frequency multiplex data transmission according to an embodiment of the present invention. In FIG. 3, 31a, 31b and 31n are multiplexing circuits, 33a, 33b and 33n are digital modulation circuits,
34 is a data separation / combination circuit, 311a, 311b, 31
1n is a synthesis circuit, 312a, 312b, 312n are null data generation circuits, 313a, 313b, 313n are speed comparison circuits, 331a, 331b, 331n are reference clocks of a digital modulation circuit, and the same numbers as those in FIG. Is shown.

In this embodiment, the transmission speed of each output data of the data separation circuit 12 is set to the digital modulation circuit 33a,
This is an embodiment when the transmission speed does not match the transmission speed of 33b or 33n. In order to control the transmission speed, the speed comparison circuit 313a, 313b or 313n uses a reference clock 33 of the digital modulation circuit based on the transmission speed of the digital modulation circuit 33a, 33b or 33n.
1a, 331b, or 331n, and speed information from the combining circuits 311a, 311b, or 311n to compare speed information, obtain a speed error signal, and generate a null data generation circuit according to the speed error. Null data from 312a, 312b or 312n is transmitted. The multiplexing circuit 3 is provided by the null data.
The transmission speed from 1a, 31b or 31n can match the transmission speed of digital modulation circuit 33a, 33b or 33n.

As a result, in the present embodiment, null data can be multiplexed by the null data generation circuit, so that the transmission speed of digital data from the data input terminal 11 is lower than the total transmission speed of frequency-multiplexed transmission. The transmission speed can be matched with the transmission speed of the digital modulation circuit.

In this embodiment in which digital data of BS digital broadcasting is transmitted by CATV, the digital data from the data input terminal 11 is digital data in the form of a transport stream, and is transmitted by one transponder having a 34.5 MHz band. A transmission capacity of 52.17 megabits per second. Since the transmission capacity of CATV in the 6 MHz band at 64 QAM is 29.162 megabits per second,
Although two waves of 64 QAM in the 6 MHz band are used, the total transmission capacity is 58.324 Mbits / sec, and the difference can be compensated for by multiplexing null data. However, in digital data in a transport stream format such as BS digital broadcasting, Since the signal processing is performed using packetized data of 188 bytes, it can be realized by multiplexing null packets.

FIG. 4 is a diagram for explaining an example of a frame structure of a transport stream according to the present invention. The transmission rate to which the 64 QAM error correction code of the 6 MHz band is added is 3 per second.
1 shows an example of a frame configuration of a 1.644 Mbit transport stream. 4000 is a data stream in a transport stream format including an error correction code, 4001 is a synchronization byte, 4002 is digital data, and 4003 is an error correction code. The synchronization byte 4001 and the digital data 4002 constitute a 188-byte digital data stream in the form of a transport stream, which represents a transmission capacity of 29.162 megabits per second. Also, the synchronization byte 4001
204 bytes obtained by adding the error correction code 4003 to the digital data 4002 correspond to a transmission rate of 31.644 megabits per second. This transmission speed determines the transmission band.

FIG. 5 is a block diagram showing a transmitting apparatus and a receiving apparatus for frequency multiplex data transmission according to an embodiment of the present invention. In FIG. 5, reference numerals 51a, 51b and 51n denote a header multiplexing circuit, 52 denotes a header separation data synthesizing circuit,
1a, 511b and 511n are synthesis circuits, 512a and 51
2b and 512n are null data generation circuits, 513a and 51
3b, 513n are speed comparison circuits, 514a, 514b,
514n is a header generation circuit, and the same numbers as those in FIG. 3 indicate the same functional blocks.

In the present embodiment, when the digital data from the data input terminal 11 is not a data stream in the transport stream format, but another transmitting device or receiving device such as a digital modulation circuit is a data stream in the transport stream format, An example will be described in which transmission is performed in accordance with the data sequence. The header from the header generation circuit 514a, 514b or 514n is combined with each output data of the data separation circuit 12, and the combination circuit 511a, 511b or 511n is combined.
And the reference clock 331a, 331b or 331n of the digital modulation circuit based on the transmission speed of the digital modulation circuit 33a, 33b or 33n.
The speed comparison circuit 513 compares the speed information with the transmission speed information of the
a, 513b or 513n to obtain a speed error signal, and a null data generation circuit 512 according to the speed error.
a, 512b or 512n is transmitted. By using the null data, the header multiplexing circuit 5
The transmission speed from 1a, 51b or 51n can match the transmission speed of digital modulation circuit 33a, 33b or 33n.

As a result, in the present embodiment, the digital data from the data input terminal 11 is not a data stream in the transport stream format, but another transmitting device or receiving device such as a digital modulation circuit has a data stream in the transport stream format. Also in this case, the transmission speed can be made to match the transmission speed of the digital modulation circuit.

FIG. 6 is a configuration diagram showing a transmitting apparatus and a receiving apparatus for frequency multiplex data transmission according to an embodiment of the present invention. In FIG. 6, 6 is a telephone public network, 61 is a telephone public network input terminal, 62 is a telephone public network synchronization circuit, 63 is a clock control circuit, 64a, 64b, 64n.
Denotes a digital modulation circuit, 641a, 641b, and 641n denote clock synchronization circuits, and the same numbers as those in FIG. 3 indicate the same functional blocks.

In this embodiment, the transmitting apparatus is for transmitting frequency-division multiplexed data in synchronization with the telephone public line network 6,
A clock control circuit 63 generates a reference signal from a telephone public network synchronization circuit 62 in response to a signal from a telephone public network input terminal 61, and a clock synchronization circuit 641a, 641 in a digital modulation circuit 64a, 64b or 64n.
b, 641n to generate a clock synchronized with the reference signal from the clock control circuit 63,
a, 64b or 64n is operated as a reference clock serving as a reference. According to the reference clock, the speed comparison circuit 313a, 313b or 313
n is the null data generation circuit 312a, 312b or 3
12n, and sends out the null data from the combining circuit 311.
a, 311b or 311n.

As a result, in the present embodiment, since transmission can be performed based on the reference oscillation frequency synchronized with an integral multiple of 8 kHz, which is the synchronous clock frequency of the telephone public network, it is possible to match with the communication, and with the broadcast. It is possible to provide a transmitting device and a receiving device for large-capacity digital data transmission in which communication can be integrated.

FIG. 3 shows the telephone public network 6, telephone public network input terminal 61, telephone public network synchronization circuit 62, clock control circuit 63, and digital modulation circuits 64a and 64b. , 64n are added to form the embodiment of FIG. 6, but the same effect can be obtained by adding to FIG. 1 and FIG.

FIG. 7 is a block diagram showing a transmitting device and a receiving device for frequency multiplex data transmission according to an embodiment of the present invention. In FIG. 7, reference numerals 71a, 71b, and 71n denote variable multi-value digital modulation circuits, and reference numerals 72a, 72b, and 72n denote variable multi-value digital demodulation circuits.

In the present embodiment, the multilevel digital modulation circuits 71a, 71b or 71n of the transmitter 1 are used to adjust the signal quality of the frequency transmitted by the frequency multiplexing of the radio transmission line or the wired transmission line. In the receiving apparatus 2, the digital demodulation circuits 72a, 72b, and 72n respectively perform digital demodulation in accordance with the multilevel levels of the plurality of digitally modulated waves transmitted to the transmission path 3. I do.

As an example where the change of the multilevel is effective,
There is a wired transmission path such as CATV. An example is shown in FIG. FIG. 8 is a conceptual diagram of frequency multiplexing on the transmission line according to FIG. 7 of the present invention, showing a signal transmitted to the transmission line 3 in FIG.
02 is a modulated wave modulated by 64QAM digital modulation, 800
Numeral 3 indicates a modulated wave subjected to 16QAM digital modulation. In a wired transmission line such as a CATV, there is no restriction on the used frequency band unlike the wireless system, and it is possible to use the frequency band used in the wireless system. There are frequency bands that are not easily affected. In such a transmission path, for example, it is possible to transmit at 64 QAM in a frequency band that is not easily affected. Transmission with reduced modulation is possible.

In the present embodiment, digital modulation means for changing the multi-level of the multi-level modulation is used, and the multi-level modulation is performed in accordance with the signal quality of the frequency transmitted by frequency multiplexing of the radio transmission line or the wired transmission line. Since the value level can be selected and transmitted, large-capacity digital data can be used to the fullest in the performance of the transmission path.

The description of this embodiment is based on the assumption that the digital modulation circuits 13a, 13b and 13n in FIG. 1 are replaced by variable multi-value digital modulation circuits 71a, 71b and 71n, and the digital demodulation circuits 22a, 22b and 22n are replaced by variable multi-value digital signals. Demodulation circuit 7
Although the embodiment of FIG. 7 is changed to 2a, 72b, and 72n, the same effect can be obtained by changing the digital modulation circuit and the digital demodulation circuit of FIGS. 3, 5, and 6.

FIG. 9 is a block diagram showing a transmitting apparatus and a receiving apparatus for frequency multiplex data transmission according to one embodiment of the present invention, and shows a configuration example in the case of transmitting a BS digital broadcast by CATV. In FIG. 9, 90 is a modulated signal of BS digital broadcasting, 91a and 91m are BS digital receivers, 92a,
92m is a data separation circuit, 93a, 93b and 93m are 6
4QAM modulation circuit, 94a, 94b, 94n are multiplexing circuits, 901a, 901m are digital demodulation / decoding circuits, 9
02a and 902m are TMCC decoding circuits, 921a and 92
1b is a 64QAM demodulation circuit, 922a and 922b are error correction circuits, 923 is a data separation / combination circuit, and 924 is a TS
A packet separation circuit, 925 is an MPEG video decoder circuit, 926 is an audio decoder circuit, 927 is a TV receiver on the receiving terminal side, 931a, 931b, 931n are 6
4QAM modulation circuit reference clock, 941a, 941
b and 941n are packet combining circuits, 942a and 942
b, 942n are null packet generation circuits, 943a, 94
3b and 943n are speed comparison circuits, and the same numbers as in FIG. 1 indicate the same functional blocks.

The modulated signal 90 of the BS digital broadcast received by the outdoor unit (not shown) is transmitted to the BS digital receiver 91a or 9 in the transmitter 1 by a cable.
Digital demodulation / decoding circuit 901a or 90m within 1m
The data separation circuit 92a or 92m is transmitted by the TMCC decoding circuit 902a or 902m from a plurality of transport streams transmitted by BS digital broadcasting which have been subjected to digital channel demodulation, error correction, energy spreading, and other transmission path decoding processing of the channel selected in 1m. Then, the selected single transport stream is separated and added to the multiplexing circuit 94a, 94b or 94n. In the speed comparison circuit 943a, 943b or 943n, 64
The transmission rate information of the reference clock 931a, 931b or 931n of the 64QAM modulation circuit based on the transmission rate of the QAM modulation circuit 93a, 93b or 93n and the packet synthesis circuit 941a, 941b or 941n
Then, the speed information is compared with the speed information to obtain a speed error signal, and a null packet is transmitted from the null packet generation circuit 942a, 942b or 942n according to the speed error. With this null packet, the transmission speed from the multiplexing circuit 94a, 94b or 94n can match the transmission speed of the 64QAM modulation circuit 93a, 93b or 93n. 64QAM modulation circuit 9
Multi-level digital modulation of 64QAM is performed by 3a, 93b or 93n.

The receiving device 2 receives a plurality of digitally modulated waves transmitted to the transmission path 3 as input, and outputs a plurality of frequency selecting circuits 2 from the plurality of digitally modulated waves.
1a and 21b, a required modulated wave is selected, and the selected 64QAM modulated wave is converted to a 64QAM demodulation circuit 92.
1a and 921b, and demodulate in error correction circuits 922a and 922b.
The digital data subjected to the error correction in 22b is separated by the data separation / combination circuit 923 into null packets combined by the transmission device, and combined into digital data to return to the transmitted digital data in a single transport stream format. Digital data in a single transport stream format is input to the TS packet separation circuit 924,
The video and audio packets are separated from each other, the video packet data is decoded by an MPEG video decoder 925, and the audio packets are decoded by an MPEG audio decoder 92.
The video signal and the audio signal are obtained by decoding at step 6,
This is input to the TV receiver 927.

In the present embodiment, digital data transmitted by BS digital broadcasting from the BS digital receiver 91a in the transmission device 1 is transmitted in the form of a transport stream,
5 per second with one transponder with 4.5 MHz bandwidth
2.17 Mbit transmission capacity, but CATV's 6
The transmission capacity at 64 QAM in the MHz band is 29.16 per second.
Since the transmission capacity is 2 megabits, the total transmission capacity is 58.324 per second using two waves of 64 QAM in a 6 MHz band.
Synchronous transmission was realized by multiplexing the difference in transmission capacity as a megabit by multiplexing null packets. Therefore, there is an advantage that even if a service of 29.162 megabits per second or more is implemented with digital data of one transport stream in the future BS digital broadcasting, CATV transmission is possible.

Also, in this embodiment, since transmission is performed in a plurality of 6 MHz bands at 64 QAM, it is assumed that leakage of the local oscillator of the television receiver returns to the CATV transmission line during the current analog terrestrial television retransmission in cable television. Is not affected, and the bandwidth of the transmission path can be fully utilized.

FIG. 10 is a block diagram showing a transmitting apparatus and a receiving apparatus for frequency multiplex data transmission according to one embodiment of the present invention, and shows a configuration example in the case of transmitting a BS digital broadcast by CATV. In FIG. 10, 101a, 101b, 10
1n is a 64QAM modulation circuit, 1011a, 1011b,
Reference numeral 1011n denotes a clock synchronization circuit, and the same numbers as those in FIG. 6 or FIG. 9 indicate the same functional blocks.

In this embodiment, the transmitting apparatus is for transmitting BS digital broadcasting in frequency multiplexed data in synchronization with the telephone public line network 6, and according to a signal from the telephone public line input terminal 61, the telephone public line network. A reference signal is generated from the synchronization circuit 62 by the clock control circuit 63, and a clock synchronized with the reference signal from the clock control circuit 63 by the clock synchronization circuit 1011a, 1011b or 1011n in the 64QAM modulation circuit 101a, 101b or 101n. Generated 64QAM modulation circuits 101a, 101b
Alternatively, it is operated as a reference clock serving as a reference such as a transmission speed of 101n. In accordance with this reference clock, the speed comparison circuit 943a, 943b or 943n causes the null packet generation circuit 942a, 942b or 942n.
To send a null packet from the packet synthesizing circuit 9
Control the speed from 41a, 941b or 941n.

As a result, in this embodiment, transmission can be performed based on the reference oscillation frequency synchronized with an integral multiple of 8 kHz, which is the synchronous clock frequency of the telephone public line network. It is possible to provide a transmitting device and a receiving device for large-capacity digital data transmission in which communication can be integrated. The transmission rate of BS digital broadcasting is 57.72 Mbit / s, which is 7215 times 8 kHz, and CA
TV transmission speed of 31.644 Mbit / s 64
63.288 Mbit / sec using two waves of QAM is 8
Since the frequency is 7911 times the kHz, the synchronous clock frequency of the telephone public line network of 8 kHz and BS digital broadcasting or CAT
The transmission speed of V transmission can be synchronized.

FIG. 11 is a block diagram showing a transmitting apparatus and a receiving apparatus for frequency multiplex data transmission according to an embodiment of the present invention, and shows a configuration example in the case of transmitting a BS digital broadcast by CATV. In FIG. 11, reference numerals 111a and 111b denote TSs.
MF addition multiplexing circuit, 112 is a TSMF decoding circuit, 11
3 is a TS separation circuit, 1111a and 1111b are packet synthesis circuits, 1112a and 1112b are null packet generation circuits, 1113a and 1113b are speed comparison circuits, 111
Reference numerals 4a and 1114b denote TSMF generating circuits, and the same numbers as in FIG. 9 indicate the same functional blocks.

In the present embodiment, the start flag information for emergency alert broadcast transmitted by BS digital
The transmission to the receiving device by the TSMF addition multiplexing circuits 111a and 111b having the F generation circuits 1114a and 1114b has been added to the embodiment shown in FIG.

The modulated signal 90 of the BS digital broadcast is transmitted to the BS digital receiver 91a in the transmitter 1 by a cable.
A plurality of transport streams transmitted by BS digital broadcasting, which have been subjected to digital demodulation, error correction, energy spreading, and other transmission path decoding processes of the channel selected by the digital demodulation / decoding circuit 901a, are transmitted by the TMCC decoding circuit 902. The data separation circuit 92a separates a plurality of (two in the figure) selected transport streams, adds them to the packet synthesis circuits 1111a and 1111b, and sends them by BS digital broadcast obtained by the TMCC decoding circuit 902a. TSM for coming information
The signal is sent to the F generation circuits 1114a and 1114b. There is a start flag for emergency alert broadcasting that activates a receiver for BS digital broadcast at the time of emergency alert broadcast, which is information transmitted by BS digital broadcast, and the information is transmitted as a TMCC signal for BS digital broadcast. Therefore, the TMCC signal is decoded by the TMCC decoding circuit 902a,
The signal is sent to the F generation circuits 1114a and 1114b. Also,
In BS digital broadcasting, there is hierarchical transmission using a characteristic that can be transmitted by combining a plurality of modulation schemes in order to reduce service interruption due to rainfall. Examples of layered transmission include trellis 8-phase PSK (TC8PSK) for normal television broadcasting (high hierarchy) and QPSK or BPSK that can be received even at a low CN ratio. It is shown that the switching between the higher layer and the lower layer using the layer transmission descriptor is performed based on a signal that detects a decrease in the CN ratio or an increase in the error rate. This information is
Since it is known only where the S digital broadcast is being received, the BSMF broadcast receiving conditions obtained from the BS digital receiver 91a are transmitted to the TSMF generating circuits 1114a and 1114a in order to send the information to the CATV receiving terminal device.
14b. As shown in FIG.
Multi-level digital modulation is performed by the 4QAM modulation circuits 93a and 93b, but TSMF is applied to 2TS from the data separation circuit 92a.
The TSMF information from the generating circuits 1114a and 1114b is combined by the packet combining circuits 1111a and 1111b, and the null packets from the null packet generating circuits 1112a and 1112b are transmitted by the speed comparing circuits 1113a and 1113b. Control the speed of the car.

Note that the TSMF generation circuits 1114a and 1114a
For an example of TSMF information of the 14b, see the Technical Report of the Institute of Image Information and Television Engineers (July 27, 1999) (v
ol. 23, no. 48), pages 13 to 18, "Multi-MPEG-TS Cable TV Transmission Experiment".

The receiving device 2 receives a plurality of digitally modulated waves transmitted to the transmission path 3 as input and outputs a plurality of frequency selecting circuits 2 from the plurality of digitally modulated waves.
1a and 21b, a required modulated wave is selected, and the selected 64QAM modulated wave is converted to a 64QAM demodulation circuit 92.
1a and 921b, and demodulate in error correction circuits 922a and 922b.
The digital data subjected to the error correction in 22b is separated by the data separation / combination circuit 923 into null packets combined by the transmission device, and combined into digital data to be returned to a plurality of transport stream format digital data transmitted. The TSMF decoding circuit 112 decodes start flag information for emergency alert broadcasting sent by BS digital broadcasting from digital data in a plurality of transport stream formats, obtains TS separation information, and obtains TS separation information by the TS separation circuit 113. The desired digital data in the single transport stream format is separated from the digital data in the transport stream format. Then, TS
The video packet data is input to the packet separation circuit 924 to separate video and audio packets.
The audio packet is decoded by the PEG video decoder 925, and the audio packet is decoded by the MPEG audio decoder 926 to obtain a video signal and an audio signal.
7 is input.

In the present embodiment, digital data in a plurality of transport stream formats can be transmitted, so that null packets in transmission data can be reduced, and data transmission efficiency can be increased.

In this embodiment, since TSMF information can be multiplexed and transmitted, there is an advantage that information such as start flag information for emergency alert broadcasting transmitted by BS digital broadcasting can be transmitted by CATV.

In the present embodiment, since a plurality of digital data in the form of a transport stream can be transmitted, other digital data for an Internet connection service or the like can be multiplex-transmitted.

FIG. 12 is a diagram showing an example of the configuration of the data separation circuit 12 according to FIG. 1 of the present invention, FIG. 13 is a diagram showing an example of a signal train such as an input / output or an internal data train, and FIG. The configuration example of the data synthesis circuit 24 according to FIG.
FIG. 15 is a diagram showing an example of a signal sequence such as an input / output or an internal data sequence. 1201, 1203, 1204
Is a latch circuit, 1202 is a clock control circuit, and 1
301, 1303, 1306, 1307 are data strings, 1
Reference numerals 302, 1304, and 1305 denote clock signals.
The same numbers as in the example of the signal train in FIG. Also, 1401,
1402 and 1405 are latch circuits; 1403 is a clock and other control circuit; 1404 is a selector circuit;
1, 1503, 1506, 1507 are data strings, 150
Reference numerals 2, 1504, and 1508 denote clock signals, and 1505 denotes a selector control signal, which are given the same numbers as in the example of the signal sequence in FIG.

The data separation circuit of FIG. 12 shows an example of one input and two outputs, and the data synthesis circuit of FIG. 14 is an example of returning the separated output to the original data string. Also, the latch circuit 120
1, 1203, 1204, 1401, 1402, 140
The phase relationship between the data of No. 5 and the clock signal is shown on the assumption that the data is latched (acquired) at the rising edge of the clock signal and output with almost the same phase relationship.

The data string 1301 of digital data input to the data separation circuit 12 is latched at the rising edge of the clock signal 1302 in the latch circuit 1201 to become a data string 1303. In the clock control circuit 1202,
A clock signal 1302 is input, and two clock signals 1304 and 1305 having phases different from each other at twice the cycle are output. When the data string 1303, which is the output of the latch circuit 1201, is latched at the rise of the clock signal, the output of the latch circuit 1203 outputs the data "A", "C", and "O" in which the data string 1303 exists at the rise of the clock signal 1304. Data string 130 indicated by...
6 is obtained, and the output of the latch circuit 1204 is the data string 1303 represented by the data "a", "d", "f", etc. in the data string 1303 at the rising edge of the clock signal 1305.
7 is obtained. As a result, the data of the data string 1301 can be separated into two outputs of the data string 1306 and the data string 1307 every other data.

On the other hand, in the data synthesizing circuit 24, the two input data strings are latched by the latch circuits 1401 and 1402 at the rising edges of the clock signal 1502 and the clock signal 1504 to become the data string 1501 and the data string 1503. The clock control circuit 1403 receives the clock signal 1502 and the clock signal 1504 and outputs a selector control signal 1505 having the same cycle and a clock signal 1508 having a half cycle. The data sequence 1501 and the data sequence 1503, which are two input data sequences of the selector circuit 1404, are switched by the selector control signal 1505 to become the data sequence 1506.
506 is latched at the rise of the clock signal 1508 to become a data string 1507. As a result, a data sequence 1301 of the original digital data is obtained.

FIG. 16 is a diagram showing an example of the configuration of the data separation circuit 12 according to the present invention shown in FIG. 1, FIG. 17 is a diagram showing an example of a signal train such as input / output or an internal data train, and FIG. The configuration example of the data synthesis circuit 24 according to FIG.
FIG. 19 is a diagram showing an example of a signal sequence such as an input / output or an internal data sequence. 1601 is a memory control circuit, 1
Reference numerals 602 and 1603 denote memory circuits.
05 and 1708 are data strings, 1702, 1703 and 17
Reference numerals 04, 1706, and 1707 denote clock signals, which have the same numbers as in the example of the signal sequence in FIG. 1801 is a memory circuit, 1802 is a memory control circuit, and 190
1, 1903, 1911 are data strings, 1902, 190
4, 1905, 1906, 1907 are clock signals,
The same numbers as in the example of the signal sequence in FIG. 19 are given.

The data separation circuit of FIG. 16 shows an example of one input and two outputs, and the data synthesis circuit of FIG. 18 is an example of returning the separated output to the original data string. Also, the memory circuit 160
Reference numerals 2, 1603, and 1801 indicate that data is stored at the falling edge of the storage clock signal when data is stored, and output at the rising edge of the output clock signal when data is output.

Memory control circuit 1 in data separation circuit 12
Reference numeral 601 denotes a clock signal 1703 which is two types of clock signals for storage, in which a clock signal 1702 is inputted and the number of clocks having the period is generated intermittently at certain intervals.
A clock signal 1704 and a clock signal 1707, which are two types of output clock signals having different phases at twice the period, are output together with the clock signal 1706 and the clock signal 1706. The data string 1701 of the input digital data is applied to the memory circuit 1602 and the memory circuit 1603, and the data “A”, “I”, “U”, “E”, and “O” are supplied to the memory circuit 1602 at the falling edge of the clock signal 1703. Is stored, and a data sequence 1705 is output at the rise of the clock signal 1704.
Also, at the falling edge of the clock signal 1706, the memory circuit 16
03, the data “f”, “g”, “k”, “k”, and “k” are stored, and a data sequence 1708 is output at the rise of the clock signal 1707. As a result, the data of the data sequence 1701 is obtained by being separated into two outputs of a data sequence 1705 and a data sequence 1708 for every five data.

On the other hand, in the data synthesizing circuit 24, two input data strings are added to the memory circuit 1801, and each data string is stored in another area of the memory circuit 1801. Further, the clock signal 1902 and the clock signal 1904 are input to the memory control circuit 1802, and two types of clock signals having substantially the same phase and the same cycle as the clock signals are output as clock signals for storage of the memory circuit 1801. A clock signal 1907 having a half cycle and two types of clock signals 1905 and 1906 which generate a number of clocks intermittently at a certain interval are generated for output from the memory circuit 1801. Two input data strings, that is, a data string 1901 and a data string 1902 are applied to the memory circuit 1801, and the memory control circuit 1802 sends the data "1" to the memory circuit 1801 at the falling edge of the clock signal having substantially the same phase as the clock signal 1902 and the clock signal 1904. A, I, U, D
"O" ... and data "K""K""K""K""K"
... is stored in another area. The data stored in the memory circuit 1801 is called by the clock signal 1905 from the area where the data string 1901 is stored, and the clock signal 1906 is called from the area where the data string 1903 is stored.
908 are obtained. As a result, a data string 1701 of the original digital data is obtained.

FIG. 20 is a diagram showing an example of the configuration of the data separation circuit 12 according to FIG. 5 of the present invention, and FIG. 21 is a diagram showing an example of the input / output or signal trains such as internal and external data trains.
FIG. 22 is a diagram showing an example of the configuration of the header separation data synthesizing circuit 52 according to FIG. 5 of the present invention, and FIG. 23 is a diagram showing an example of a signal sequence such as input / output or internal data sequence. These figures explain an example in which null data and a header shown in FIG. 5 of the present invention are inserted. 2102, 2103, 210
Numeral 4 denotes a data sequence, 2101 denotes a clock signal, and has the same numbers as those of the example of the signal sequence in FIG. Also, 2201, 22
02 is a header detection header & null data deletion circuit,
2301, 2303, 2305, 2306, 2311 are data strings, 2302, 2304, 2307, 2308,
Reference numerals 2309, 2310, and 2312 denote clock signals.
The same numbers as in the example of the signal sequence No. 3 are given. 5, 16, 17, 18, and 19 indicate the same functional block or an example of a signal sequence such as a data sequence.

The data separation circuit of FIG. 20 shows an example of one input and two outputs, and the data synthesis circuit of FIG. 22 is an example of returning the separated output to the original data string. The difference from the examples of FIGS. 16 and 18 is that a header is provided at the head of the data string as shown in FIG. 5 and that the transmission speed is matched by inserting null data. "H" indicates null data, and "Null" indicates a case of one data each.

In FIG. 20, as in FIG.
A data string 2102 is output to the output of 602 at the rising edge of the clock signal 2101. In synchronization with the clock signal 2101, the data "A", "I", "U", "E", "O" and the next data "S" are output. It is output with the space between "", "S", "S", "S", and "S" open. The data is added to the header generation circuit 5
The header from 14a and the null data from the null data generating circuit 512a are combined by the combining circuit 511a and output as a data string 2103. The data string 210
The clock signal of No. 3 is indicated by 2103 clk. Similarly, the data “f” and “g” stored in the memory circuit 1603
As for “K”, “K”, and “K”, the header from the header generation circuit 514b and the null data from the null data generation circuit 512b are synthesized by the synthesis circuit 511b and output as a data string 2104.

On the other hand, in the data synthesizing circuit 52, the header detection header & null data deleting circuit 2201 outputs the data string 23.
Data string 2 with header and null data removed from 01
305 and header detection header & null data deletion circuit 220
The data string 2306 obtained by removing the header and null data from the data string 2303 in step 2 is added to the memory circuit 1801. In the memory control circuit 1802, two kinds of clock signals 2307 and 2308 generated intermittently are generated.
Are output for storage in the memory circuit 1801 and two kinds of clock signals 2309 and 2310 which are generated intermittently are output for the storage contents of the memory circuit 1801. Two input data strings, a data string 2305 and a data string 2306, are applied to the memory circuit 1801, and the data "A", "B", and "C" are sent from the memory control circuit 1802 to the memory circuit 1801 at the falling edge of the clock signal 2307 and the clock signal 2308. "E""O" and data "Ka""Ki"
“K”, “K”, and “K” are stored in different areas. The data stored in the memory circuit 1801 is a clock signal 2309.
Is called from the area where the data string 2305 is stored, and the clock signal 2310
The data string 2311 is obtained by calling from the area where 06 is stored. As a result, a data string 1701 of the original digital data is obtained.

17, FIG. 19, FIG. 21, and FIG.
Thus, the same operation can be performed regardless of whether the data described in “A” or the like is 1-bit data or multi-bit data. The multi-bit data indicates 8-bit 1-byte data or data composed of a longer bit number.

FIG. 24 is a diagram showing an example of the configuration of the data separating circuit 92 according to FIG. 9 of the present invention, and FIG. 25 is a diagram showing an example of a signal train such as an input / output or an internal or external data train.
FIG. 26 shows a data separation / combination circuit 92 according to FIG. 9 of the present invention.
FIG. 27 is a diagram showing an example of a signal sequence such as an input / output or an internal data sequence. 2401 is a memory control circuit, 2402 and 2403 are memory circuits,
Reference numerals 2501, 2505, 2506, 2508, and 2509 denote data strings, and reference numerals 2502, 2503, 2504, and 2507 denote clock signals, which have the same numbers as in the signal string example of FIG. Numerals 2601 and 2602 denote null packet detection / deletion circuits, 2603 denotes a memory circuit, and 2604 denotes a memory control circuit. 2701, 2703, 2705, and 270
6, 2712 are data strings, 2702, 2704, 270
Reference numerals 7, 2708, 2709, 2710, and 2711 denote clock signals, which are given the same numbers as in the example of the signal sequence in FIG.
The same numbers as those in FIG. 9 indicate the same functional blocks. The data described in “A”, “A”, “U”, etc. in FIG. 25 or FIG. 27 represent data in units of 188 bytes or 204 bytes including the synchronization byte shown in FIG. The period of existence of the clock signal is represented by being painted out because it cannot be indicated by. These figures show examples in which two null packets are inserted.

In the memory control circuit 2401 in the data separation circuit 92a, a clock signal 2502 is input and intermittently generates a number of clocks at a certain interval at a certain interval.
The clock signal 2503 and the clock signal 2507 which are the clock signals for storage of the two types of memory circuits 2402 and 2403 are the clock signal 2504 and the clock signal 2508 which are the clock signals for output of the two types of memory circuits 2402 and 2403. Is output. The data string 2501 of the input digital data is applied to the memory circuit 2402 and the memory circuit 2403, and the data “A”, “I”, “U”, “E”, and “O” are stored in the memory circuit 2402 by the clock signal 2503. , A data sequence 2505 is output by the clock signal 2504. A transport format null packet from the null packet generation circuit 942a is combined with the data sequence 2505 by the packet combining circuit 941a to output a data sequence 2506. The clock signal of the data string 2506 is 25
Shown at 06clk. Similarly, the data “f” and “g” stored in the memory circuit 2403 by the clock signal 2507
“K”, “K”, and “K” become a data string 2508, and the transport format null packet from the null packet generation circuit 942b is combined by the packet combining circuit 941b to be output as a data string 2509. As a result, the data of the data string 2501 is changed to the data string 2506 and the data string 250
Each of the two outputs 9 is obtained by separating every 5 packets and inserting 2 null packets each.

On the other hand, in data separation / combination circuit 923, null packet detection / deletion circuit 2601 removes null packets from data sequence 2701, and null packet detection / deletion circuit 2602 removes null packets from data sequence 2703. The data sequence 2706 is applied to the memory circuit 2603. The clock signal 2702 and the clock signal 2703 are input to the memory control circuit 2604, and two types of clock signals 2707 generated intermittently are input.
And a clock signal 2708 are output for storage in the memory circuit 2603, and two kinds of clock signals 2709 and 2710 generated intermittently are
Occurs for output of the storage contents of 03. Data sequence 2705
And a data string 2706 are applied to the memory circuit 2603, and the clock signal 2707 and the clock signal 2708 from the memory control circuit 2604 store the data string 2705 and the data string 2706 in another area in the memory circuit 2603. . The data stored in the memory circuit 2603 is converted into a data string 2705 by the clock signal 2709.
Is called from the area where the clock signal 2 is stored.
The data string 2712 is obtained by being called from the area where the data string 2706 is stored according to 710. As a result, the data sequence 250 of the original digital data
1 is obtained.

[0086]

According to the present invention, digital data is separated and frequency-multiplexed by a plurality of digital modulating means in broadcasting or communication using a radio transmission line such as a satellite or terrestrial transmission line or a cable transmission line such as a cable television. To the transmission path, and on the receiving side, the original data can be obtained by combining a plurality of digital data obtained by the plurality of selective demodulation means, so that large-capacity digital data can be transmitted effectively. It becomes possible.

Further, according to the present invention, data can be transmitted in the form of a transport stream in which digital data such as images compressed by MPeg 2 are multiplexed, so that future digital broadcasting such as three-dimensional video will be possible. The required large volume of digital data can be transmitted effectively.

Further, since transmission can be performed based on a reference oscillation frequency synchronized with an integral multiple of 8 kHz which is a synchronous clock frequency of a telephone public line network, matching with communication is also possible.
It is possible to provide a transmitting device and a receiving device for large-capacity digital data transmission capable of integrating broadcasting and communication.

Further, the multi-level modulation of the multi-level modulation is carried out by using digital modulation means which makes the multi-level modulation variable. Can be selected and transmitted, so that the performance of the transmission path can be maximized for large-capacity digital data.

Further, when the BS digital broadcast according to the present invention is transmitted to a cable television, a plurality of 6 MHz bands of 64 QAM can be transmitted. Therefore, even if a service of 29.162 Mbit / s or more per second is provided by the BS digital broadcast, the cable television is transmitted. Can be transmitted.

Further, when the BS digital broadcast according to the present invention is transmitted to a cable television, since a plurality of 6 MHz bands are transmitted at 64 QAM, the local portion of the television receiver in the current analog terrestrial television retransmission in the cable television is used. Even if the leakage of the oscillator returns to the CATV transmission line, it is not affected, and the band of the transmission line can be utilized to the maximum.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a transmission device and a reception device for frequency multiplex data transmission according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram of frequency multiplexing on a transmission line according to the present invention.

FIG. 3 is a configuration diagram illustrating a transmitting device and a receiving device for frequency multiplex data transmission according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of a frame configuration of a transport stream according to the present invention.

FIG. 5 is a configuration diagram illustrating a transmission device and a reception device for frequency multiplex data transmission according to an embodiment of the present invention.

FIG. 6 is a configuration diagram illustrating a transmission device and a reception device for frequency multiplex data transmission according to an embodiment of the present invention.

FIG. 7 is a configuration diagram illustrating a transmission device and a reception device for frequency multiplex data transmission according to an embodiment of the present invention.

8 is a conceptual diagram of frequency multiplexing on a transmission line according to FIG. 7 of the present invention.

FIG. 9 is a configuration diagram illustrating a transmission device and a reception device for frequency multiplex data transmission according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a configuration example when an S digital broadcast is transmitted by CATV.

FIG. 10 is a configuration diagram showing a transmission device and a reception device for frequency multiplex data transmission according to an embodiment of the present invention;
It is a figure which shows the example of a structure at the time of CATV transmission of BS digital broadcasting.

FIG. 11 is a configuration diagram showing a transmission device and a reception device for frequency multiplex data transmission according to an embodiment of the present invention;
It is a figure which shows the example of a structure at the time of CATV transmission of BS digital broadcasting.

FIG. 12 is a diagram showing a configuration example of a data separation circuit according to FIG. 1 of the present invention.

13 is a diagram showing an example of a signal sequence such as an input / output or an internal data sequence according to FIG. 12 of the present invention.

FIG. 14 is a diagram showing a configuration example of a data synthesis circuit according to FIG. 1 of the present invention.

FIG. 15 is a diagram showing an example of a signal sequence such as an input / output or an internal data sequence according to FIG. 14 of the present invention.

FIG. 16 is a diagram showing a configuration example of a data separation circuit according to FIG. 1 of the present invention.

17 is a diagram showing an example of a signal sequence such as an input / output or an internal data sequence according to FIG. 16 of the present invention.

FIG. 18 is a diagram showing a configuration example of a data synthesis circuit according to FIG. 1 of the present invention.

19 is a diagram showing an example of a signal sequence such as an input / output or an internal data sequence according to FIG. 18 of the present invention.

20 is a diagram showing a configuration example of a data separation circuit according to FIG. 5 of the present invention.

FIG. 21 is a diagram showing an example of a signal sequence such as an input / output or an internal data sequence according to FIG. 20 of the present invention.

FIG. 22 is a diagram showing a configuration example of a data synthesis circuit according to FIG. 5 of the present invention.

FIG. 23 is a diagram showing an example of a signal sequence such as an input / output or an internal data sequence according to FIG. 22 of the present invention.

24 is a diagram showing a configuration example of a data separation circuit according to FIG. 9 of the present invention.

25 is a diagram showing an example of a signal sequence such as an input / output or an internal data sequence according to FIG. 24 of the present invention.

26 is a diagram showing a configuration example of a data synthesis circuit according to FIG. 9 of the present invention.

27 is a diagram showing an example of a signal sequence such as an input / output or an internal data sequence according to FIG. 26 of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transmission device, 2 ... Reception device, 3 ... Transmission line, 6 ... Public telephone network, 11 ... Data input terminal, 12 ... Data separation circuit, 13a, 13b, 13n, 33a, 33b, 33
n, 64a, 64b, 64n ... digital modulation circuit, 14
... frequency multiplexing circuits, 21a, 21b, 21n ... frequency selection circuits, 22a, 22b, 22n ... digital demodulation circuits,
24 data synthesis circuit, 25 data output terminal, 31
a, 31b, 31n: multiplexing circuit, 34: data separating / combining circuit, 51a, 51b, 51n: header multiplexing circuit,
52: header separation data synthesis circuit, 61: telephone public network input terminal, 62: telephone public network synchronization circuit, 63 ...
Clock control circuit, 71a, 71b, 71n: variable multi-level digital modulation circuit, 72a, 72b, 72n: variable multi-level digital demodulation circuit, 90: modulation signal of BS digital broadcasting, 91a, 91m: BS digital receiver, 92a, 9
2m data separation circuit, 93a, 93m, 101a, 1
01b, 101n ... 64 QAM modulation circuit, 94a, 94
b, 94n: multiplexing circuit, 111a, 111b: TSM
F addition multiplexing circuit, 112... TSMF decoding circuit, 113
... TS separation circuit, 311a, 311b, 311n, 51
1a, 511b, 511n ... combining circuit, 312a, 31
2b, 312n ... null data generation circuit, 313a, 31
3b, 313n: speed comparison circuit, 331a, 331b,
331n: Reference clock of digital modulation circuit, 512
a, 512b, 512n... null data generation circuit, 513
a, 513b, 513n: speed comparison circuit, 514a, 5
14b, 514n... Header generation circuit, 641a, 641
b, 641n: clock synchronization circuit, 901: digital demodulation / decoding circuit, 902: TMCC decoding circuit, 921 ...
64QAM demodulation circuit, 922 ... error correction circuit, 923 ...
Data separation / combination circuit, 924 ... TS packet separation circuit,
925: MPEG video decoder circuit, 926: audio decoder circuit, 927: TV receiver on the receiving terminal side,
931a, 931b, 931n... Reference clock of 64QAM modulation circuit, 941a, 941b, 941n... Packet synthesis circuit, 942a, 942b, 942n... Null packet generation circuit, 943a, 943b, 943n... Speed comparison circuit, 1011a, 1011b, 1011n. Clock synchronization circuit, 1111a, 1111b ... combination circuit, 1
112a, 1112b ... null packet generation circuit, 111
3a, 1113b: speed comparison circuit, 1114a, 111
4b ... TSMF generation circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04L 12/18 H04L 11/18 27/34 27/00 E (72) Inventor Hiroyuki Mizukami Totsuka, Yokohama-shi, Kanagawa 292, Yoshida-cho, Ward Hitachi, Ltd. Digital Media Development Division (72) Inventor Satoshi Yamashita 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Digital Media System Division, Hitachi, Ltd. F-term (reference) 5K004 AA08 JA01 JA09 JE03 JG01 5K022 AA07 AA12 AA22 DD13 DD17 DD19 DD22 DD32 5K028 AA11 BB04 CC05 DD01 DD02 EE03 EE05 EE08 KK03 KK32 MM05 MM16 NN23 NN51 RR03 TT02 5K030 GA00 HB01 H0102B01 JB01H01B01 HB02 H01L01 DD02 EE04 GG45 GG46 LL01 MM02 MM12 MM18

Claims (14)

[Claims] An apparatus for frequency-multiplexed data transmission for frequency-multiplexing and transmitting digital data in broadcast or communication using a wireless transmission line or a wired transmission line, wherein the digital data is separated into a plurality of digital data. Separating means; a plurality of digital modulating means for digitally modulating a plurality of digital data outputs of the separating means by a modulation method of a transmission method of the wireless transmission path or the wired transmission path; and outputs of the plurality of digital modulation means And a signal synthesizing means for frequency-multiplexing a plurality of modulated waves including: and transmitting the modulated waves to a transmission path. 2. A frequency multiplexing data transmission transmitting apparatus for frequency-multiplexing and transmitting digital data in broadcasting or communication using a wireless transmission line or a wired transmission line, wherein the digital data is separated into a plurality of digital data. Demultiplexing means for multiplexing null digital data for matching and outputting a plurality of transport stream format digital data to match the digital transmission data rate of the transmission system of the wireless transmission line or the wired transmission line, A plurality of digital modulation means for digitally modulating a plurality of digital data outputs of the separation / multiplexing means by a modulation method of the transmission method of the wireless transmission path or the wired transmission path; and an output of the plurality of digital modulation means. Signal synthesizing means for frequency-multiplexing a plurality of modulated waves and transmitting the modulated waves to a transmission path. Wavenumber multiplex data transmission of the transmitter. 3. A frequency multiplexing data transmission transmitting apparatus for frequency-multiplexing and transmitting digital data in broadcast or communication using a wireless transmission line or a wired transmission line, wherein the digital data is separated into a plurality of digital data. A packet header is multiplexed into digital data in a transport stream format, and null digital data for matching is multiplexed to match a digital transmission data rate of the transmission system of the wireless transmission line or the wired transmission line. Separating header multiplexing means for outputting digital data in a transport stream format; and digitally modulating a plurality of digital data outputs of the separating header multiplexing means by a modulation method of the transmission method of the wireless transmission line or the wired transmission line. A plurality of digital modulation means; Transmission device of a frequency multiplex data transmission, characterized in that a signal synthesizing means for delivering to the transmission line by frequency multiplexing a plurality of modulated wave including a force. 4. The system according to claim 1, wherein a reference clock frequency of a digital transmission data rate of said plurality of digital modulating means is synchronized with a network clock frequency of another broadcasting system or communication system. Transmitter for frequency multiplexed data transmission. 5. The wireless transmission line or the wired transmission system according to claim 1, wherein when the digital modulation method of the plurality of digital modulation means is multi-level modulation, the multi-level is made variable. A transmission apparatus for frequency multiplex data transmission, wherein a multilevel level is selected and transmitted according to the signal quality of a frequency multiplexed and transmitted on a channel. 6. The method of claim 1, 2, 3, 4, or 5,
The wireless transmission path or the wired transmission path is a cable-based cable television transmission, and the plurality of digital modulating means are transmitted by digital modulation of multi-level QAM such as 64-value, so that digital transmission such as satellite or terrestrial transmission is possible. A transmission apparatus for frequency multiplexed data transmission, wherein digital data in a transport stream format is selected from a broadcast and transmitted according to a digital transmission data rate of a cable television. 7. The digital data of a plurality of digital data outputs of said separation header multiplexing means according to claim 3, 4 or 5, wherein said wireless transmission line or said wired transmission line is a cable cable television transmission. Is composed of a plurality of transport stream format digital data and a header for separating the plurality of transport stream format digital data on the receiving side and transmitting the data. A transmission apparatus for frequency multiplex data transmission, wherein digital data is selected and transmitted according to a digital transmission data rate of a cable television. 8. A frequency multiplexing data transmission receiving apparatus for frequency-multiplexing and transmitting digital data in broadcast or communication using a wireless transmission line or a wired transmission line, wherein the wireless transmission line or the wired transmission line is provided. A desired plurality of digital modulated waves are selected from a plurality of modulated waves transmitted in a frequency multiplexed manner, and digital demodulation matching the digital modulation method of the transmission method of the wireless transmission path or the wired transmission path is performed. Frequency multiplexing data transmission, comprising: a plurality of selective demodulating means for performing; and digital data combining means for combining a plurality of digital data output from the plurality of selective demodulating means and returning to digital data before transmission. Receiving device. 9. A frequency multiplexing data transmission receiving apparatus for frequency-multiplexing and transmitting digital data in broadcast or communication using a wireless transmission line or a wired transmission line, wherein the wireless transmission line or the wired transmission line is provided. A desired plurality of digital modulated waves are selected from a plurality of modulated waves transmitted in a frequency multiplexed manner, and digital demodulation matching the digital modulation method of the transmission method of the wireless transmission path or the wired transmission path is performed. A plurality of selective demodulating means for performing, and matching from a plurality of transport stream format digital data output from the plurality of selective demodulating means to a digital transmission data rate of a transmission system of the wireless transmission line or the wired transmission line. A plurality of digital data separating means for removing null digital data for use, and an output of the plurality of digital data separating means. That a plurality of receiving devices in the frequency multiplex data transmission, characterized in that a digital data combining means for returning the digital data before synthesis to transmit digital data. 10. A frequency multiplexing data transmission receiving apparatus for frequency-multiplexing and transmitting digital data in broadcasting or communication using a wireless transmission line or a wired transmission line, wherein the wireless transmission line or the wired transmission line is provided. A desired plurality of digital modulated waves are selected from a plurality of modulated waves transmitted in a frequency multiplexed manner, and digital demodulation matching the digital modulation method of the transmission method of the wireless transmission path or the wired transmission path is performed. A plurality of selective demodulating means for performing, and matching from a plurality of transport stream format digital data output from the plurality of selective demodulating means to a digital transmission data rate of a transmission system of the wireless transmission line or the wired transmission line. Multiplexed packet headers into null digital data for transport and digital data in transport stream format. A plurality of data header separating means for separating the plurality of data headers, and a digital data combining means for combining a plurality of digital data output from the plurality of data header separating means and returning to digital data before transmission. Receiver for multiplex data transmission. 11. The frequency multiplexing method according to claim 8, 9 or 10, wherein a digital demodulation method of said plurality of selective demodulation means is digitally demodulated in accordance with a modulation signal of a signal transmitted as a multi-level variable signal. Receiving device for data transmission. 12. The digital demodulation system according to claim 8, 9, 10 or 11, wherein said wireless transmission line or said wired transmission line is a cable-based cable television transmission, and said plurality of selective demodulation means have a 64-bit digital demodulation system. A digital demodulation according to a multilevel QAM digital modulation signal. 13. The digital data synthesizing unit according to claim 9, 11 or 12, wherein said wireless transmission line or said wired transmission line is a cable cable television transmission, and said digital data synthesizing means is inputted from said plurality of digital data separating means. The received digital data is a plurality of transport stream format digital data, and the plurality of transport format digital data output from the plurality of digital data separating means are combined, and a frequency multiplexing data transmission receiving apparatus is provided. . 14. The method according to claim 10, 11 or 12,
The wireless transmission line or the cable transmission line is a cable cable transmission of a cable system, and the digital data synthesizing unit converts the digital data input from the plurality of data header separation units into a plurality of transport stream format digital data. A plurality of transport stream format digital data constituted by a header for separating the plurality of transport stream format digital data on a receiving side, wherein a plurality of transport formats which are outputs of the plurality of data header separating means. A receiving apparatus for frequency multiplexed data transmission, which combines digital data, and separates and outputs single transport stream format digital data according to the header information and the like.