JP2001185738A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize the switching voltage and the holding voltage of a thyristor used as an electrostatic protecting element, by adjusting the layout of the respective regions of a semiconductor device, and especially, provide an effective structure of the semiconductor device in a microprocess. SOLUTION: In a semiconductor device, a diode portion is formed in the region separated by a selected distance from the region interposed between the anode portion and the cathode portion of a thyristor, and respective activated regions independent of each other are formed in the vicinities of the anode and cathode portions of the thyristor and the diode portion. By altering the layout of the respective regions of the semiconductor device, the resistances among the respective regions are set properly, and thereby, the holding voltage and the switching voltage of the thyristor can be optimized independently of each other, and as a result, a proper protecting element and a proper protecting circuit for preventing the electrostatic breakdowns of transistors formed in a CMOS process are made form-able.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a protection function for protecting a gate oxide film from an excessive voltage and a method of manufacturing the same.

[0002]

2. Description of the Related Art An example is shown in which a P-type silicon substrate is used as a substrate of a semiconductor device, and a diode whose width is defined by polysilicon is used as a trigger element in a low-concentration N-type semiconductor region formed on this substrate (for example, JP-A-9-213
811 and Japanese Patent Application Laid-Open No. 9-293883).
FIG. 1 shows the structure of a conventional semiconductor device and each step of a manufacturing method.
A description will be given with reference to FIGS.

(A) A photoresist is applied to the substrate surface,
The resist at the portion where the element isolation region 2 is formed is removed by patterning, and after the etching, the oxide is buried, and then the CMP method (chemical mechanical polishing) is performed.
A step of forming the element isolation region 2; At this time, the active region where the diode is formed in a later step includes a high-concentration P-type semiconductor which is formed in the low-concentration N-type semiconductor region 3 (see step B) and forms the thyristor anode, and a low-concentration P-type semiconductor. It is formed in a region sandwiched between the high-concentration N-type semiconductor region which is formed in the type semiconductor region 4 (see step B) and forms the cathode portion of the thyristor.

(B) After applying a photoresist and removing the resist in a portion where the low-concentration N-type semiconductor region 3 is to be formed by patterning, low-concentration N-type semiconductor region 3 is ion-implanted at a low concentration. Forming a. (C) After the photoresist is removed, a photoresist is applied again, the resist in the portion where the low-concentration P-type semiconductor region 4 is formed is removed by patterning, and P-type impurities are ion-implanted at a low concentration. Removing the photoresist after forming 4.

(C ′) An oxide film is formed by an oxidation step,
Thereafter, a step of forming the polysilicon portion 5 by a method such as a CVD method (chemical vapor deposition method). That is, first, a photoresist is applied, and the photoresist other than the pattern that defines the distance between the high-concentration N-type impurity region forming the diode by patterning and the high-concentration P-type impurity region is removed, and etching is performed. The photoresist is removed, and a polysilicon portion 5 and an oxide film pattern are formed on the substrate on which the low concentration N-type impurity region 3 is formed.

(D) A first high-concentration N-type semiconductor region 6 (cathode of a thyristor) formed in the low-concentration P-type semiconductor region 4 by applying a photoresist and patterning;
A second high-concentration N-type semiconductor region 7 forming a diode formed in the low-concentration N-type semiconductor region 3 in a region between the thyristor anode portion and the thyristor cathode portion;
First high-concentration P-type semiconductor region 9 formed in step (E)
The resist of the third high-concentration N-type semiconductor region 8 formed at a selected distance from the anode of the thyristor is removed, and N-type impurities are ion-implanted at a high concentration in a direction substantially perpendicular to the substrate surface. To form high-concentration N-type semiconductor regions 6, 7, 8.

(E) After removing the photoresist, a photoresist is applied again, and the first high-concentration P-type semiconductor region 9 formed in the low-concentration N-type semiconductor region by patterning
(Anode of the thyristor), a second high-concentration P-type semiconductor formed over the low-concentration N-type semiconductor region and the low-concentration P-type semiconductor region between the anode of the thyristor and the cathode of the thyristor Region 10, step (D)
The third high-concentration P-type semiconductor region 1 formed in the low-concentration P-type semiconductor region at a selected distance from the first high-concentration N-type semiconductor region 6 (cathode of the thyristor)
Step 1 of removing each resist and performing high-concentration ion implantation of P-type impurities from a direction substantially perpendicular to the substrate surface to form high-concentration P-type semiconductor regions 9, 10, and 11.

(F) After removing the photoresist, a metal film of Ti or the like is formed on the substrate surface by sputtering, and thereafter, the formation of metal silicide in the active region portion and the polysilicon portion by heat treatment and the steps (C) and ( The implanted impurities are activated in D), and thereafter, the first and third high-concentration N-type semiconductor regions 6 and 8 and the first and third high-concentration P-type semiconductor regions 9 and 11 are contacted with each other. And electrically connecting to a power supply, a ground, or an input / output terminal with a metal wiring or the like.

In the structure of the semiconductor device according to the prior art, the substrate has a low concentration of N
A low-concentration P-type semiconductor region, a first high-concentration N-type semiconductor region 6 (cathode of a thyristor), and a low-concentration N-type semiconductor region. 1, a high-concentration P-type semiconductor region 9 (anode portion of the thyristor) is formed, and the low-concentration N region of the region between the anode portion of the thyristor and the cathode portion of the thyristor is formed.
In the semiconductor region, a second high-concentration N-type semiconductor region 7 forming a diode, and a second high-concentration P-type semiconductor region 10 extending over the low-concentration N-type semiconductor region and the low-concentration P-type semiconductor region. Are formed respectively.

Furthermore, the first high-concentration P-type semiconductor region 9
The third high-concentration N-type semiconductor region 8 is located in the low-concentration N-type semiconductor region at a selected distance from the thyristor anode.
Are formed, and a third high-concentration P-type semiconductor region portion 11 is formed in a low-concentration P-type semiconductor region separated by a selected distance from the first high-concentration N-type semiconductor region 6 (cathode portion of the thyristor). I have.

In the structure of a semiconductor device according to the prior art, a power supply, an input / output terminal, a ground terminal and the like are connected.
Only one high-concentration N-type semiconductor region formed in the low-concentration N-type semiconductor region and one high-concentration P-type semiconductor region formed in the low-concentration P-type semiconductor region are formed. The characteristics, that is, the switching voltage (the voltage at which the thyristor is turned on) and the holding voltage (the voltage for maintaining the thyristor in the on state) depend on these arrangements. The above description is for the case of forming on a P-type substrate, but the case of forming on an N-type substrate is completely the same in terms of process.

[0012]

Semiconductor devices formed by a CMOS (complementary MOS) process generally have low resistance to static electricity (the gate oxide film is thin and thus easily broken). In general, a protection circuit for static electricity is formed. A thyristor is often used as an electrostatic protection device for forming such an electrostatic protection circuit.

A thyristor is a semiconductor device including two or more PN junctions, and typically has a PNPN structure. One end of a thyristor is a P-type semiconductor, and the other end is an anode. Is referred to as a cathode. A thyristor generally shows current-voltage characteristics as shown in FIG. When a semiconductor device having such characteristics is used as an electrostatic protection device, the switching voltage needs to be higher than the power supply voltage, and the holding voltage needs to be lower in order to effectively discharge the electrostatic discharge.

FIGS. 12 and 13 show a conventional structure of a thyristor formed using a CMOS process and including a trigger diode for lowering a switching voltage, and FIG. 16 shows an equivalent circuit thereof. Here, Rsn is the resistance between the high-concentration N-type semiconductor provided in the low-concentration N-type semiconductor region and the region between the anode and the cathode of the thyristor,
Rsp is the resistance between the high-concentration P-type semiconductor provided in the low-concentration P-type semiconductor region and the region between the anode and cathode of the thyristor.

In the conventional thyristor, when a voltage equal to or higher than a breakdown voltage is applied in the reverse direction to a trigger diode provided to reduce the switching voltage of the thyristor, a current flows through the diode, and this current is triggered. As a result, the thyristor operates by turning on the bipolar transistor. For this reason, when Rsn and Rsp are reduced, the voltage drop due to the current flowing through Rsn and Rsp is small, so that the potential difference between both ends of the diode increases, and as a result, the switching voltage of the thyristor decreases.

FIG. 17 shows an example of a simulation result. FIG. 17A shows a case where the distance between the anode portion of the thyristor and the third high-concentration N-type semiconductor region formed in the low-concentration N-type semiconductor region is 4 μm, and FIG. This is a case where the distance between the anode portion and the third high-concentration N-type semiconductor region formed in the low-concentration N-type semiconductor region is 1 μm. It can be seen that as the distance is reduced, that is, as the resistance is reduced, both the ON-state resistance value and the switching voltage are reduced. For this reason, in order to reduce the holding voltage in order to apply this device to a process with a smaller oxide film breakdown voltage, the power supply voltage must be changed (lower) accordingly.

One of the main objects of the present invention is to provide a thyristor used as an electrostatic protection element in which the switching voltage and the holding voltage can be optimized by changing the layout, thereby providing a device structure effective in a fine process. .

[0018]

According to the present invention, an N-type and a P-type low-concentration semiconductor region are respectively formed on a semiconductor substrate, and a P-type first thyristor anode portion is formed in the N-type low-concentration semiconductor region. A high-concentration semiconductor region is formed in the P-type low-concentration semiconductor region, and an N-type first high-concentration semiconductor region is formed as a cathode of the thyristor, and further sandwiched between the N-type and P-type first high-concentration semiconductor regions. N-type second
A high-concentration semiconductor region and a P-type second high-concentration semiconductor region, one of which is in the same type of low-concentration semiconductor region, the other is over the N-type and P-type low-concentration semiconductor regions, and A diode portion is formed at a predetermined interval to form a diode portion. The diode portion is separated from the P-type first and N-type second high-concentration semiconductor regions and is placed in the N-type low-concentration semiconductor region. And a fourth high-concentration semiconductor region are respectively formed to electrically connect the N-type third and fourth high-concentration semiconductor regions to the P-type first high-concentration semiconductor region, and The P-type third and fourth high-concentration semiconductor regions are formed in the P-type low-concentration semiconductor region apart from the first and P-type second high-concentration semiconductor regions, respectively, and the P-type third and fourth high-concentration semiconductor regions are formed. And electrically connecting the fourth high-concentration semiconductor region and the N-type first high-concentration semiconductor region. To provide a semiconductor device.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the following steps (A) to (F). (A) A photoresist is applied on a semiconductor substrate, and a portion of the resist for forming an element isolation region is removed by patterning. After etching, an oxide is buried, and then CMP is performed to perform element isolation. Forming a region, (B) applying a photoresist, removing a portion of the photoresist for forming a low-concentration N-type semiconductor region by patterning, ion-implanting N-type impurities at a low concentration; Forming a concentration N-type semiconductor region;
(C) After removing the photoresist, the photoresist is applied again, and by patterning, a portion of the photoresist for forming the low-concentration P-type semiconductor region is removed.
Removing the photoresist after forming a low-concentration P semiconductor region by ion-implanting a low-concentration impurity at a low concentration; (D)
Apply a photoresist and pattern it to a low concentration P
A first high-concentration N-type semiconductor region (cathode portion) formed in the first-type semiconductor region, and a low-concentration N-type semiconductor region or a second portion formed over this region and the low-concentration P-type semiconductor region to form a diode portion. A second high-concentration N-type semiconductor region and a third and fourth high-concentration N formed in a region away from the second high-concentration N-type semiconductor region in the low-concentration N-type semiconductor region.
The photoresist in each region with the mold semiconductor region is removed, and N
Implanting high-concentration impurities into the semiconductor substrate at a high concentration in a direction substantially perpendicular to the semiconductor substrate to form first to fourth high-concentration N-type semiconductor regions; (E) removing the photoresist; A first high-concentration P-type semiconductor region (anode portion) formed by applying a photoresist over the entire surface and patterning the low-concentration N-type semiconductor region apart from the third and fourth high-concentration N-type regions; , The second high-concentration semiconductor region extending over the P-type and N-type low-concentration semiconductor regions or the P-type low-concentration region at a predetermined distance from the second high-concentration N-type semiconductor region. Photoresist in respective regions of a high-concentration P-type semiconductor region and third and fourth high-concentration P-type semiconductor regions formed in the low-concentration P-type semiconductor region apart from the first high-concentration N-type semiconductor region To remove
A step of performing high-concentration ion implantation of a P-type impurity in a direction substantially perpendicular to the substrate surface to form first to fourth high-concentration P-type semiconductor regions, and (F) removing the photoresist Electrically connecting the first, third, and fourth high-concentration N-type semiconductor regions, and electrically connecting the first, third, and fourth high-concentration P-type semiconductor regions.

That is, according to the present invention, a trigger diode formed for the purpose of lowering the switching voltage of a thyristor is formed in a low-concentration N-type semiconductor region.
In addition, the distance between the high-concentration N-type semiconductor forming the diode portion and the high-concentration P-type semiconductor is defined by the polysilicon portion formed on the N-type semiconductor region. In the case where the area is defined by the element isolation region, the step of forming the polysilicon portion is unnecessary. Further, as another means, when a trigger diode is formed in a low-concentration P-type semiconductor region, it is possible only by changing the patterning of a resist for forming each impurity-implanted region.
According to still another aspect, the present invention provides an electrostatic protection circuit including one or more of the above-described semiconductor devices as an electrostatic protection element.

[0021]

According to the present invention, in a thyristor formed using a CMOS process, a diode formed for the purpose of controlling a switching voltage is selected from a region sandwiched between an anode and a cathode of the thyristor. It is formed in a remote area, and in the vicinity of the anode and cathode of the thyristor and the diode,
An independent activation region is provided. Thus, the switching voltage and the holding voltage can be changed by changing the layout. These operations will be described with reference to FIG. 1, FIG. 2, FIG. 3, and FIG.

FIG. 1 is a layout view of a semiconductor device according to the present invention viewed from a direction perpendicular to a substrate surface.
FIG. 2 is a sectional view taken along AA ′ and BB ′ shown in FIG. 1. FIG. 9 is an equivalent circuit diagram of the semiconductor device of FIG. 1, and each of the resistors Rsn1 to Rsn3, Rsp1 to Rsp3 shown here.
Are arranged and formed as shown in FIGS. However, Rsn3 and Rsp3 are not only in the cross section of FIG.
And the diffusion resistance between BB ′. Referring to FIG. 9, when Rsn2 and Rsp2 are reduced, the voltage drop between Rsn2 and Rsp2 is reduced, the potential difference between both ends of the diode is increased, and the switching voltage is reduced.

However, once the current starts flowing, Rs
The thyristor is turned on because the potential difference between the base region and the emitter of the bipolar transistor, which is connected via n3 and Rsp3, also increases. The on-state voltage is determined solely by the on-resistance of the bipolar transistor and Rsn1 and Rsp1. From this,
By appropriately setting each resistance, the switching voltage and the holding voltage of the thyristor can be set independently.

A thyristor trigger diode is formed in a low-concentration N-type semiconductor, and the distance between a high-concentration N-type semiconductor region and a high-concentration P-type semiconductor region forming a diode is defined by an element isolation region. It can be formed. Also,
A thyristor trigger diode is formed in the low-concentration P-type semiconductor, and the distance between the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region forming the diode can be formed as defined by the polysilicon portion. is there. Further, a thyristor trigger diode is formed in the low-concentration P-type semiconductor, and the distance between the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region forming the diode is formed so as to be defined by the element isolation region. It is possible.

By appropriately setting the respective resistors Rsn1 to Rsn3 and Rsp1 to Rsp3, the switching voltage and the holding voltage of the thyristor can be set independently.
This is a step included in the process of forming a normal CMOS transistor, and does not require an additional step.

[0026]

Here, embodiments of the present invention will be described.
In the case where a trigger diode of a thyristor is formed using a polysilicon portion in a low-concentration N-type semiconductor region,
FIG. 7 shows a structure of a semiconductor device according to the present invention and a method of manufacturing the same.
FIG. FIG. 7 corresponds to the AA ′ section of FIG. 1 and FIG. 8 corresponds to the BB ′ section of FIG.

Step (A) First, a P-type silicon substrate 12 (impurity concentration of 2.0 × 10 ¹⁵ /
A photoresist is applied to the substrate surface of cm ³ ), and the resist in a portion where the element isolation region 13 is to be formed is removed by patterning. After the etching, an oxide is buried, and a CMP method (chemical mechanical polishing) is performed to form an element isolation region 13. At this time, the active region where the diode portion is formed in the step (C ′) described later is replaced with the step (D).
Are formed at a selected distance from the region sandwiched between the cathode portion formed in step (A) and the anode portion formed in step (E) with the element isolation region 13 interposed therebetween.

Step (B) A photoresist is applied, and the resist at the portion where the low-concentration N-type semiconductor region is to be formed is removed by patterning. Then, an N-type impurity such as phosphorus ( ³¹ P ⁺ ) is ion-implanted at a low concentration. And the low-concentration N-type impurity region 14 (impurity concentration of about 5.0 × 1
0 ¹⁷ / cm ³ ).

Step (C) Next, after the photoresist is removed, the photoresist is removed again.
Apply and pattern to form a low-concentration P-type semiconductor region
The resist of the part to be formed is removed and boron (¹¹B ⁺)
P-type impurities are ion-implanted at a low concentration to form
Area 15 (impurity concentration ~ 2.0 × 10¹⁷/cm^Three), Then
Remove the photoresist.

Step (C ') An oxide film is formed by an oxidation step, and then a polysilicon portion is formed by a method such as CVD (chemical vapor deposition). A distance between the second high-concentration N-type impurity region formed in step (D) and the second high-concentration P-type impurity region formed in step (E) is defined by applying a photoresist and patterning. The photoresist other than the polysilicon portion 16 is removed,
After the etching, the photoresist is removed, and a polysilicon portion 16 is formed in the low-concentration N-type impurity region on the substrate.

Step (D) A photoresist is applied and a low concentration P is formed by patterning.
A first high concentration N-type semiconductor region 17 (cathode portion) formed in the low concentration N-type semiconductor region, a second high concentration N-type semiconductor region 18 forming the diode portion in the low concentration N-type semiconductor region, First high-concentration P-type semiconductor region 21 (anode portion) formed in step (E) in the concentration N-type semiconductor region
And a third high-concentration N-type semiconductor region 19 formed in a region away from the second high-concentration N-type semiconductor region 18 by a selection distance from the second high-concentration N-type semiconductor region 18 in the low-concentration N-type semiconductor region. The resist in each region with the fourth high-concentration N-type semiconductor region 20 is removed. Then, high concentration (~ N-type impurities such as arsenic ⁽⁷⁵ As ⁺⁾ from a direction substantially perpendicular to the substrate surface
Ions are implanted at 3.0 × 10 ¹⁵ / cm ³ and 50 KeV) to form first to fourth high-concentration N-type semiconductor regions 17, 18, 19 and 20.

Step (E) After the removal of the photoresist, a photoresist is applied to the entire surface again, and the first high-concentration P-type semiconductor region 21 (anode portion) formed in the low-concentration N-type semiconductor region by patterning
And a second high-concentration P-type semiconductor region 22 formed over the low-concentration P-type semiconductor region and the low-concentration N-type semiconductor region to form a diode portion;
First high concentration N-type semiconductor region 1 formed in step (D)
7, the third high concentration P formed in a region separated by a selected distance from
Resists in the respective regions of a high-concentration P-type semiconductor region 23 and a fourth high-concentration P-type semiconductor region 24 formed in a region of a low-concentration P-type semiconductor region and a selected distance from the second high-concentration P-type semiconductor region 22 Is removed. Next, a P-type impurity such as boron (BF2 ⁺ ) is concentrated in a direction substantially perpendicular to the substrate surface (~
Ions are implanted at 2.0 × 10 ¹⁵ / cm ² and 40 KeV) to form first to fourth high-concentration N-type semiconductor regions 21, 22, 23 and 24.

Step (F) After removing the photoresist, a metal such as Ti is formed on the substrate surface by sputtering, and thereafter, the activated region and the metal silicide of the polysilicon portion are formed in a self-aligned manner by heat treatment. The activation of the impurities implanted in (D) and (E) is performed, and the first, third, and fourth high-concentration N-type semiconductor regions 17, 19, and 20, and the first, third, and fourth high-concentration N-type semiconductor regions are activated. A contact is formed in each of the high-concentration P-type semiconductor regions 21, 23, and 24, and the first high-concentration P-type semiconductor region 21 and the third and fourth high-concentration N-type semiconductor regions 19, 20 are connected to the same terminal.
T1 and the first high-concentration N-type semiconductor region 17 and the third,
The third high-concentration P-type semiconductor regions 23 and 24 are connected to the same terminal T2. Power supply, ground, T1 and T2 with metal wiring etc.
Alternatively, it is electrically connected to one of the input / output terminals.

In the semiconductor device manufactured by the above steps, the third and fourth high-concentration N-type semiconductor regions 19 and 20 and the third and fourth high-concentration P-type semiconductor regions 23 and 24 are separately arranged. This makes it possible to independently change the switching voltage of the thyristor and the voltage after turning on.

FIG. 10 shows the electrical characteristics of a semiconductor device by simulation according to the embodiment of the present invention. FIG.
In the case of (1), the fourth high-concentration N-type semiconductor region 20 and the second high-concentration N-type semiconductor region 18 forming the diode portion are formed.
Is about 1.5 μm, and in the case of (2), about 5.0 μm
m, and other design values and process conditions are the same. Comparing (1) and (2) of FIG. 10, it can be seen that the switching voltages of the thyristors are different, and the voltages after turn-on are almost equal.

FIGS. 4, 5, and 6 are views corresponding to FIG. 1 of other embodiments 2, 3, and 4 of the semiconductor device according to the present invention. In Example 2 of FIG. 4, the distance between the second high-concentration N-type semiconductor region forming the diode portion and the second high-concentration P-type semiconductor region is defined by the element isolation region. 5 and 6
In the third and fourth embodiments, the diode portion formed to lower the switching voltage of the thyristor is formed in the low-concentration P-type semiconductor region. The distance between the second high-concentration N-type semiconductor region forming the diode portion and the second high-concentration P-type semiconductor region is defined by the polysilicon portion in the third embodiment of FIG. In the fourth embodiment shown in FIG. 6, it is defined by the element isolation region. In any of the embodiments shown in FIGS. 4, 5, and 6, the cathode of the thyristor and the high-concentration P-type semiconductor region forming the diode portion are separated from each other by a selected distance in the low-concentration P-type semiconductor region. 3 high-concentration P-type semiconductor regions and a fourth high-concentration P-type semiconductor region.
The type semiconductor regions are formed independently of each other. Also,
A third high-concentration N-type semiconductor region separated from the high-concentration N-type semiconductor region forming the anode portion and the diode portion of the thyristor by a selected distance in the low-concentration N-type semiconductor region;
Fourth high-concentration N-type semiconductor regions are formed independently of each other. By changing the arrangement of the third and fourth high-concentration N-type semiconductors and the arrangement of the third and fourth high-concentration P-type semiconductor regions, the respective resistance values independently change, and the electrical characteristics of the thyristor are changed. Can be changed.

FIG. 11 shows an example in which the thyristor according to the present invention is applied to an electrostatic protection circuit. In FIG. 11, the input / output terminal
Used as a protection element between ground terminals.

As shown in the above embodiment, according to the present invention, the switching voltage and the holding voltage can be changed independently, and an appropriate protection element for a semiconductor circuit formed by a CMOS process can be produced.

[0039]

According to the present invention, the diode portion is formed at a selected distance from the region between the anode and the cathode of the thyristor, and the anode portion and the cathode portion are independently activated near the diode portion. By forming regions and changing the layout, the resistance between each region is set appropriately, thereby enabling the thyristor holding voltage and switching voltage to be independently optimized, and the CM
It is possible to form an appropriate protection element and protection circuit for preventing electrostatic breakdown of a transistor formed in the OS process.

[Brief description of the drawings]

FIG. 1 is a layout view of a semiconductor device according to the present invention as viewed from a direction perpendicular to a substrate surface.

FIG. 2 is a sectional view taken along line A-A 'of FIG.

FIG. 3 is a sectional view taken along line B-B 'of FIG.

FIG. 4 is a diagram corresponding to FIG. 1 showing a second embodiment of the present invention.

FIG. 5 is a view corresponding to FIG. 1 showing a third embodiment of the present invention.

FIG. 6 is a view corresponding to FIG. 1 showing a fourth embodiment of the present invention.

FIG. 7 is a process drawing showing a cross section AA ′ of FIG. 1 for explaining the method of manufacturing a semiconductor device according to the present invention.

FIG. 8 is a view corresponding to FIG. 7, showing a section taken along line BB ′ of FIG. 1;

FIG. 9 is an equivalent circuit diagram of the semiconductor device of FIG. 1;

FIG. 10 is a graph showing the electrical characteristics of the thyristor of the present invention.

FIG. 11 is an explanatory view showing a protection device for a semiconductor device according to the present invention.

FIG. 12 is a diagram corresponding to FIG. 1 showing a conventional semiconductor device.

FIG. 13 is a sectional view taken along line A-A ′ of FIG.

FIG. 14 is a view corresponding to FIG. 7, illustrating a conventional method for manufacturing a semiconductor device.

FIG. 15 is a graph showing current-voltage characteristics of a general thyristor.

FIG. 16 is an equivalent circuit diagram of a conventional example.

FIG. 17 is a graph showing electric characteristics of a conventional thyristor.

[Explanation of symbols]

 Reference Signs List 12 P-type silicon substrate 13 Element isolation region 14 Low-concentration N-type impurity region 15 Low-concentration P-type semiconductor region 16 Polysilicon portion 17 First high-concentration N-type semiconductor region (cathode) 18 Second high-concentration N-type semiconductor region 19 third high-concentration N-type semiconductor region 20 fourth high-concentration N-type semiconductor region 21 first high-concentration P-type semiconductor region (anode) 22 second high-concentration P-type semiconductor region (diode) 23 3 high concentration P-type semiconductor region 24 fourth high concentration P-type semiconductor region

Claims (12)

[Claims] An N-type and P-type low-concentration semiconductor region are respectively formed on a semiconductor substrate, and a P-type first high-concentration semiconductor region as an anode of a thyristor is formed in the N-type low-concentration semiconductor region. In the low-concentration semiconductor region, an N-type first high-concentration semiconductor region is formed as a thyristor cathode portion. Further, the N-type first high-concentration semiconductor region is separated from the region sandwiched between the N-type and P-type first high-concentration semiconductor regions. Second high-concentration semiconductor region of
A second high-concentration semiconductor region of one type, and one region within the low-concentration semiconductor region of the same type, and the other region over the low-concentration semiconductor regions of N-type and P-type, and at predetermined intervals. A diode portion is disposed to form N-type third and fourth high-concentration semiconductors in the N-type low-concentration semiconductor region apart from the P-type first and N-type second high-concentration semiconductor regions. Regions are formed respectively to electrically connect the N-type third and fourth high-concentration semiconductor regions to the P-type first high-concentration semiconductor region, and to form N-type first and P-type high-concentration semiconductor regions. P-type third and fourth high-concentration semiconductor regions are respectively formed in the P-type low-concentration semiconductor region apart from the high-concentration semiconductor region of P2, and the P-type third and fourth high-concentration semiconductor regions are formed. A semiconductor device in which a region and an N-type first high-concentration semiconductor region are electrically connected. 2. An N-type second high-concentration semiconductor region includes an N-type low-concentration semiconductor region, and a P-type second high-concentration semiconductor region includes an N-type second high-concentration semiconductor region.
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed over the low-concentration semiconductor regions of the P-type and the P-type, respectively. 3. The P-type second high-concentration semiconductor region includes an N-type second high-concentration semiconductor region in a P-type low-concentration semiconductor device.
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed over the low-concentration semiconductor regions of the P-type and the P-type, respectively. 4. The semiconductor device according to claim 1, wherein a polysilicon portion for defining a predetermined interval between the N-type and P-type second high-concentration semiconductor regions is formed on the semiconductor substrate. 13. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein an element isolation region for defining a predetermined interval between the N-type and P-type second high-concentration semiconductor regions is formed in the semiconductor substrate. Semiconductor device. 6. A conductive region is formed on a semiconductor substrate, and the conductive region is connected to N-type third and fourth high-concentration semiconductor regions.
The electrical connection with the first high-concentration semiconductor region of the type and the electrical connection between the third and fourth high-concentration semiconductor regions of the P-type and the first high-concentration semiconductor region of the N-type, respectively. 1 to
6. The semiconductor device according to any one of 5. 7. A method for manufacturing a semiconductor device comprising the following steps (A) to (F). (A) A photoresist is applied on a semiconductor substrate, and a portion of the resist for forming an element isolation region is removed by patterning. After etching, an oxide is buried, and then CMP is performed to perform element isolation. Forming a region; (B) By applying a photoresist and patterning,
Forming a low-concentration N-type semiconductor region by removing a portion of the photoresist for forming the low-concentration N-type semiconductor region and then implanting N-type impurities at a low concentration; (C) After removing the photoresist, the photoresist is applied again, and by patterning, a portion of the photoresist for forming the low-concentration P-type semiconductor region is removed.
Removing the photoresist after the low-concentration P semiconductor region is formed by ion-implanting a low-concentration type impurity. (D) A first high-concentration N-type semiconductor region (cathode portion) formed in a low-concentration P-type semiconductor region by coating and patterning a photoresist, and a low-concentration N-type semiconductor region or a low-concentration P-type semiconductor region. A second high-concentration N-type semiconductor region that is formed across the semiconductor region and forms a diode portion; and a second high-concentration N-type semiconductor region formed in the low-concentration N-type semiconductor region and away from the second high-concentration N-type semiconductor region. The photoresist in each of the third and fourth high-concentration N-type semiconductor regions is removed, and N-type impurities are ion-implanted at a high concentration in a direction substantially perpendicular to the semiconductor substrate. High concentration N of 4
Forming respective mold semiconductor regions. (E) After removing the photoresist, a photoresist is again applied to the entire surface, and the first is formed in the low-concentration N-type semiconductor region by patterning away from the third and fourth high-concentration N-type regions. Whether it spans the high-concentration P-type semiconductor region (anode) and the P-type and N-type low-concentration semiconductor regions,
Alternatively, a second high-concentration P-type semiconductor region, which is arranged at a predetermined distance from the second high-concentration N-type semiconductor region in the P-type low-concentration region to form a diode portion, and the first high-concentration N-type semiconductor region; The photoresist in each of the third and fourth high-concentration P-type semiconductor regions formed in the low-concentration P-type semiconductor region apart from the semiconductor region is removed, and P-type impurities are substantially removed from the substrate surface. A step of performing high-concentration ion implantation from a vertical direction to form first to fourth high-concentration P-type semiconductor regions; (F) After removing the photoresist, the first, third, and fourth high-concentration N-type semiconductor regions are electrically connected, and the first, third, and fourth high-concentration P-type semiconductor regions are electrically connected. Step of connecting to. 8. In the step (E), N-type and P-type second
8. The method of manufacturing a semiconductor device according to claim 7, wherein when arranging the high-concentration semiconductor regions at a predetermined interval, a polysilicon portion defining the predetermined interval is formed on the semiconductor substrate in advance. 9. In the step (E), N-type and P-type second
8. The method of manufacturing a semiconductor device according to claim 7, wherein when arranging the high-concentration semiconductor regions at a predetermined interval, an element isolation region defining the predetermined interval is formed in the semiconductor substrate in advance. 10. In steps (D) and (E), the N-type and P-type second high-concentration semiconductor regions are set in the N-type low-concentration semiconductor region, and the P-type second high-concentration semiconductor region is set in the N-type. 7. The semiconductor device according to claim 7, wherein said semiconductor layer is formed over a P-type low-concentration semiconductor region.
10. The semiconductor device according to any one of items 9. 11. In the steps (D) and (E), the P-type second high-concentration semiconductor region is placed in the P-type low-concentration semiconductor region.
The semiconductor device according to claim 7, wherein the N-type second high-concentration semiconductor region is formed over the N-type and P-type low-concentration semiconductor regions, respectively. 12. An electrostatic protection circuit including one or more of the semiconductor devices according to claim 1 as an electrostatic protection element.