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JP2001185646A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2001185646A
JP2001185646A JP36595499A JP36595499A JP2001185646A JP 2001185646 A JP2001185646 A JP 2001185646A JP 36595499 A JP36595499 A JP 36595499A JP 36595499 A JP36595499 A JP 36595499A JP 2001185646 A JP2001185646 A JP 2001185646A
Authority
JP
Japan
Prior art keywords
electrode
fixed
semiconductor device
conductive
fixed electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP36595499A
Other languages
Japanese (ja)
Inventor
Haruhiko Sakai
春彦 境
Shigeru Fujii
茂 藤井
Haruo Hyodo
治雄 兵藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP36595499A priority Critical patent/JP2001185646A/en
Publication of JP2001185646A publication Critical patent/JP2001185646A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of realizing a small-sized thin package adapted to mounting of a fine semiconductor chip by thinning a supporting board. SOLUTION: The supporting board 50 is formed by integrating two conductive foils 52, 53 with a thermosetting resin film 51 disposed between the foils 52 and 53 by heat press bonding. A conductive material 57 for electrically connecting both the foils 52, 53 without via hole is formed by passing the material 57 through the film 51 at the press bonding time. Electrodes are formed of the foils 52, 53, and the semiconductor chip 58 is mounted. Thus, an extremely thin mounting structure can be realized in a simple structure, and the semiconductor device optimum to mount the fine semiconductor chip is realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置、特にパ
ッケージ外形を超小型で薄型に形成できる微小チップを
収容する樹脂封止型の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device for accommodating a small chip whose package outer shape can be formed to be ultra-small and thin.

【０００２】[0002]

【従来の技術】従来の半導体装置の組立工程において
は、ウェハからダイシングして分離した半導体チップを
リードフレームに固着し、金型と樹脂注入によるトラン
スファーモールドによって半導体チップを封止し、リー
ドフレームを切断して個々の半導体装置毎に分離すると
いう工程が行われている。この方法によって得れらる半
導体装置は、図９に示したように、半導体チップ１の周
囲を樹脂層２で被覆し、該樹脂層２の側部から外部接続
用のリード端子３を導出した構造になる（例えば特開平
０５−１２９４７３号）。2. Description of the Related Art In a conventional semiconductor device assembling process, a semiconductor chip separated by dicing from a wafer is fixed to a lead frame, and the semiconductor chip is sealed by a transfer mold using a mold and resin injection. A process of cutting and separating each semiconductor device is performed. In the semiconductor device obtained by this method, as shown in FIG. 9, the periphery of the semiconductor chip 1 is covered with a resin layer 2, and lead terminals 3 for external connection are led out from the side of the resin layer 2. (For example, JP-A-05-129473).

【０００３】この構造は、樹脂層２の外側にリード端子
３が突出すること、リードフレームの加工精度の問題や
金型との位置あわせ精度の問題により、外形寸法とその
実装面積の縮小化には限界が見えていた。[0003] This structure reduces the external dimensions and the mounting area due to the protrusion of the lead terminals 3 outside the resin layer 2, the problem of the processing accuracy of the lead frame and the problem of the positioning accuracy with the mold. Was seeing the limits.

【０００４】近年、外形寸法を半導体チップサイズと同
等あるいは近似した寸法にまで縮小する事が可能な、ウ
ェハスケールＣＳＰ（チップサイズパッケージ）が注目
され始めている。これは、図１０（Ａ）を参照して、半
導体ウェハ１１に各種拡散などの前処理を施して多数の
半導体チップ１２を形成し、図１０（Ｂ）に示したよう
に半導体ウェハ１１の上部を樹脂層１３で被覆すると共
に樹脂層１３表面に外部接続用の電極１４を導出し、そ
の後半導体ウェハ１１のダイシングラインに沿って半導
体チップ１１を分割して、図１０（Ｃ）に示したような
完成品としたものである。樹脂層１３は半導体チップ１
２の表面（裏面を被覆する場合もある）を被覆するだけ
であり、半導体チップ１２の側壁にはシリコン基板が露
出する。電極１４は樹脂層１３下部に形成された集積回
路網と電気的に接続されており、実装基板上に形成した
導電パターンに対して電極１４を対向接着することによ
りこの半導体装置の実装が実現する。In recent years, attention has been paid to a wafer-scale CSP (chip size package) capable of reducing an outer dimension to a size similar to or close to a semiconductor chip size. In this, referring to FIG. 10A, a large number of semiconductor chips 12 are formed by performing various pretreatments such as diffusion on a semiconductor wafer 11, and an upper portion of the semiconductor wafer 11 is formed as shown in FIG. Is covered with a resin layer 13, electrodes 14 for external connection are led out on the surface of the resin layer 13, and then the semiconductor chips 11 are divided along dicing lines of the semiconductor wafer 11, as shown in FIG. It is a finished product. The resin layer 13 is the semiconductor chip 1
2 only covers the front surface (which may cover the back surface) of the semiconductor chip 12, and the silicon substrate is exposed on the side wall of the semiconductor chip 12. The electrode 14 is electrically connected to an integrated circuit network formed below the resin layer 13, and the semiconductor device is mounted by bonding the electrode 14 to a conductive pattern formed on a mounting substrate. .

【０００５】斯かる半導体装置は、装置のパッケージサ
イズが半導体チップのチップサイズと同等であり、実装
基板に対しても対向接着で済むので、実装占有面積を大
幅に減らすことが出来る利点を有する。また、後工程に
拘わるコストを大幅に減じることが出来る利点を有する
ものである。（例えば、特開平９−６４０４９号）しか
しながら、チップサイズが１０数ｍｍ角にも及ぶＬＳＩ
チップであればその寸法内に多数個の電極を配置するこ
とが可能であるものの、例えばチップサイズが１ｍｍ角
に満たない程度のトランジスタチップ等では、この寸法
内に複数個の電極を配置することは物理的に無理がある
し、実現したとしても実装が困難である欠点がある。[0005] Such a semiconductor device has the advantage that the package size of the device is equivalent to the chip size of the semiconductor chip, and the device can be adhered to the mounting substrate by opposing, so that the area occupied by the mounting can be greatly reduced. Further, there is an advantage that the cost associated with the post-process can be significantly reduced. (For example, Japanese Patent Laid-Open No. 9-64049)
Although it is possible to arrange a large number of electrodes within the dimensions of a chip, for example, for a transistor chip having a chip size of less than 1 mm square, it is necessary to arrange a plurality of electrodes within this dimension. Has the drawback that it is physically unreasonable and difficult to implement even if realized.

【０００６】そこで、チップサイズが１ｍｍ角に満たな
い程度のチップでは図１１（Ａ）（Ｂ）（Ｃ）に示すよ
うに実装されている。 図中、２１はセラミックやガラ
スエポキシ等からなる絶縁基板であり、それらが１枚あ
るいは数枚重ね合わされて、板厚が２５０〜３５０μｍ
と製造工程における機械的強度を維持し得る厚みと、長
辺×短辺が１．０ｍｍ×０．８ｍｍ程度の矩形形状を有
している。Therefore, chips having a chip size of less than 1 mm square are mounted as shown in FIGS. 11A, 11B and 11C. In the figure, reference numeral 21 denotes an insulating substrate made of ceramic, glass epoxy, or the like.
And a thickness capable of maintaining the mechanical strength in the manufacturing process, and a rectangular shape having a long side × short side of about 1.0 mm × 0.8 mm.

【０００７】絶縁基板２１の表面には、タングステン等
の金属ペーストの印刷と、電解メッキ法による前記金属
ペースト上への金メッキによって導電パターンを形成
し、アイランド部２２と電極部２３ａ、２３ｂとを形成
している。アイランド部２２の上には、Ａｇペーストな
どの導電性接着剤２４によって半導体チップ２５が固着
されている。On the surface of the insulating substrate 21, a conductive pattern is formed by printing a metal paste such as tungsten and gold plating on the metal paste by an electrolytic plating method to form an island portion 22 and electrode portions 23a and 23b. are doing. A semiconductor chip 25 is fixed on the island portion 22 by a conductive adhesive 24 such as an Ag paste.

【０００８】半導体チップ２５の表面にはアルミ電極パ
ッド２６が形成され、電極パッド２６と電極部２３ａ、
２３ｂとが、ボンディングワイヤ２７によって電気接続
される。電極パッド２６側に１ｓｔボンド、電極部２３
側に２ｎｄボンドが打たれる。バイポーラトランジスタ
で有れば、電極部２３ａ、２３ｂはエミッタとベースに
対応し、パワーＭＯＳＦＥＴで有れば、ソースとゲート
に対応する。An aluminum electrode pad 26 is formed on the surface of the semiconductor chip 25, and the electrode pad 26 and the electrode portion 23a are formed.
23b are electrically connected to each other by a bonding wire 27. 1st bond on electrode pad 26 side, electrode section 23
A 2nd bond is struck on the side. If it is a bipolar transistor, the electrode portions 23a and 23b correspond to the emitter and the base, and if it is a power MOSFET, it corresponds to the source and the gate.

【０００９】前記絶縁基板２１の裏面側には、同じく金
メッキ層によって第１の外部接続電極２８と第２の外部
接続電極２９ａ、２９ｂが形成される。絶縁基板２１に
はこれを貫通する、円形の第１のビアホール３０と第２
のビアホール３１ａ、３１ｂが形成され、各ビアホール
３０、３１ａ、３１ｂの内部はタングステンなどの導電
材料によって埋設される。素材としては、電気的導電性
と熱伝導性に優れた素材で埋設する。該ビアホール３
０、３１ａ、３１ｂによって、アイランド部２２と第１
の外部接続電極２８とを、電極部２３ａ、２３ｂと第２
の外部接続電極２９ａ、２９ｂとを、各々電気接続す
る。第１の外部接続電極２８が例えばコレクタ電極とな
り、第２の外部接続電極２９ａ、２９ｂが例えばベー
ス、エミッタ電極となる。A first external connection electrode 28 and second external connection electrodes 29a and 29b are formed on the back surface of the insulating substrate 21 by the same gold plating layer. A circular first via hole 30 and a second
Are formed, and the inside of each via hole 30, 31a, 31b is buried with a conductive material such as tungsten. The material is buried with a material having excellent electrical and thermal conductivity. The via hole 3
0, 31a and 31b, the island portion 22 and the first
Of the external connection electrode 28 and the electrode portions 23a and 23b and the second
Are electrically connected to the external connection electrodes 29a and 29b, respectively. The first external connection electrodes 28 are, for example, collector electrodes, and the second external connection electrodes 29a, 29b are, for example, base and emitter electrodes.

【００１０】絶縁基板２１の上方は、半導体チップ２５
とボンディングワイヤ２７とを封止する樹脂層３２で被
覆される。樹脂層３２は絶縁基板２１と共にパッケージ
外形を構成する。パッケージの周囲４側面は樹脂層３２
と絶縁基板２１の切断面で形成され、パッケージの上面
は平坦化した樹脂層３２の表面、パッケージの下面は絶
縁基板２１の裏面側で形成される。The semiconductor chip 25 is located above the insulating substrate 21.
And the bonding wire 27 is covered with a resin layer 32. The resin layer 32 forms an outer shape of the package together with the insulating substrate 21. The four sides around the package are resin layers 32
The upper surface of the package is formed on the flattened surface of the resin layer 32, and the lower surface of the package is formed on the back surface side of the insulating substrate 21.

【００１１】[0011]

【発明が解決しようとする課題】しかしながら図１１で
示した実装構造においていろいろな問題点がある。第１
にタングステン等の高価な金属ペーストを用いているの
で、ローコストの実装構造とは言えない。第２に両面の
電極等を接続するために、絶縁基板を貫通するビアホー
ルが不可欠であり、この加工精度も０．１５mm程度が限
界であるので、更なる小型化の障害となっている。第３
にこのビアホール内を金属ペーストで充填するため作業
性が極めて悪く、コスト高の原因となる。第４に絶縁基
板が機械的強度を維持するために０．２５mmから０．３
５mmは必要であるために薄型化の阻害要因となっている
等々の多くの問題点が発生している。However, there are various problems in the mounting structure shown in FIG. First
Is expensive, so that it cannot be said that the mounting structure is low-cost. Secondly, in order to connect electrodes and the like on both sides, a via hole penetrating the insulating substrate is indispensable, and the processing accuracy is limited to about 0.15 mm, which is an obstacle to further miniaturization. Third
Since the inside of the via hole is filled with a metal paste, the workability is extremely poor, which causes an increase in cost. Fourth, in order to maintain the mechanical strength of the insulating substrate, 0.25 mm to 0.3
Since 5 mm is necessary, there are many problems such as an obstacle to thinning.

【００１２】[0012]

【課題を解決するための手段】本発明は上述した種々の
問題点に鑑みてなされたもであり、熱可塑性樹脂で離間
された相対向する導電箔を有し、一方の導電箔を所望形
状に形成された固着電極および取り出し電極を設け、他
方の導電箔で形成された前記固着電極および取り出し電
極に対応して対向する接続電極を設け、かつ前記固着電
極および取り出し電極と対応する前記接続電極とを電気
的に接続し前記熱可塑性樹脂を貫通する導電材とを有す
る支持基板と、前記固着電極上に固着された半導体素子
と、前記半導体素子の電極と前記取り出し電極とを接続
するボンディング細線と、前記接続電極を露出して前記
半導体素子、固着電極、取り出し電極および前記ボンデ
ィング細線を少なくとも被覆する絶縁樹脂とを具備する
ことを特徴としている。SUMMARY OF THE INVENTION The present invention has been made in view of the various problems described above, and has opposed conductive foils separated by a thermoplastic resin, and one of the conductive foils has a desired shape. A connection electrode facing the fixed electrode and the extraction electrode formed of the other conductive foil, and the connection electrode corresponding to the fixed electrode and the extraction electrode. , A support substrate having a conductive material that electrically connects the semiconductor device and the conductive material, penetrates the thermoplastic resin, a semiconductor element fixed on the fixed electrode, and a bonding thin wire connecting the electrode of the semiconductor element and the extraction electrode. And an insulating resin that exposes the connection electrode and at least covers the semiconductor element, the fixed electrode, the extraction electrode, and the bonding thin wire. That.

【００１３】[0013]

【発明の実施の形態】本発明の一実施例を図１および図
２を参照して説明する。 図１は、本発明の完成された
個別の半導体装置を説明する図であり、（Ａ）が平面
図、（Ｂ）が断面図、（Ｃ）が裏面図である。図２は、
本発明に用いる支持基板を説明する図であり、（Ａ）が
平面図、（Ｂ）が裏面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. 1A and 1B are diagrams illustrating a completed individual semiconductor device of the present invention, wherein FIG. 1A is a plan view, FIG. 1B is a cross-sectional view, and FIG. FIG.
It is a figure explaining a support substrate used for the present invention, (A) is a top view and (B) is a back view.

【００１４】本発明の特徴とする支持基板５０は、熱可
塑性樹脂のフィルム５１の両面に２枚の導電箔５２，５
３（図３参照）を熱圧着して形成されている。熱可塑性
樹脂は加熱することにより軟化して二次加工が容易であ
り、従来用いていたセラミックスやガラスエポキシの硬
質基板よりはるかに扱いやすくなる。熱可塑性樹脂とし
ては液晶ポリマーが最適であり、本実施例では全芳香族
ポリエステル系液晶ポリマー（商品名ベクトラ）を用い
た。この全芳香族ポリエステル系液晶ポリマーは物性的
特性として、融点が３２５℃、はんだ耐熱性は３２０℃
であり、十分に半導体素子の実装基板として使用でき
る。これは例えばガラスエポキシ基板のはんだ耐熱性が
２６０℃であることからも容易に分かる。The supporting substrate 50, which is a feature of the present invention, comprises two conductive foils 52, 5 on both surfaces of a thermoplastic resin film 51.
3 (see FIG. 3) is formed by thermocompression bonding. The thermoplastic resin is softened by heating and is easily subjected to secondary processing, and is much easier to handle than a conventionally used ceramic or glass epoxy hard substrate. A liquid crystal polymer is most suitable as the thermoplastic resin. In this example, a wholly aromatic polyester liquid crystal polymer (Vectra) was used. This wholly aromatic polyester-based liquid crystal polymer has physical properties such as a melting point of 325 ° C and a solder heat resistance of 320 ° C.
Therefore, it can be sufficiently used as a mounting substrate for a semiconductor element. This can be easily understood from the fact that the solder heat resistance of the glass epoxy substrate is 260 ° C., for example.

【００１５】熱可塑性樹脂フィルム５１の両面にはこの
樹脂フィルムで離間されかつ電気的に絶縁された２枚の
導電箔５２，５３が圧着されている。この導電箔として
は安価で電気的抵抗の小さい銅箔が最適である。具体的
には５０μｍの厚みの熱可塑性樹脂フィルム５１の両面
に各々１２μｍの厚みの銅箔５２，５３が圧着されてい
る。一方の導電箔５２はエッチングされて所望形状のパ
ターンに加工され、固着電極５４と取り出し電極５５
ａ、５５ｂを形成する。固着電極５４は少なくとも半導
体チップ５８が載置できる大きさと形状を有しており、
この固着電極５４に隣接して少し離間して取り出し電極
５５ａ、５５ｂが複数個形成されている。他方の導電箔
５３もエッチングされて所望形状のパターンに加工さ
れ、固着電極５４と取り出し電極５５ａ、５５ｂと対向
する位置に接続電極５６、５６ａ、５６ｂを形成する。
接続電極５６、５６ａ、５６ｂはプリント基板にはんだ
付けできる大きさに形成され、はんだ付けの際にはんだ
ブリッジが形成されないように離間され、対応する固着
電極５４および取り出し電極５５ａ、５５ｂよりは小さ
く形成される。なお固着電極５４、取り出し電極５５
ａ、５５ｂおよび接続電極５６、５６ａ、５６ｂは電解
メッキによりその表面をニッケルメッキ層と金メッキ層
で被覆されており、導電ペーストとの接触抵抗を減少さ
せ、またボンディング細線の固着を可能にしている。Two conductive foils 52 and 53 which are separated from each other by the resin film and electrically insulated are pressure-bonded to both surfaces of the thermoplastic resin film 51. As the conductive foil, an inexpensive copper foil having a small electric resistance is optimal. Specifically, copper foils 52 and 53 each having a thickness of 12 μm are pressure-bonded to both surfaces of a thermoplastic resin film 51 having a thickness of 50 μm. One conductive foil 52 is etched and processed into a desired shape pattern, and the fixed electrode 54 and the extraction electrode 55
a and 55b are formed. The fixed electrode 54 has at least a size and a shape on which the semiconductor chip 58 can be mounted.
A plurality of extraction electrodes 55a and 55b are formed adjacent to the fixed electrode 54 and slightly apart therefrom. The other conductive foil 53 is also etched and processed into a desired shape pattern, and connection electrodes 56, 56a, 56b are formed at positions facing the fixed electrode 54 and the extraction electrodes 55a, 55b.
The connection electrodes 56, 56a, 56b are formed in a size that can be soldered to a printed circuit board, are separated so that a solder bridge is not formed at the time of soldering, and are formed smaller than the corresponding fixed electrodes 54 and extraction electrodes 55a, 55b. Is done. Note that the fixed electrode 54 and the extraction electrode 55
The surfaces of the a and 55b and the connection electrodes 56, 56a and 56b are covered with a nickel plating layer and a gold plating layer by electrolytic plating to reduce the contact resistance with the conductive paste and enable the bonding of the bonding thin wires. .

【００１６】導電材５７は一方の導電箔５２で形成され
た固着電極５４、取り出し電極５５ａ、５５ｂと他方の
導電箔５３で形成された対応する接続電極５６、５６
ａ、５６ｂとを接続している。導電材５７としては銀ペ
ーストを用い、熱可塑性樹脂５１を加熱して軟化させて
導電材５７を貫通させている。従って予めビアホールを
設ける必要が無くなる。導電材５７を貫通させる位置は
図１（Ａ）（Ｃ）に破線丸印で示すように、固着電極５
４では取り出し電極５５ａ、５５ｂと離れた側の上下両
端近くに２個設け、取り出し電極５５ａ、５５ｂではほ
ぼ中央部に１個形成している。The conductive material 57 includes a fixed electrode 54 formed of one conductive foil 52, extraction electrodes 55a, 55b, and corresponding connection electrodes 56, 56 formed of the other conductive foil 53.
a, 56b. A silver paste is used as the conductive material 57, and the thermoplastic resin 51 is heated and softened to penetrate the conductive material 57. Therefore, it is not necessary to provide a via hole in advance. The position through which the conductive material 57 is penetrated is indicated by a broken-line circle in FIGS.
In No. 4, two are provided near the upper and lower ends on the side distant from the extraction electrodes 55a and 55b, and one is formed substantially in the center of the extraction electrodes 55a and 55b.

【００１７】半導体チップ５８は固着電極５４上にＡｇ
ペーストなどの導電ペースト５９により固着されてい
る。半導体チップ５８としては、バイポーラトランジス
タ、パワーＭＯＳＦＥＴ等の３端子素子又はダイオード
などの２端子素子が形成されているウエファーから供給
される。半導体チップ５８自体は、Ｎ＋／Ｎ型構造のよ
うに、裏面側に高濃度不純物層を有しており、該高濃度
層を介して、ダイオード素子で有ればアノード又はカソ
ードの一方の端子を、バイポーラ型トランジスタで有れ
ばコレクタ端子を、パワーＭＯＳＦＥＴで有ればドレイ
ン端子を導出する構造を有しているので、この高濃度層
が導電ペースト５９を介して固着電極５４にオーミック
接続される。The semiconductor chip 58 has Ag fixed on the fixed electrode 54.
It is fixed by a conductive paste 59 such as a paste. The semiconductor chip 58 is supplied from a wafer on which a three-terminal element such as a bipolar transistor or a power MOSFET or a two-terminal element such as a diode is formed. The semiconductor chip 58 itself has a high-concentration impurity layer on the back side like an N + / N-type structure, and through the high-concentration layer, connects one terminal of an anode or a cathode if it is a diode element. In the case of a bipolar transistor, the collector terminal is provided, and in the case of a power MOSFET, the drain terminal is provided, so that this high concentration layer is ohmically connected to the fixed electrode 54 via the conductive paste 59. .

【００１８】半導体チップ５８の表面にはアルミ電極パ
ッド６０が形成され、電極パッド６０と取り出し電極５
５ａ、５５ｂとが、金線ボンディングワイヤ６１によっ
て電気接続される。電極パッド６０側に１ｓｔボンド、
取り出し電極５５ａ、５５ｂ側に２ｎｄボンドが打たれ
る。バイポーラトランジスタで有れば、取り出し電極５
５ａ、５５ｂはエミッタとベースに対応し、パワーＭＯ
ＳＦＥＴで有れば、ソースとゲートに対応する。An aluminum electrode pad 60 is formed on the surface of the semiconductor chip 58, and the electrode pad 60 and the extraction electrode 5 are formed.
5a and 55b are electrically connected by a gold wire bonding wire 61. 1st bond on the electrode pad 60 side,
A second bond is formed on the side of the extraction electrodes 55a and 55b. If it is a bipolar transistor, the extraction electrode 5
5a and 55b correspond to the emitter and the base, respectively.
If it is an SFET, it corresponds to the source and the gate.

【００１９】支持基板５０の上面は、半導体チップ５
８、固着電極５４、取り付け電極５５ａ、５５ｂおよび
ボンディングワイヤ６１とを被覆する絶縁樹脂６２で封
止される。絶縁樹脂６２は支持基板５１と共にパッケー
ジ外形を構成する。パッケージの周囲４側面は絶縁樹脂
６２と支持基板５１の切断面で形成され、パッケージの
上面は平坦化した絶縁樹脂層６２の表面、パッケージの
下面は支持基板５０の裏面側で形成される。絶縁樹脂６
２は一般的に用いられるエポキシ樹脂を用いる。The upper surface of the supporting substrate 50 is
8. Sealed with an insulating resin 62 covering the fixed electrode 54, the mounting electrodes 55a and 55b, and the bonding wires 61. The insulating resin 62 forms a package outer shape together with the support substrate 51. The four peripheral sides of the package are formed by the cut surface of the insulating resin 62 and the support substrate 51, the upper surface of the package is formed by the flattened surface of the insulating resin layer 62, and the lower surface of the package is formed by the back surface of the support substrate 50. Insulating resin 6
2 uses a commonly used epoxy resin.

【００２０】次に、図２を参照して支持基板５１の上面
に一方の導電箔５２から形成される固着電極５４および
取り出し電極５５ａ、５５ｂと、裏面に他方の導電箔５
３から形成される接続電極５６、５６ａ、５６ｂの関係
を説明する。Next, referring to FIG. 2, fixed electrode 54 and extraction electrodes 55a and 55b formed from one conductive foil 52 on the upper surface of support substrate 51, and the other conductive foil 5 on the back surface.
The relationship between the connection electrodes 56, 56a, and 56b formed from 3 will be described.

【００２１】点線で囲んだ各搭載部７０は、例えば長辺
×短辺が０．９ｍｍ×０．８ｍｍの矩形形状を有してお
り、これらは互いに２０〜５０μｍの間隔を隔てて２４
行２４列の行列上に縦横に配置されている。前記間隔は
後の工程でのダイシングライン７１となる。導電パター
ンは、各搭載部７０内において固着電極５４と取り出し
電極５５ａ、５５ｂを形成し、これらのパターンは各搭
載部７０内において同一形状である。Each mounting portion 70 surrounded by a dotted line has, for example, a rectangular shape of 0.9 mm × 0.8 mm in a long side × a short side, and is separated from each other by a distance of 20 to 50 μm.
They are arranged vertically and horizontally on a matrix of 24 rows. The interval becomes a dicing line 71 in a later step. The conductive pattern forms the fixed electrode 54 and the extraction electrodes 55a and 55b in each mounting portion 70, and these patterns have the same shape in each mounting portion 70.

【００２２】固着電極５４からは２本の連結部７２が連
続したパターンで延長される。これらの線幅は固着電極
５４よりも狭い線幅で、例えば０．０７５ｍｍの線幅で
延在する。連結部７２はダイシングライン７１を超えて
隣の搭載部７０の取り出し電極５５ａ、５５ｂに連結す
るまで延在する。更に、固着電極５４から上下方向に連
結部７３が、連結部７２とは直行する方向に延在され、
ダイシングライン７１を越えて隣の搭載部７０の固着電
極５４に連結するまで延在される。連結部７３は更に、
搭載部７０周囲を取り囲む共通連結部７４に連結され、
各搭載部７０の固着電極５４と取り出し電極５５ａ、５
５ｂとを電気的に共通接続する。From the fixed electrode 54, two connecting portions 72 are extended in a continuous pattern. These line widths are narrower than the fixed electrode 54 and extend with a line width of, for example, 0.075 mm. The connecting portion 72 extends beyond the dicing line 71 until it is connected to the extraction electrodes 55a and 55b of the adjacent mounting portion 70. Further, a connecting portion 73 extends vertically from the fixed electrode 54 in a direction perpendicular to the connecting portion 72,
It extends until it is connected to the fixed electrode 54 of the adjacent mounting part 70 beyond the dicing line 71. The connecting portion 73 further includes
Connected to a common connecting portion 74 surrounding the mounting portion 70,
The fixed electrode 54 and the extraction electrodes 55a, 5
5b is electrically connected in common.

【００２３】支持基板５０の裏面側には、第１と第２の
接続電極５６、５６ａ、５６ｂを形成する。これらの接
続電極５６、５６ａ、５６ｂは、搭載部７０の端から
０．０５〜０．１ｍｍ程度後退されたパターンで形成さ
れている。両導電箔５２，５３を離間する熱可塑性樹脂
５１は丸印で図示する位置で導電材５７で貫通されて電
気的接続をされている。具体的には固着電極５４と第１
の接続電極５６は上下に２個設けた導電材５７で接続さ
れ、各々の取り出し電極５５ａ、５５ｂは第２の接続電
極５６ａ、５６ｂとその中央部に設けた導電材５７で接
続されている。従って各電極は導電材５７を介して、支
持基板５０表面側の共通連結部７４に接続される。従っ
て、ダイシング後にそれぞれが細い連結部７３，７４を
切断されることで個々の電極として機能する。全パター
ンが電気的に共通接続されるので、電解メッキ法により
各電極表面をニッケルメッキ層および金メッキ層で被覆
することが可能となる。On the back side of the support substrate 50, first and second connection electrodes 56, 56a, 56b are formed. These connection electrodes 56, 56 a, 56 b are formed in a pattern recessed from the end of the mounting section 70 by about 0.05 to 0.1 mm. The thermoplastic resin 51 separating the two conductive foils 52 and 53 is penetrated by a conductive material 57 at a position shown by a circle to be electrically connected. Specifically, the fixed electrode 54 and the first
The connection electrodes 56 are connected by two conductive members 57 provided above and below, and the respective extraction electrodes 55a and 55b are connected to the second connection electrodes 56a and 56b by a conductive material 57 provided at the center thereof. Therefore, each electrode is connected to the common connection part 74 on the surface side of the support substrate 50 via the conductive material 57. Accordingly, the thin connecting portions 73 and 74 are cut off after dicing to function as individual electrodes. Since all the patterns are electrically connected in common, it is possible to cover the surface of each electrode with a nickel plating layer and a gold plating layer by an electrolytic plating method.

【００２４】熱可塑性樹脂５１はセラミックやガラスエ
ポキシ基板に比較すると軟質であるので、ボンディング
する際にボンディング圧力が発散する欠点がある。これ
を防止するために取り出し電極５５ａ、５５ｂと第２の
接続電極５６ａ、５６ｂはほぼ重なるように配置され、
少なくとも両電極が重なる位置の取り出し電極５５ａ、
５５ｂ上にボンディング細線をボンディングすることが
望ましく、更には両電極と導電材５７とが重なる取り出
し電極５５ａ、５５ｂの中央にボンディング細線をボン
ディングすることがより望ましい。また固着電極５４は
第１の接続電極５６と半分程度重なって形成されている
が、半導体チップの約半分以上が第１の接続電極５６と
重なって固着電極５４に上に固着され、かつ２個の導電
材５７と重なるように固着することによりボンディング
時に半導体チップの上下の沈みを抑えることができボン
ディング細線のループ形状を安定化できる。さらに望ま
しくは半導体チップ５８の電極６０を第１の接続電極５
６上に位置するようにするとボンディング時の半導体チ
ップの上下の沈みを除去できる。Since the thermoplastic resin 51 is softer than a ceramic or glass epoxy substrate, there is a disadvantage that a bonding pressure is diverged during bonding. In order to prevent this, the extraction electrodes 55a, 55b and the second connection electrodes 56a, 56b are arranged so as to substantially overlap,
An extraction electrode 55a at a position where at least both electrodes overlap,
It is desirable to bond a bonding thin wire on 55b, and it is more preferable to bond the bonding thin wire to the center of the extraction electrodes 55a and 55b where both electrodes and the conductive material 57 overlap. The fixed electrode 54 is formed so as to overlap with the first connection electrode 56 by about half. However, about half or more of the semiconductor chip overlaps with the first connection electrode 56 and is fixed on the fixed electrode 54, and two By fixing the conductive material 57 so as to overlap with the conductive material 57, the vertical sinking of the semiconductor chip during bonding can be suppressed, and the loop shape of the bonding thin wire can be stabilized. More preferably, the electrode 60 of the semiconductor chip 58 is connected to the first connection electrode 5.
6, the upper and lower sinks of the semiconductor chip during bonding can be removed.

【００２５】上述した本発明による半導体装置は両導電
箔の離間材料として熱可塑性樹脂フィルムを利用してい
ることにより、熱可塑性に起因する軟質性の障害を取り
除くことが重要である。しかし熱可塑性樹脂フィルムと
して液晶ポリマーを用いることによる数々の利点も有し
ている。電気特性では、誘電率において１ＭＨ（２０
℃、９６Ｈ、６５％ＲＨ）で３．０，１ＧＨｚで２．９
であり、ガラスエポキシ基板で誘電率が１ＭＨｚで４．
７〜５．０と比較するとかなり優れている。また表面抵
抗は１４×１０１３Ωであり、ポリイミド樹脂の１．１
×１０１３Ωと比較しても大幅に絶縁性が高い。これら
から本発明の支持基板は極めて高周波領域での特性が良
好であることが明らかである。更に耐折性についてはＪ
ＩＳ Ｃ５０１６評価規格でＲ＝０．３８ｍｍで４４回
もあり、同一条件でポリイミド樹脂は３３回と比較すれ
ば細線の断線が少ない。更に吸水率０．０４％であり、
湿度下での絶縁性は良好であり、ガスバリヤー性も高
く、ノンハロゲン、スルーホールメッキレスと環境調和
も優れている。In the semiconductor device according to the present invention described above, since a thermoplastic resin film is used as a material for separating both conductive foils, it is important to remove a soft failure caused by thermoplasticity. However, there are also a number of advantages of using a liquid crystal polymer as the thermoplastic resin film. In electrical properties, the dielectric constant is 1 MH (20
C., 96H, 65% RH) 3.0, 2.9 at 1 GHz.
And a glass epoxy substrate having a dielectric constant of 1 MHz.
It is considerably better than 7 to 5.0. The surface resistance is 14 × 10 13 Ω, and the resistance of the polyimide resin is 1.1.
The insulating property is significantly higher than that of × 10 13 Ω. From these, it is apparent that the support substrate of the present invention has excellent characteristics in an extremely high frequency range. As for the folding resistance,
There are 44 times with R = 0.38 mm in the IS C5016 evaluation standard. Under the same conditions, the polyimide resin is less likely to break the thin line than 33 times. Furthermore, the water absorption is 0.04%,
It has good insulation properties under humidity, high gas barrier properties, and is environmentally friendly with no halogens and no through-hole plating.

【００２６】続いて本発明の半導体装置の製造方法を図
３から図８を参照して説明する。Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

【００２７】第１工程：図３（Ａ）（Ｂ）（Ｃ）参照 本工程ではまず支持基板を形成することにある。図３
（Ａ）に示すように、第１の導電箔５２、熱可塑性樹脂
から成るフィルム５１および第２の導電箔５３を準備す
る。第１および第２の導電箔５２,５３は安価で電気抵
抗の低い銅箔が適しており、１２μｍ厚で熱可塑性樹脂
から成るフィルム５１と当接する面を凹凸に粗面化して
固着強度を高めるようにしている。熱可塑性樹脂５１と
しては液晶ポリマーが最適であり、本実施例では全芳香
族ポリエステル系液晶ポリマー（商品名ベクトラ）を用
いた。この全芳香族ポリエステル系液晶ポリマーは物性
的特性として、融点が３２５℃、はんだ耐熱性は３２０
℃であり、十分に半導体素子の実装基板として使用でき
る。これは例えばガラスエポキシ基板のはんだ耐熱性が
２６０℃であることからも容易に分かる。第２の導電箔
５３表面には導電材５７である銀ぺーストを所定の位置
にスクリーン印刷して熱可塑性樹脂フィルム５１を貫通
する高さ（例えば５０μｍ以上）にバンプ８０を予め形
成しておく。First step: See FIGS. 3A, 3B and 3C In this step, first, a supporting substrate is formed. FIG.
As shown in (A), a first conductive foil 52, a film 51 made of a thermoplastic resin, and a second conductive foil 53 are prepared. As the first and second conductive foils 52 and 53, an inexpensive and low-resistance copper foil is suitable, and the surface in contact with the film 51 made of a thermoplastic resin and having a thickness of 12 μm is roughened into irregularities to increase the bonding strength. Like that. As the thermoplastic resin 51, a liquid crystal polymer is most suitable. In this example, a wholly aromatic polyester liquid crystal polymer (Vectra) was used. The properties of the wholly aromatic polyester-based liquid crystal polymer are as follows: melting point: 325 ° C .;
° C, and can be sufficiently used as a mounting substrate for a semiconductor element. This can be easily understood from the fact that the solder heat resistance of the glass epoxy substrate is 260 ° C., for example. On the surface of the second conductive foil 53, a silver paste as the conductive material 57 is screen-printed at a predetermined position, and a bump 80 is formed in advance at a height (for example, 50 μm or more) penetrating the thermoplastic resin film 51. .

【００２８】第１および第２の導電箔５２，５３と熱可
塑性樹脂フィルム５１は最初は幅１ｍのロール状で供給
され、多数の支持基板５０を形成した後に個別の支持基
板５０に分離される。この個別の支持基板５０が図２に
示すものであり、この個別の支持基板５０にも２４行２
４列に５７６個の半導体素子の搭載部７０が形成される
ことになる。The first and second conductive foils 52 and 53 and the thermoplastic resin film 51 are initially supplied in the form of a roll having a width of 1 m, formed into a large number of support substrates 50, and then separated into individual support substrates 50. . This individual support substrate 50 is shown in FIG.
The mounting portions 70 of 576 semiconductor elements are formed in four rows.

【００２９】次に、図３（Ｂ）に示すように第１の導電
箔５２、熱可塑性樹脂フィルム５１および第２の導電箔
５３を熱圧着して一体化された支持基板５０を形成す
る。この熱圧着時に熱可塑性樹脂フィルム５１は加熱さ
れて軟化するので、第２の導電箔５３に付着された導電
材５７となるバンプは熱可塑性樹脂フィルム５１を貫通
し第１の導電箔５２まで到達する。熱可塑性樹脂フィル
ム５１として液晶ポリマーを用いた場合は、加熱温度３
００℃、圧着圧力４．４〜８．７ｋＰａで真空熱圧着を
行う。このとき液晶ポリマーはガラス転移点に近くかな
り軟化しているので、導電ペーストで形成された先端が
尖ったバンプ８０がこの液晶ポリマーを貫通する。なお
このときに接着剤は使用していない。Next, as shown in FIG. 3B, the first conductive foil 52, the thermoplastic resin film 51, and the second conductive foil 53 are thermocompression-bonded to form an integrated support substrate 50. During this thermocompression bonding, the thermoplastic resin film 51 is heated and softened, so that the bumps serving as the conductive material 57 attached to the second conductive foil 53 penetrate the thermoplastic resin film 51 and reach the first conductive foil 52. I do. When a liquid crystal polymer is used as the thermoplastic resin film 51, the heating temperature is 3
Vacuum thermocompression bonding is performed at 00 ° C. and a compression pressure of 4.4 to 8.7 kPa. At this time, since the liquid crystal polymer is considerably softened near the glass transition point, a bump 80 having a sharp tip made of a conductive paste penetrates the liquid crystal polymer. At this time, no adhesive was used.

【００３０】更に、図３（Ｃ）に示すように熱圧着を完
了すると、第１の導電箔５２、熱可塑性樹脂フィルム５
１、第２の導電箔５３は密着して一体化されるので、導
電ペーストよりなるバンプ８０も潰されて０．１５ｍｍ
の径の柱状の導電材５７を形成する。Further, as shown in FIG. 3C, when the thermocompression bonding is completed, the first conductive foil 52, the thermoplastic resin film 5
Since the first and second conductive foils 53 are in close contact and integrated, the bumps 80 made of conductive paste are also crushed to 0.15 mm.
A columnar conductive material 57 having a diameter of is formed.

【００３１】第２工程：図４（Ａ）（Ｂ）参照 斯かる支持基板５０の両主面は第１および第２の導電箔
５２，５３で被覆されている。図４（Ａ）示すように、
この第１の導電箔５２上には所定の形状の固着電極５
４、取り出し電極５５上を覆うようにレジスト膜８１を
付着し、第２の導電箔５３上にも所定の形状の第１およ
び第２の接続電極５６、５６ａ、５６ｂ上を覆うように
レジスト膜８１を付着する。レジスト膜８１としては液
状のレジスト材料をスピンコートして感光現像しても良
いし、フィルム状のレジスト材料を貼り付けて感光現像
しても良い。Second step: See FIGS. 4A and 4B Both main surfaces of the support substrate 50 are covered with first and second conductive foils 52 and 53. As shown in FIG.
The fixed electrode 5 having a predetermined shape is formed on the first conductive foil 52.
4. A resist film 81 is attached so as to cover the extraction electrode 55, and the resist film is also formed on the second conductive foil 53 so as to cover the first and second connection electrodes 56, 56a, and 56b having a predetermined shape. Attach 81. As the resist film 81, a liquid resist material may be spin-coated and subjected to photosensitive development, or a film-shaped resist material may be attached and subjected to photosensitive development.

【００３２】続いてレジスト膜８１をマスクとして第１
および第２の導電箔５２，５３を塩化第２鉄溶液を用い
て化学的にエッチングして、第１の導電箔５２で固着電
極５４、取り出し電極５５ａ、５５ｂを形成し、第２の
導電箔５３で第１および第２の接続電極５６、５６ａ、
５６ｂを形成する。これらの電極の具体的な形状はすで
に図２（Ａ）（Ｂ）で説明しているので、その部分を参
照されたい。これらの電極は全てが連結電極７２，７３
や導電材５７で電気的に接続されているので、電解メッ
キによりこれらの電極上に金メッキの下地となるニッケ
ルメッキ層（５μｍ以上）とその上に金メッキ層（０．
５μｍ以上）を形成している。Subsequently, the first film is formed using the resist film 81 as a mask.
Then, the second conductive foils 52 and 53 are chemically etched using a ferric chloride solution to form the fixed electrode 54 and the lead-out electrodes 55a and 55b with the first conductive foil 52. At 53, the first and second connection electrodes 56, 56a,
Form 56b. The specific shapes of these electrodes have already been described with reference to FIGS. 2A and 2B, so please refer to those portions. These electrodes are all connected electrodes 72, 73.
And a nickel plating layer (5 μm or more) serving as a base for gold plating on these electrodes by electrolytic plating, and a gold plating layer (0.
5 μm or more).

【００３３】第３工程：図５参照 上述したように各電極を形成した支持基板５０の各搭載
部７０毎に、半導体チップ５８をダイボンドする。半導
体チップ５８は固着電極５４表面にＡｇペーストなどの
導電ペースト５９によって固着される。導電ペースト５
９は個別の支持基板５０の固着電極５４上にスクリーン
印刷で付着された後、半導体チップ５８を載置して、還
元雰囲気中の電気炉内で熱可塑性樹脂フィルムのガラス
転移点２０５℃以下の約１５０℃の温度で約３０分間硬
化させる。Third step: see FIG. 5 A semiconductor chip 58 is die-bonded to each mounting portion 70 of the support substrate 50 on which each electrode is formed as described above. The semiconductor chip 58 is fixed to the surface of the fixed electrode 54 with a conductive paste 59 such as an Ag paste. Conductive paste 5
9, a semiconductor chip 58 is mounted on the fixed electrode 54 of the individual support substrate 50 by screen printing, and placed in an electric furnace in a reducing atmosphere, and has a glass transition point of 205 ° C. or less of a thermoplastic resin film. Cure at a temperature of about 150 ° C. for about 30 minutes.

【００３４】また本工程で、固着電極５４は第１の接続
電極５６と半分程度重なって形成されているが、半導体
チップ５８の約半分以上が第１の接続電極５６と重なっ
て固着電極５４に上に固着され、かつ２個の導電材５７
と重なるように固着することによりボンディング時に半
導体チップ５８の上下の沈みを抑えることができボンデ
ィング細線のループ形状を安定化できる。さらに望まし
くは半導体チップ５８の電極６０を第１の接続電極５６
上に位置するようにするとボンディング時の半導体チッ
プ５８の上下の沈みを除去できる。In this step, the fixed electrode 54 is formed so as to overlap with the first connection electrode 56 by about half. However, about half or more of the semiconductor chip 58 overlaps with the first connection electrode 56 and forms the fixed electrode 54. Fixed on the top and two conductive members 57
When the semiconductor chip 58 is bonded, the sinking of the semiconductor chip 58 in the vertical direction can be suppressed, and the loop shape of the bonding fine wire can be stabilized. More preferably, the electrode 60 of the semiconductor chip 58 is connected to the first connection electrode 56.
When it is positioned above, the upper and lower sinks of the semiconductor chip 58 during bonding can be removed.

【００３５】第４工程：図６参照 半導体チップ５８の電極パッド６０と取り出し電極５５
ａ、５５ｂとを各々金などのボンディングワイヤ６１で
接続する。金線によりボールボンドをする場合は、支持
基板５０を１５０℃に加熱して半導体チップ５８の電極
パッド６０に金線の一端に形成したボール部分を熱圧着
し、多端を取り出し電極５５ａ、５５ｂに熱圧着する。
この際、熱可塑性樹脂フィルム５１はセラミックやガラ
スエポキシ基板に比べて軟質でボンディングが難しいの
で、第２の接続電極５６ａ、５６ｂと重なる取り出し電
極５５ａ、５５ｂ上にボンディングをすることにより両
導電箔を形成する銅箔の堅さを利用すると良い。更に第
２接続電極５６ａ、５６ｂと導電材５７および取り出し
電極５５ａ、５５ｂが重なる部分にボンディングする
と、熱可塑性樹脂フィルム５１の軟質性の障害を完全に
クリアできる。Fourth step: See FIG. 6 The electrode pad 60 and the extraction electrode 55 of the semiconductor chip 58
a and 55b are connected by bonding wires 61 such as gold. In the case of performing ball bonding with a gold wire, the supporting substrate 50 is heated to 150 ° C., and the ball portion formed at one end of the gold wire is thermocompression-bonded to the electrode pad 60 of the semiconductor chip 58, and multiple ends are taken out to the electrodes 55a and 55b. Thermocompression bonding.
At this time, since the thermoplastic resin film 51 is softer than the ceramic or glass epoxy substrate and is difficult to bond, the two conductive foils are bonded by bonding on the extraction electrodes 55a and 55b overlapping the second connection electrodes 56a and 56b. It is preferable to use the hardness of the copper foil to be formed. Further, by bonding the second connection electrodes 56a and 56b to the portions where the conductive material 57 and the extraction electrodes 55a and 55b overlap, the soft failure of the thermoplastic resin film 51 can be completely cleared.

【００３６】第５工程：図７（Ａ）（Ｂ）（Ｃ）参照 支持基板５０の各載置部に半導体チップ５８のダイボン
ドとボンディング細線６１による接続が終了すると、絶
縁樹脂６２により全体のモールドを行う。本工程では支
持基板５０の裏面に露出する接続電極５６、５６ａ、５
６ｂを除き、半導体チップ５８、固着電極５４、取り出
し電極５５ａ、５５ｂおよびボンディング細線６１をエ
ポキシ系樹脂６２で被覆する。Fifth Step: See FIGS. 7A, 7B, and 7C When the die bonding of the semiconductor chip 58 and the bonding thin wires 61 are completed on each mounting portion of the support substrate 50, the entire molding is performed by the insulating resin 62. I do. In this step, the connection electrodes 56, 56a, 5
Except for 6b, the semiconductor chip 58, the fixed electrode 54, the extraction electrodes 55a and 55b, and the bonding thin wires 61 are covered with an epoxy resin 62.

【００３７】すなわち、図７（Ａ）に示すように、支持
基板５０の上方に移送したディスペンサ（図示せず）か
ら所定量のエポキシ系液体樹脂を滴下（ポッティング）
し、すべての半導体チップ５８を共通の絶縁樹脂層６２
で被覆する。液体樹脂として例えばＣＶ５７６ＡＮ（松
下電工製）を用いた。滴下した液体樹脂は比較的粘性が
高く、表面張力を有しているので、その表面が湾曲す
る。That is, as shown in FIG. 7A, a predetermined amount of epoxy liquid resin is dropped (potted) from a dispenser (not shown) transferred above the support substrate 50.
Then, all the semiconductor chips 58 are connected to the common insulating resin layer 62.
Cover with. For example, CV576AN (manufactured by Matsushita Electric Works) was used as the liquid resin. Since the dropped liquid resin has relatively high viscosity and surface tension, its surface is curved.

【００３８】次に、図７（Ｂ）に示すように、絶縁樹脂
層６２の湾曲した表面を、平坦面に加工する。加工する
には、樹脂が硬化する前に平坦な成形部材を押圧して平
坦面に加工する手法と、滴下した樹脂層６２を１８０℃
で数時間の熱処理（キュア）にて硬化させた後に、湾曲
面を例えばダイシングブレードで研削することによって
平坦面に加工する手法とが考えられる。この工程では、
絶縁樹脂層６２の表面が支持基板５０から０．３〜１．
０ｍｍの高さに揃うように、表面を削る。平坦面は、少
なくとも最も外側に位置する半導体チップ５８を個別半
導体装置に分離したときに、規格化したパッケージサイ
ズの樹脂外形を構成できるように、その端部まで拡張す
る。Next, as shown in FIG. 7B, the curved surface of the insulating resin layer 62 is processed into a flat surface. In order to process the resin, a flat molding member is pressed before the resin is cured to form a flat surface.
After curing by heat treatment (curing) for several hours, a method of processing the curved surface into a flat surface by grinding the curved surface with, for example, a dicing blade can be considered. In this step,
The surface of the insulating resin layer 62 is 0.3 to 1.
Grind the surface to make it equal to 0mm height. The flat surface is extended to its end so that at least when the outermost semiconductor chip 58 is separated into individual semiconductor devices, a resin outer shape having a standardized package size can be formed.

【００３９】更に図７（Ｃ）に示すように、搭載部７０
毎に絶縁樹脂層６２と支持基板５０を切断して各々の半
導体素子に分離する。切断にはダイシング装置を用い、
ダイシングライン７１に沿って絶縁樹脂層６２と支持基
板５０とをダイシングブレード８５で同時に切断するこ
とにより、搭載部７０毎に分割した半導体装置を形成す
る。この工程で切断された接続部７２，７３の残りが、
図１で示した接続部７２、７３である。ダイシング工程
においては支持基板５０の裏面側にブルーシート（たと
えば、商品名：ＵＶシート、リンテック株式会社製）を
貼り付け、前記ダイシングブレードがブルーシートの表
面に到達するような切削深さで切断する。Further, as shown in FIG.
Each time, the insulating resin layer 62 and the support substrate 50 are cut and separated into respective semiconductor elements. Use a dicing device for cutting,
By simultaneously cutting the insulating resin layer 62 and the supporting substrate 50 with the dicing blade 85 along the dicing line 71, a semiconductor device divided for each mounting portion 70 is formed. The remaining connection parts 72 and 73 cut in this step are
These are the connection parts 72 and 73 shown in FIG. In the dicing process, a blue sheet (for example, trade name: UV sheet, manufactured by Lintec Corporation) is attached to the back surface of the support substrate 50, and cut at a cutting depth such that the dicing blade reaches the surface of the blue sheet. .

【００４０】図８は、上述の工程によって形成された各
半導体素子を示す斜視図である。FIG. 8 is a perspective view showing each semiconductor element formed by the above-described steps.

【００４１】[0041]

【発明の効果】本発明によれば、第１に２枚の導電箔５
２、５３と導電材５７で各電極を形成するので、従来用
いていたタングステン等の高価な金属ペーストが不要と
なり、極めて安価な実装構造を実現できる利点を有す
る。また導電箔５２，５３として銅箔を用いると電気抵
抗も低くでき、飽和オン抵抗も大幅に改善できる。According to the present invention, first, two conductive foils 5 are formed.
Since each electrode is formed by the electrodes 2 and 53 and the conductive material 57, an expensive metal paste such as tungsten conventionally used is not required, and there is an advantage that an extremely inexpensive mounting structure can be realized. When copper foil is used as the conductive foils 52 and 53, the electric resistance can be reduced, and the saturation on-resistance can be greatly improved.

【００４２】第２に２枚の導電箔５２，５３の層間絶縁
膜として熱可塑性樹脂フィルム５１を用いているので、
ビアホールの形成やスルーホールメッキ等を不要にで
き、導電材５７を熱可塑性樹脂フィルム５１を熱圧着時
に貫通させるだけで両導電箔５２，５３で形成した各電
極を電気的に接続できる極めて簡単な実装構造を提供で
きる。このためにノンハロゲン、スルーホールめっきレ
スで極めて環境に優しい実装構造となる。Second, since the thermoplastic resin film 51 is used as an interlayer insulating film between the two conductive foils 52 and 53,
The formation of via holes and through-hole plating can be eliminated, and the electrodes formed by the conductive foils 52 and 53 can be electrically connected only by penetrating the conductive material 57 at the time of thermocompression bonding of the thermoplastic resin film 51. Provide mounting structure. For this reason, a non-halogen, no through-hole plating and extremely environmentally friendly mounting structure is obtained.

【００４３】第３に本発明の支持基板５０は銅箔が約１
２μｍ、熱可塑性樹脂フィルム５１が約５０μｍで形成
されるので、全体では厚みが高々７５μｍにでき、従来
のセラミック基板の厚みがセラミックだけで０．２５ｍ
ｍから０．３５ｍｍもあり、約１／５に薄型化できる利
点を有する。このため完成された半導体装置の薄型化に
も大いに貢献でき、１ｍｍ×１ｍｍ以下の極めて微細な
トランジスタチップ等の実装構造には最適である。Third, the supporting substrate 50 of the present invention has a copper foil of about 1
Since the thickness of the thermoplastic resin film 51 is about 50 μm, the thickness can be as high as 75 μm as a whole.
m to 0.35 mm, which is advantageous in that the thickness can be reduced to about 1/5. For this reason, it can greatly contribute to the reduction in thickness of the completed semiconductor device, and is most suitable for a mounting structure of an extremely fine transistor chip of 1 mm × 1 mm or less.

【００４４】第４に本発明で用いた熱可塑性樹脂フィル
ム５１は、高周波領域における誘電率はポリイミド樹脂
と同じであり、また表面抵抗はガラスエポキシ基板と同
等であり、良好な高周波特性を得られる。Fourth, the thermoplastic resin film 51 used in the present invention has the same dielectric constant in the high-frequency region as that of the polyimide resin, and has the same surface resistance as that of the glass epoxy substrate, so that good high-frequency characteristics can be obtained. .

【００４５】第５に本発明で用いた熱可塑性樹脂フィル
ム５１は、熱可塑性による軟質さを有しているので、ポ
リイミド樹脂以上に耐折性に優れているので、微細幅の
配線でも断線する確率が極めて低く、各電極の微細化に
最適である。Fifth, since the thermoplastic resin film 51 used in the present invention has softness due to thermoplasticity and is more excellent in folding resistance than polyimide resin, it breaks even in a wiring having a fine width. The probability is extremely low, and it is optimal for miniaturization of each electrode.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体装置を説明する（Ａ）平面図、
（Ｂ）断面図、（Ｃ）裏面図である。FIG. 1A is a plan view illustrating a semiconductor device of the present invention,
(B) is a sectional view, (C) is a back view.

【図２】本発明に用いる支持基板を説明する（Ａ）平面
図、（Ｂ）裏面図である。FIGS. 2A and 2B are a plan view and a rear view illustrating a support substrate used in the present invention. FIGS.

【図３】本発明の半導体装置の製造方法を説明する断面
図である。FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

【図４】本発明の半導体装置の製造方法を説明する断面
図である。FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

【図５】本発明の半導体装置の製造方法を説明する断面
図である。FIG. 5 is a sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;

【図６】本発明の半導体装置の製造方法を説明する断面
図である。FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

【図７】本発明の半導体装置の製造方法を説明する断面
図である。FIG. 7 is a sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;

【図８】本発明の半導体装置を説明する斜視図である。FIG. 8 is a perspective view illustrating a semiconductor device of the present invention.

【図９】従来の半導体装置を説明する断面図である。FIG. 9 is a cross-sectional view illustrating a conventional semiconductor device.

【図１０】従来の半導体装置を説明する（Ａ）平面図
（Ｂ）断面図（Ｃ）斜視図である。10A is a plan view, FIG. 10B is a cross-sectional view, and FIG. 10C is a perspective view illustrating a conventional semiconductor device.

【図１１】従来の半導体装置を説明する（Ａ）平面図
（Ｂ）断面図（Ｃ）裏面図である。11A is a plan view, FIG. 11B is a cross-sectional view, and FIG.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 兵藤 治雄 大阪府守口市京阪本通２丁目５番５号 三 洋電機株式会社内 Ｆターム(参考） 5F061 AA01 BA03 CA04 CB13  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Haruo Hyodo 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term in Sanyo Electric Co., Ltd. 5F061 AA01 BA03 CA04 CB13

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】 熱可塑性樹脂で離間された相対向する導
電箔を有し、一方の導電箔を所望形状に形成された固着
電極および取り出し電極を設け、他方の導電箔で形成さ
れた前記固着電極および取り出し電極に対応して対向す
る接続電極を設け、かつ前記固着電極および取り出し電
極と対応する前記接続電極とを電気的に接続し前記熱可
塑性樹脂を貫通する導電材とを有する支持基板と、 前記固着電極上に固着された半導体素子と、 前記半導体素子の電極と前記取り出し電極とを接続する
ボンディング細線と、 前記接続電極を露出して前記半導体素子、固着電極、取
り出し電極および前記ボンディング細線を少なくとも被
覆する絶縁樹脂とを具備することを特徴とした半導体装
置。1. A fixed electrode and a take-out electrode having opposing conductive foils separated by a thermoplastic resin, one of the conductive foils being formed in a desired shape, and the fixing being formed by the other conductive foil. A supporting substrate having a connection electrode facing the electrode and the extraction electrode, and a conductive material that electrically connects the fixed electrode and the extraction electrode and the corresponding connection electrode and penetrates the thermoplastic resin; A semiconductor element fixed on the fixed electrode; a bonding thin wire connecting the electrode of the semiconductor element and the extraction electrode; and the semiconductor element, the fixed electrode, the extraction electrode, and the bonding thin wire exposing the connection electrode. And an insulating resin for covering at least the semiconductor device. 【請求項２】 前記導電箔として銅箔を用いたことを特
徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a copper foil is used as said conductive foil. 【請求項３】 前記銅箔表面をニッケルおよび金のメッ
キ層で被覆することを特徴とする請求項２記載の半導体
装置。3. The semiconductor device according to claim 2, wherein said copper foil surface is covered with a nickel and gold plating layer. 【請求項４】 前記熱可塑性樹脂として液晶ポリマーを
用いたことを特徴とする請求項１記載の半導体装置。4. The semiconductor device according to claim 1, wherein a liquid crystal polymer is used as said thermoplastic resin. 【請求項５】 前記導電材として銀ペーストを用いたこ
とを特徴とする請求項１記載の半導体装置。5. The semiconductor device according to claim 1, wherein a silver paste is used as said conductive material. 【請求項６】 熱可塑性樹脂で離間された相対向する導
電箔を有し、一方の導電箔を所望形状に形成された固着
電極および取り出し電極を設け、他方の導電箔で形成さ
れた前記固着電極および取り出し電極に対応して対向す
る接続電極を設け、かつ前記固着電極および取り出し電
極と対応する前記接続電極とを電気的に接続し前記熱可
塑性樹脂を貫通する導電材とを有する支持基板と、 前記固着電極上に固着された半導体素子と、 前記半導体素子の電極と前記取り出し電極とを接続する
ボンディング細線と、 前記接続電極を露出して前記半導体素子、固着電極、取
り出し電極および前記ボンディング細線を少なくとも被
覆する絶縁樹脂とを具備する半導体装置であって、 前記ボンディング細線の一端は前記接続電極と重なる前
記取り出し電極上に固着されることを特徴とする半導体
装置。6. A fixed electrode and a take-out electrode, each having a conductive foil facing each other and separated by a thermoplastic resin, wherein one of the conductive foils is provided with a fixed electrode and a lead-out electrode, and the other is formed by the other conductive foil. A supporting substrate having a connection electrode facing the electrode and the extraction electrode, and a conductive material that electrically connects the fixed electrode and the extraction electrode and the corresponding connection electrode and penetrates the thermoplastic resin; A semiconductor element fixed on the fixed electrode; a bonding thin wire connecting the electrode of the semiconductor element and the extraction electrode; and the semiconductor element, the fixed electrode, the extraction electrode, and the bonding thin wire exposing the connection electrode. An insulating resin that covers at least one of the bonding wires, wherein one end of the bonding thin wire overlaps with the connection electrode. Wherein a is secured to the upper. 【請求項７】 前記ボンディング細線の一端は前記接続
電極および前記導電材と重なる前記取り出し電極上に固
着されることを特徴とする請求項６記載の半導体装置。7. The semiconductor device according to claim 6, wherein one end of said bonding thin wire is fixed on said connection electrode and said extraction electrode overlapping with said conductive material. 【請求項８】 前記固着電極は少なくとも前記半導体素
子が載置される大きさに形成され、それと対応する前記
接続電極は前記固着電極より小さく形成され、前記半導
体素子は少なくとも半分以上が前記接続電極と重なるよ
うに前記固着電極上に固着されることを特徴とする請求
項６から８記載の半導体装置。8. The fixed electrode is formed at least in a size on which the semiconductor element is mounted, and the connection electrode corresponding to the fixed electrode is formed smaller than the fixed electrode, and the semiconductor element has at least half or more of the connection electrode. 9. The semiconductor device according to claim 6, wherein said semiconductor device is fixed on said fixed electrode so as to overlap with said fixed electrode. 【請求項９】 前記固着電極の前記半導体素子が載置さ
れた下に前記導電材を設けたことを特徴とする請求項８
記載の半導体装置。9. The conductive material is provided under the fixed electrode on which the semiconductor element is mounted.
13. The semiconductor device according to claim 1.
JP36595499A 1999-12-24 1999-12-24 Semiconductor device Pending JP2001185646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP36595499A JP2001185646A (en) 1999-12-24 1999-12-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP36595499A JP2001185646A (en) 1999-12-24 1999-12-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2001185646A true JP2001185646A (en) 2001-07-06

Family

ID=18485546

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196390A (en) * 2000-01-11 2001-07-19 Sanyo Electric Co Ltd Method of manufacturing semiconductor device
KR100439407B1 (en) * 2002-04-11 2004-07-09 삼성전기주식회사 Method of producing a semiconductor device package
KR100455698B1 (en) * 2002-03-07 2004-11-06 주식회사 케이이씨 chip size package and its manufacturing method
JP2007266544A (en) * 2006-03-30 2007-10-11 Koa Corp Composite electronic component manufacturing method, and composite electronic component

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196390A (en) * 2000-01-11 2001-07-19 Sanyo Electric Co Ltd Method of manufacturing semiconductor device
KR100455698B1 (en) * 2002-03-07 2004-11-06 주식회사 케이이씨 chip size package and its manufacturing method
KR100439407B1 (en) * 2002-04-11 2004-07-09 삼성전기주식회사 Method of producing a semiconductor device package
JP2007266544A (en) * 2006-03-30 2007-10-11 Koa Corp Composite electronic component manufacturing method, and composite electronic component

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