JP2001184896A - Random access memory of packet system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means capable of preventing disappearance of stored data of a memory cell during a discrimination period of output data even when a burn-in test is performed using a test device of low speed, for a DRAM operated by a packet system at high speed. SOLUTION: A DRAM 1 of a packet, system operated with an operation frequency of several hundreds MHz is provided with a burn-in mode in which a memory test is performed with an operation frequency of several tens MHZ at the time of a burn-in test. And at the time of a burn-in test, independently of a normal self-refresh instruction of a packet form outputted from a logic circuit 2, a memory cell of a memory cell array 7 is refreshed by a ring oscillator circuit 4, an address counter circuit 5, and a RAS logic circuit 6 based on a self-refresh signal outputted from a timing detecting circuit 8, and disappearance of stored data of a memory cell is prevented during a discrimination period of output data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet type dynamic random access memory which operates at a high operating frequency at a high operating frequency by a packet type instruction, and particularly has a low operation at burn-in. The present invention relates to a packet type dynamic random access memory having a burn-in mode for performing a memory test at a frequency.

[0002]

2. Description of the Related Art A dynamic random access memory (hereinafter, referred to as "DRAM") has a small area occupied by each memory cell and is suitable for high integration. Therefore, it is widely used as a memory device for various electronic devices such as personal computers. Used. As such a DRAM, an EDO-DR having an operating frequency of several tens of MHz has been conventionally used.
AM (Extended data-out DRAM) and the like are widely used.

However, in recent years, for example, in personal computers and the like, with the increase in the speed of the operation of the CPU, the speed of the access operation of the DRAM used as the memory device has been required. Thus, in recent years, a synchronous DRAM having an operation frequency of 100 to 200 MHz has appeared, and more recently, a Rambus DRAM (Rambus DRAM) or a sync link DRAM (operation frequency of several hundred MHz) which operates at a high speed by a packet method (Packet method). SyncLink DRAM) has also appeared.

However, in a DRAM, the electric charge stored in each memory cell attenuates with the passage of time.
If you leave the data after storing it in the memory cell,
Eventually, the stored data is lost. So, DRA
In M, in order to prevent such loss of stored data,
It is necessary to appropriately perform a refresh operation (rewrite) such as re-injecting charges into the memory cells.

Thus, in a DRAM which operates at a high speed by a packet method, for example, a Rambus DRAM or a sync link DRAM, a self refresh (internal refresh) operation is usually performed by designating an operation mode by a packet format instruction. Specifically, each memory cell in the memory array is refreshed by a ring oscillator circuit, an address counter circuit, an RAS logic circuit, or the like, based on a self-refresh request signal output from a logic circuit, for example. In such a DRAM, in order to output a self-refresh request signal to the logic circuit, it is necessary to apply a packet command to the logic circuit at an operating frequency of several hundred MHz.

[0006] Generally, in a DRAM,
Various tests are performed to check the performance or quality. Burn-in is performed to stabilize the characteristics. The burn-in is a process of operating the DRAM for a certain period of time before actually using the DRAM to improve the familiarity or stabilize the operation characteristics. At the time of burn-in, a burn-in test for inspecting the performance or quality of the DRAM is performed by using, for example, a testing burn-in device or a burn-in device.

Here, when performing a burn-in test on a DRAM operating at high speed by a packet method, for example, a Rambus DRAM or a sync link DRAM, a clock generator or a pattern generator for generating a complicated packet code of several hundred MHz is originally required. Becomes Nevertheless, in reality, such a DRAM
Also, a special test mode called a "DA mode" for testing a memory cell area at a low operation frequency of about several tens of MHz like a normal EDO-DRAM or the like is built in. This is because there is a consideration that a relatively low-speed testing burn-in device conventionally used by a memory maker or the like can be continuously used.

[0008]

By the way, in the conventional low-speed testing burn-in apparatus,
It takes time to determine the output data of the DRAM to be tested, and it may take several hundred ms at the longest.
On the other hand, in a conventional DRAM having a built-in DA mode and operating at high speed by a packet method, the refresh operation cannot be performed when the output data is actually determined.

Therefore, when a low-speed ordinary testing burn-in device is used for a DRAM operating at a high speed by the packet method, the time required to determine the output data is equal to the data holding time of the memory cell (data refresh without performing refresh). May be exceeded), which may make it impossible to hold data accurately. For this reason, D which operates at high speed by the packet method is used.
The RAM has a problem that an ordinary testing burn-in device cannot be used or that the testing burn-in device must be modified at a high cost.

Japanese Patent Application Laid-Open No. Hei 6-119780 discloses a semiconductor memory in which a refresh operation can be arbitrarily controlled by a test mode signal at the time of self-refresh. However, in this semiconductor memory, refresh is stopped by a test mode signal, and even if the refresh method used in this semiconductor memory is used, a DRAM which operates at a high speed by a packet method has a lower speed than a normal memory. When a Sting burn-in device is used, data cannot be held accurately.

Generally, in a testing burn-in apparatus, a large number of D
A RAM chip is mounted, one output data determiner (comparator, comparator) is connected to a series of DRAM chips, and the one output data determiner sequentially tests each DRAM chip. . For example, when determining whether the output of the DRAM chip (hereinafter, referred to as a “determination target DRAM chip”) that is a target of the output data determination is “H (High)”, whether or not only the determination target DRAM chip is correct. H, the other DRAM chips are set to “L (Low)”, and the determination is performed on the determination target DRAM chip. In this case, the determination target D
Since the output of the RAM chip and the output of other DRAM chips interfere with each other (collide with each other), the test program is executed while appropriately correcting the determination potential based on an experimental value.

However, in this case, since a mutual current flows between the DRAM chips, the
There is a problem that the chip may be damaged. Further, a plurality of DRs sharing one output data decision unit
If one of the AM chips is not normal, all D
There is also a problem that erroneous determination occurs for the RAM chip.

Japanese Patent Application Laid-Open No. 7-99435 discloses that
When a large number of CMOS output buffers are connected to one bus, when a plurality of output buffers are selected, mutual current does not flow between the output buffers and the floating of the bus is prevented. A disclosed bus drive system is disclosed. However, in the method of preventing mutual current used in this bus drive system, at the time of burn-in test, each DRA
Mutual current cannot be prevented from flowing between the M chips.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problem. Even when a burn-in test is performed on a DRAM operating at a high speed by a packet method using a low-speed test device, the output is reduced. It is an object to provide a means for preventing loss of data stored in a memory cell during a data determination period. Further, a plurality of DRAs are output by one output data decision unit.
It is an object of the present invention to provide a means capable of preventing a mutual current from flowing between DRAM chips even when output data is sequentially determined for M chips.

[0015]

A packet type DRAM (for example, a Rambus DRAM, a sync link D) according to a first aspect of the present invention has been made to solve the above problems.
The RAM or the like operates at a high operating frequency (for example, several hundred MHZ) by a packet format instruction, and has a burn-in mode for performing a memory test at a lower operating frequency (for example, several tens of MHz) at the time of burn-in. When the memory test is performed at least in the burn-in mode,
Instructions in packet format (including normal refresh instructions)
Independently, a self-refresh means for refreshing a memory cell based on an internal clock signal is provided.

The packet type DRA according to the first aspect
In M, when the memory test is performed in the burn-in mode, each memory cell is refreshed by the self-refresh means based on the internal clock signal independently of the packet format instruction. Therefore, even if it takes a long time to judge the output data of the DRAM to be tested, each memory cell is refreshed at an appropriate timing during this time. No data is lost.

The packet type DRAM according to the second aspect of the present invention is the DRAM according to the first aspect,
When a signal corresponding to a column address strobe (hereinafter, referred to as “zCAS”) signal is activated prior to a signal corresponding to a row address strobe (hereinafter, referred to as “zRAS”) signal by the self-refresh means. , In which the memory cells are refreshed. In this specification,
Symbols representing various signals (for example, zCAS, zRA
“Z” added to the head of S) means that the symbol is low active or that the symbol is NOT.

The DRA of the packet system according to the second aspect
In M, the DRA according to the first aspect is basically
The same operation as in the case of M occurs. Further, since the memory cell is refreshed by using the signal corresponding to the zCAS signal and the signal corresponding to the zRAS signal, which is an internal signal, the configuration of the self-refresh means is simplified.

A packet type DRAM according to a third aspect of the present invention is the DRAM according to the first or second aspect, wherein a predetermined internal signal (for example, an ENABLE signal,
zENABLE), a signal output unit impedance switching means capable of making the impedance of the signal output unit higher than usual.

The packet type DRA according to the third aspect
In M, basically the same operation as in the case of the DRAM according to the first or second aspect occurs. Further, the impedance of the signal output unit can be arbitrarily increased based on the internal signal.
When M (DRAM chip) is mounted and the output data of one DRAM is sequentially judged by a single output data judging device, the signal output section of the DRAM to be judged has a normal impedance while the signals of other DRAMs are set. By setting the output section to have a high impedance, it is possible to prevent a mutual current from flowing between the DRAMs, and to prevent the DRAM chips from being damaged. Even if a plurality of DRAMs sharing one output data determiner are not normal, no erroneous determination occurs in the other DRAMs.

A packet-type DRAM according to a fourth aspect of the present invention is the DRAM according to the third aspect,
A first CMO to which an internal output signal is input;
An output buffer circuit comprising: an S (complementary MOS) inverter; and a second CMOS inverter to which an output signal of the first CMOS inverter is input and an external output signal corresponding to an internal output signal is output to the outside. Wherein the signal output unit impedance switching means electrically connects the output terminal of the first CMOS inverter and the input terminal of the second CMOS inverter when the predetermined internal signal is in the first state. On the other hand, when the internal signal is in the second state, the impedance of the output buffer circuit is increased by turning off the p-channel MOS transistor and the n-channel MOS transistor constituting the second CMOS inverter. It is characterized by the following.

The packet type DRA according to the fourth aspect
In M, the DRA according to the third aspect is basically
The same operation as in the case of M occurs. In addition, the first and second
In an ordinary output buffer circuit in which CMOS inverters are connected in series, a p-channel MOS transistor and an n-channel M
The impedance of the output buffer circuit can be switched simply by interposing a simple signal output unit impedance switching means formed by combining OS transistors.

The packet type DRAM (for example, Rambus DRAM, Sync Link DRAM, etc.) according to the fifth aspect of the present invention operates at a high operating frequency (for example, several hundred MHz) by a packet format instruction. Characterized by being provided with a signal output section impedance switching means capable of increasing the impedance of a signal output section based on a predetermined internal signal, based on a predetermined internal signal. It is.

The packet type DRA according to the fifth aspect
In M, since the impedance of the signal output section can be arbitrarily increased based on the internal signal, for example, at the time of a burn-in test, a plurality of DRAMs are mounted on a testing burn-in device and a single output data decision unit is used. When sequentially judging the output data of a plurality of DRAMs, the signal output section of the DRAM to be judged has a normal impedance while the signal output sections of the other DRAMs have a high impedance, so that the mutual current between the DRAMs can be increased. Can be prevented from flowing, and the DRAM can be prevented from being damaged. Even if a plurality of DRAMs sharing one output data determiner are not normal, no erroneous determination occurs in the other DRAM chips.

A packet type DRAM according to a sixth aspect of the present invention is the packet type DRAM according to the fifth aspect of the present invention, wherein the signal output section has a first CMOS inverter to which an internal output signal is input. And the first CM
A second CM to which an output signal of the OS inverter is input and an external output signal corresponding to the internal output signal is output to the outside
An output buffer circuit including an OS inverter, wherein the signal output unit impedance switching means outputs the first CM when the predetermined internal signal is in the first state.
While the output terminal of the OS inverter is electrically connected to the input terminal of the second CMOS inverter, when the internal signal is in the second state, the p-channel MOS transistor and the n-channel MOS transistor forming the second CMOS inverter The feature is that the impedance of the output buffer circuit is increased by turning off the MOS transistor.

The packet type DRA according to the sixth aspect
In M, the DRA according to the fifth aspect is basically
The same operation as in the case of M occurs. In addition, the first and second
In an ordinary output buffer circuit in which CMOS inverters are connected in series, a p-channel MOS transistor and an n-channel M
The impedance of the output buffer circuit can be switched simply by interposing a simple signal output unit impedance switching means formed by combining OS transistors.

[0027]

Embodiments of the present invention will be described below. FIG. 1 shows a packet-type DRAM (eg, a DRAM) operating at a high speed (eg, several hundred MHz) according to the present invention.
FIG. 2 is a block diagram of a portion related to a refresh operation of a RAM bus DRAM and a sync link DRAM. As shown in FIG. 1, a DRAM 1 includes a logic circuit 2, an OR circuit 3, a ring oscillator circuit 4, an address counter circuit 5, an RAS logic circuit 6 (an internal RAS signal control circuit), a memory array 7, , Timing detection circuit 8
(Internal signal timing detection circuit).

Here, the logic circuit 2 outputs various signals or instructions including the self-refresh request signal RFSH-EN (see FIG. 2) to the OR circuit 3 in a packet format. In the DRAM 1, during normal operation, each memory cell (not shown) in the memory array 7 is refreshed based on the self-refresh request signal RFSH-EN output from the logic circuit 2. I have. As will be described in detail later, when performing a burn-in test using a low-speed or low-frequency testing burn-in device, a self-refresh request signal zCBR (see FIG. 5) output from the timing detection circuit 8 is used. Thus, each memory cell in the memory array 7 is refreshed.

At the time of normal refresh, self-refresh request signal R output from logic circuit 2
The FSH-EN is input to the ring oscillator 4 and the RAS logic circuit 6 via the OR circuit 3. On the other hand, at the time of the burn-in test, the self-refresh request signal zCBR output from the timing detection circuit 8 is input to the ring oscillator 4 and the RAS logic circuit 6 via the OR circuit 3. And the ring oscillator circuit 4
Is the self-refresh request signal RFSH-EN or z
When the CBR is input, a predetermined pulse signal φ (clock signal) is output to the address counter circuit 5 and the RAS logic circuit 6.

As shown in FIG. 2, the ring oscillator circuit 4 is substantially a p-channel MOS transistor P1
To P17 and n-channel MOS transistors N1 to N
17, inverters I1 to I7, and NAND gate NA
1 is an oscillation circuit. The ring oscillator circuit 4 always generates a predetermined pulse signal φ, and the pulse signal φ is input to one input terminal of the NAND gate NA1. Thus, when the self-refresh request signal RFSH-EN is input to the inverter I12, the signal is output to the NAND through the inverter I3.
The signal is input to the other input terminal of the gate NA1. At this time, the pulse signal φ is changed to the address counter circuit 5 and R by the operation of the NAND gate NA1 and the inverter I7.
The signal is output to the AS logic circuit 6.

As shown in FIG. 3, the address counter circuit 5 substantially comprises inverters I11 to I21 and AND
This is a counter circuit including a NOR gate IA1, a NAND gate NA8, and an AND / NOR composite gate AO1 using a circuit. This address counter circuit 5
Counts up the output nodes based on the pulse signals φ to zφ input from the ring oscillator circuit 4. That is, the address of the memory cell to be refreshed is specified. The reset signals RESET are supplied to the inverters I20 to I21 of the address counter circuit 5.
And count enable signal zCNTE are input.
The count enable signal zCNTE is a signal that permits counting (count enable) when the signal is low and inhibits (skips) counting when the signal is high.

As shown in FIG. 4, the RAS logic circuit 6
Are inverters I31 to I42 and a NAND gate NA
2 to NA5 and NAND gate IO using OR circuit
1 to IO4 and NOR gate IA using AND circuit
2 is a control circuit. The RAS logic circuit 6 converts a self-refresh request signal RFSH-EN (or zCBR) received from the logic circuit 2 (or the timing circuit 8) via the OR circuit 3 and a pulse signal φ received from the ring oscillator circuit 4. Based on this, a refresh execution signal RFSH is output to the memory array 7. Thus, the memory cells in the memory array 7 specified by the address counter circuit 5 are refreshed. The RAS logic circuit 6 is reset when a reset signal SCPD or zPOR is input.

As shown in FIG. 5A, the timing detection circuit 8 substantially includes inverters I51 to I52 and N
This is a circuit composed of AND gates NA6 and NA7. The RAS equivalent signal zRASF is input to the inverter I51 of the timing detection circuit 8, and the inverter I5
2, the CAS equivalent signal zCASFM is input. Here, the RAS equivalent signal zRASF is an internal clock signal corresponding to the zRAS signal, and the CAS equivalent signal zCAS.
FM is an internal clock signal corresponding to the zCAS signal.

As shown in FIG. 5B, both input signals zRASF and zCASFM are H (High).
In the state where the self-refresh request signal zCBR output from the output terminal of the NAND gate NA7 is H (hereinafter, referred to as a "first input state"),
The AS equivalent signal zRASF becomes L (Low) and is activated (hereinafter, referred to as “second input state”), and thereafter CA
It is assumed that the S equivalent signal zCASFM has become L (hereinafter, referred to as “L”).
This is referred to as a “third input state”. ). In this case, the self-refresh request signal zCBR output from the output terminal of the NAND gate NA7 maintains H.

That is, in the first input state, H is input from both the zRASF side and L is input from the zCASFM side to both input terminals of the NAND gate NA7. When the second input state is established, the signal input from the zRASF side to the input terminal of the NAND gate NA7 changes from H to L. In this case, the output of the NAND gate NA does not change at all, and H is changed to H. maintain. Thereafter, when the state becomes the third input state, the NAND from the zCASFM side is set.
The signal input to the input terminal of the gate NA7 changes from L to H, but also in this case, the output of the NAND gate NA does not change at all and maintains H.

On the other hand, as shown in FIG. 5C, it is assumed that the CAS equivalent signal zCASFM first becomes L from the first input state (hereinafter, referred to as a "fourth input state"). In this case, the self-refresh signal zCBR output from the output terminal of the NAND gate NA7 changes from H to L. After that, even if the RAS equivalent signal zRASF becomes L (third state), the self-refresh signal zCBR output from the output terminal of the NAND gate NA7 is
Maintain L.

That is, in the first input state, H is input to both input terminals of the NAND gate NA7 from the zRASF side, and L is input to the zCASFM side. In the fourth input state, the signal input from the zCASFM side to the input terminal of the NAND gate NA7 changes from L to H.
Since H is input to both input terminals of N7, the N
The output of the AND gate NA7 changes from H to L. Thereafter, when the third input state is set, NRAS from the zRASF side
Since the signal input to the input terminal of the AND gate NA7 maintains H, the output of the NAND gate NA7 does not change at all and maintains L.

Thus, in DRAM 1, self-refresh request signal z output from timing detection circuit 8 is independent of self-refresh request signal RFSH-EN output from logic circuit 2 in packet form.
Refresh is performed by CBR.

That is, in the DRAM 1 of the packet system in which the self-refresh operation was originally performed only by designating the operation mode of the packet format, the memory cell array can be operated even at a low or low frequency (for example, several tens of MHz) clock input. In addition to the selectable burn-in mode (DA mode), the internal address counter is periodically counted up, and the memory cell at the address corresponding to the counter output is refreshed.

That is, in the conventional packet-type DRAM, only the self-refresh request signal RFSH-EN from the logic circuit 2 is used, and the built-in ring oscillator circuit 4 is used.
(Timer), the address counter circuit 5, and the RAS logic circuit 6 refresh each memory cell in the memory array 7. At this time, to output the self-refresh request signal RFSH-EN from the logic circuit 2,
Packet instruction with clock of several hundred MHz
Must be entered.

On the other hand, a testing burn-in apparatus or a burn-in apparatus normally generates an electrically accurate clock by the continuous operation of about several tens of hours due to the property of accelerating an initial failure mainly due to a manufacturing defect. No need. Therefore, it is designed and manufactured so that a large number of DRAMs (devices) can be tested at one time. Therefore, the clock accuracy of a normal testing burn-in device is usually about several tens of MHz, and it is almost impossible to generate a high-speed and complicated packet command. Therefore, in the conventional testing burn-in apparatus or burn-in apparatus, the self-refresh function built into the DRAM cannot be used by the packet command. Therefore, if a test pattern whose determination time exceeds the data holding time of the product is used, correct determination is impossible.

Therefore, in the DRAM 1 according to the present invention,
In order to solve such a problem, for example, EDO-DRA
Like the CBR (CAS before RAS) refresh provided in M and the like, a built-in self-refresh function is activated based on an input sequence and a time difference between predetermined specific signals. Thus, in the present embodiment, following the CBR refresh of the EDO-DRAM, the RAS equivalent signal zRASF and the CAS equivalent signal zC
Using ASFM, the CAS equivalent signal zCASFM is RA
Self-refresh is performed at a timing activated prior to the S equivalent signal zRASF.

That is, in the burn-in test of the DRAM 1, when the read operation and the output data determination are completed, if the above timing is set, the self-refresh function operates, and the determination period exceeds the data holding time of the DRAM 1. Even when such a testing burn-in device is used, stored data is not lost or destroyed. Therefore, even when using a testing burn-in device in which the output determination time during the test of the DRAM 1 exceeds the data holding time, the stored data can be held without being lost, and the pass / fail can be correctly obtained. ) Can be determined. Therefore,
A conventional testing burn-in device can be used without modification.

Further, a plurality of DRAMs 1 are mounted on this DRAM 1 in a testing burn-in device, and a plurality of DRs are output by one comparator (output data judgment comparator).
An impedance control circuit that can arbitrarily increase the impedance of a signal output unit based on a predetermined internal signal so as to prevent a mutual current from flowing between DRAMs when sequentially determining output data for AM1. Is provided. Hereinafter, a specific configuration and function of the impedance control circuit will be described.

FIG. 6 is a circuit diagram of an output buffer circuit of the DRAM 1 provided with the impedance control circuit according to the present invention. As shown in FIG. 6, the output buffer circuit includes p-channel MOS transistors P24 and n
First composed of channel MOS transistor N24
A CMOS inverter and a second CMOS inverter including a p-channel MOS transistor P21 and an n-channel MOS transistor N21 are provided. Here, the first CMOS inverter includes the DRAM 1
(A logical output signal to be output from the DRAM) is input via an input terminal 10. Further, an electrical external output signal corresponding to the internal output signal is output from the second CMOS inverter via the output terminal 11 to the outside.

Then, the first MOS inverter and the second MO
P-channel MOS transistors P22 to P23, n-channel MOS transistors N22 to N23, a first internal terminal 12 for receiving an ENABLE signal, and a second internal terminal 13 for receiving a zENABLE signal are provided between the S inverter. An impedance control circuit is provided. This impedance control circuit is configured to enable ENABLE applied to the first internal terminal 12.
When the signal is H, and therefore the zENABLE signal applied to the second internal terminal 13 is L, the first CM
The output terminal of the OS inverter is electrically connected to the input terminal of the second CMOS inverter.

That is, in this case, the p-channel MO
While the S transistor P22 and the n-channel MOS transistor N22 are turned on, the p-channel MOS
This is because the transistor P23 and the n-channel MOS transistor N23 are turned off, so that the impedance control circuit is equivalent to a simple conductor, and is in the same state as when no impedance control circuit is provided.

On the other hand, in the impedance control circuit, when the ENABLE signal input to the first internal terminal 12 is L,
When the ENABLE signal is H, the p-channel MOS transistor P constituting the second CMOS inverter
By turning off the N-channel MOS transistor 21 and the n-channel MOS transistor N21, the impedance of the output buffer circuit is increased.

That is, in this case, the p-channel MO
While the S transistor P22 and the n-channel MOS transistor N22 are turned off, the p-channel MOS
The transistor P23 and the n-channel MOS transistor N23 are turned on. Therefore, p channel M
The OS transistor P21 is turned off because its gate is connected to the power supply via the p-channel MOS transistor P23. On the other hand, the n-channel MOS transistor N21 is turned off because its gate is connected to the ground via the n-channel MOS transistor N23. Thus, the output buffer circuit enters a high impedance state.

In other words, the output buffer circuit can freely switch its impedance between high and low by switching H and L of ENABLE and zENABLE signals applied to both internal terminals 12 and 13 of the impedance control circuit.

Hereinafter, a test method in a burn-in test of the DRAM 1 using an ordinary testing burn-in device will be described. As shown in FIG. 7, when performing the burn-in test of the DRAM 1, a large number of DRAMs 1 are arranged in a two-dimensional array in the X direction and the Y direction on the board of the testing burn-in device 14. In the testing burn-in device 14, the output terminals of the plurality of DRAMs 1 arranged in one row in the Y direction
Connected to one comparator 16 (output determination comparator). That is, in the testing burn-in device 14, one comparator 16 is shared by a plurality of DRAMs 1 in each column in order to reduce the cost of the burn-in test.

Thus, in the testing burn-in device 14, a burn-in test of the DRAM 1 is performed for each array. In this case, first, a plurality of DRAMs belonging to the array are tested.
Write Distur to RAM1
b) The processing is performed, and thereafter, each DR
Data reading and data determination are sequentially performed for AM1.

When the burn-in test is performed as described above, in the conventional DRAM, as described above, the data other than the DRAM to be determined is set to the data opposite to that of the DRAM to be determined, and for example, the H output of the DRAM to be determined is determined. Are testing with other DRAMs set to L output. However, in this case, a mutual current flows between the DRAMs, and in some cases, the DRAMs may be damaged,
If there is at least one abnormal DRAM in the array, erroneous determination will occur in all DRAMs in the array.

Therefore, in the DRAM 1 according to the present invention,
When performing a burn-in test for each array,
For the DRAM 1 other than the AM1, the first internal terminal 12
By setting the ENABLE signal to be applied to L to L and the zENABLE signal to be applied to the second internal terminal 13 to H, the output buffer circuit is made high impedance,
A mutual current is prevented from flowing between the DRAMs 1 (OUT = Hi-Z). The DRA to be determined
For M1, ENAB applied to the first internal terminal 12
By setting the LE signal to H and the zENABLE signal applied to the second internal terminal 13 to L, the output signal of the DRAM 1 to be determined is output to the conductor 15 (IN →
OUT).

As described above, in the DRAM 1 according to the present invention, at the time of the burn-in test, the DRAM to be determined is
One output buffer circuit has a normal impedance, while the other output buffer circuits of the DRAM 1 have a high impedance, thereby preventing a mutual current from flowing between the DRAMs 1 and preventing the DRAM 1 from being damaged. Can be prevented. Also, even if a plurality of DRAMs 1 sharing one comparator 16 are not normal, no erroneous determination occurs in the other DRAMs 1. Therefore, the conventional ordinary testing burn-in device 14 can be used without any modification, and the cost of the burn-in test is reduced.

[0056]

According to the packet type DRAM according to the first aspect of the present invention, even if it takes a long time to determine the output data of the DRAM to be tested, each of the DRAMs must be properly timed during this time. Since the memory cells are refreshed, the data stored in the memory cells does not disappear during the output data determination period. Therefore, the conventional low-speed testing burn-in apparatus can be used as it is, and the manufacturing cost of the DRAM can be reduced.

According to the packet type DRAM according to the second aspect of the present invention, basically, the same effects as in the case of the DRAM according to the first aspect can be obtained. Further, since the memory cell is refreshed by using the signal corresponding to the zCAS signal and the signal corresponding to the zRAS signal, which are internal signals, the configuration of the self-refresh means is simplified, and Manufacturing costs are reduced.

In the packet type DRAM according to the third aspect of the present invention, basically the same effects as in the case of the DRAM according to the first or second aspect can be obtained. Further, it is possible to prevent a mutual current from flowing between the DRAMs at the time of the burn-in test, and even if a plurality of DRAM chips sharing one output data decision unit are abnormal, the other DRAM chips As a result, the accuracy of the burn-in test is improved, and the manufacturing cost of the DRAM is reduced, and the quality of the DRAM is improved.

In the packet type DRAM according to the fourth aspect of the present invention, basically the same effects as in the case of the DRAM according to the third aspect can be obtained. Furthermore, since the impedance of the output buffer circuit can be switched only by providing a simple signal output unit impedance switching means, the manufacturing cost of the DRAM can be reduced.

According to the packet type DRAM according to the fifth aspect of the present invention, it is possible to prevent a mutual current from flowing between the DRAMs during the burn-in test and to share one output data decision unit. Even if some of the plurality of DRAM chips are not normal, no erroneous judgment will occur in the other DRAM chips, so that the accuracy of the burn-in test is improved and the manufacturing cost of the DRAM is reduced, and the quality of the DRAM is reduced. Is enhanced.

In the packet type DRAM according to the sixth aspect of the present invention, basically the same effects as in the case of the DRAM according to the fifth aspect are obtained. Furthermore, since the impedance of the output buffer circuit can be switched only by providing a simple signal output unit impedance switching means, the manufacturing cost of the DRAM can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a portion related to a self-refresh operation of a packet type DRAM according to the present invention.

FIG. 2 is a circuit diagram of a ring oscillator circuit included in the DRAM shown in FIG.

FIG. 3 is a circuit diagram of an address counter circuit constituting the DRAM shown in FIG. 1;

4 is a circuit diagram of a RAS logic circuit constituting the DRAM shown in FIG.

5A is a circuit diagram of a timing detection circuit included in the DRAM shown in FIG. 1, and FIGS.
3 is a time chart showing the operation of the timing detection circuit shown in FIG.

6 is a circuit diagram of an output buffer circuit including an impedance control circuit of the DRAM shown in FIG.

FIG. 7 is a schematic diagram of a testing burn-in device in which a plurality of DRAMs share a comparator.

[Explanation of symbols]

1 DRAM, 2 logic circuit, 3 OR circuit,
4 ring oscillator circuit, 5 address counter circuit, 6 RAS logic circuit, 7 memory array, 8 timing detection circuit, 10 input terminal,
Reference Signs List 11 output terminal, 12 first internal terminal, 13 second internal terminal, 14 testing burn-in device, 15
Conductor, 16 comparators, AO1 AND · N
OR composite gate, I1-I7 inverter, I11
To I21 inverter, I31 to I42 inverter, I51 to I52 inverter, IA1 to IA2
NOR gate, IO1 to IO4 NAND gate,
N1 to N17 n-channel MOS transistors,
N21 to N24 n-channel MOS transistors, N
A1 to NA8 NAND gates, P1 to P17 p-channel MOS transistors, P21 to P24 p-channel MOS transistors.

Continued on front page F term (reference) 2G032 AA07 AB02 AC03 AD07 AE07 AE08 AK14 AK15 AL11 5B024 AA03 BA20 BA21 BA29 CA07 DA18 EA01 EA04 5L106 AA01 DD03 DD11 DD35 GG07

Claims (6)

[Claims] 1. A packet-type dynamic random access memory having a burn-in mode in which a memory test is performed at an operation frequency lower than the operation frequency at the time of burn-in while operating at a higher operation frequency by a packet format instruction. At least when a memory test is performed in the burn-in mode, a self-refresh means for refreshing a memory cell based on an internal clock signal is provided independently of the packet format instruction. Access memory. 2. The self-refresh means refreshes a memory cell when a signal corresponding to a column address strobe signal is activated prior to a signal corresponding to a row address strobe signal. The packet-type random access memory according to claim 1, wherein: 3. A signal output unit impedance switching means capable of increasing the impedance of a signal output unit higher than usual based on a predetermined internal signal is provided. The packet-based random access memory as described. 4. The first CMOS inverter to which an internal output signal is input, wherein the signal output unit includes: a first CMOS inverter;
A second CM to which an output signal of the inverter is input and an external output signal corresponding to the internal output signal is output to the outside
An output buffer circuit including an OS inverter, wherein the signal output unit impedance switching means outputs the first CM when the predetermined internal signal is in the first state.
While the output terminal of the OS inverter is electrically connected to the input terminal of the second CMOS inverter, when the internal signal is in the second state, the p-channel MOS transistor and the n-channel MOS transistor forming the second CMOS inverter 4. The packet type random access memory according to claim 3, wherein the impedance of the output buffer circuit is increased by turning off the MOS transistor. 5. A packet type dynamic random access memory adapted to operate at a higher operation frequency by a packet format instruction, wherein the impedance of a signal output unit is made higher than that of a normal time based on a predetermined internal signal. A packet type random access memory, comprising a signal output unit impedance switching means that can be increased. 6. The first CMOS inverter to which an internal output signal is input, wherein the signal output unit includes: a first CMOS inverter;
A second CM to which an output signal of the inverter is input and an external output signal corresponding to the internal output signal is output to the outside
An output buffer circuit including an OS inverter, wherein the signal output unit impedance switching means outputs the first CM when the predetermined internal signal is in the first state.
While the output terminal of the OS inverter is electrically connected to the input terminal of the second CMOS inverter, when the internal signal is in the second state, the p-channel MOS transistor and the n-channel MOS transistor forming the second CMOS inverter 6. The packet type random access memory according to claim 5, wherein the impedance of the output buffer circuit is increased by turning off the MOS transistor.