JP2001157437A - Charge-pumping boosting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge-pumping boosting circuit in which a reduction in the area of a power-supply circuit is realized by relaxing the degradation of a boosting efficiency due to the threshold value of a switching MOS transistor. SOLUTION: The charge-pumping boosting circuit is provided with charge pumping capacitors C1 to Cn. The boosting circuit is provided with switching MOS transistors MN0 to MNn. The boosting circuit is provided with gate boosting means GC1 to GCn which boost gates of the switching MOS transistors. The charge pumping capacitors are driven by a clock CLK1 and a clock CLK2 at a voltage amplitude generated by supplying a first voltage to a clock generating circuit A. The gate boosting means are driven by the clocks CLK1, CLK2, at a voltage amplitude generated by supplying a second voltage to a clock generating circuit C. As a result, a voltage VOUT is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a charge pump type boosting power supply circuit, and further relates to a microcomputer, for example, a flash memory having a boosting power supply circuit, a microcomputer having the flash memory together with a central processing unit. To apply to effective technology.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuit chips have tended to use a single power supply and a low power supply voltage. Is growing. As such a power supply circuit, IEEE JOURNAL OF SOLID-STATE
CIRCUIT) vol. SC11, pp374-378,
A DICKSON type charge pump circuit described in 1976 is common.

[0003] As shown in FIG.
The ICKSON type charge pump circuit is composed of n charge pumping capacitors C1 to Cn of a capacitor C and switching MOS transistors MN0 to MNn, and has two complementary clocks CLK1 having an external power supply voltage amplitude VCC and a clock frequency F. , CLK2, the odd-numbered capacity and the even-numbered capacity are alternately driven.

The gate node of a switching MOS transistor connected to a driven capacitor has a capacitance of C × VCC /
(C + CGATE) is boosted. At this time, if the voltage difference between the drain and the source is higher than the threshold value VTH of the switching MOS transistor, the charge is transferred to the adjacent node on the output side. During the charge transfer, the voltage difference between the drain and the source decreases, and the charge transfer ends when the voltage becomes equal to the threshold value VTH of the switching MOS transistor.

When the required maximum output current of the charge pump is IOUT, the maximum output voltage is VOUT, and the parasitic gate capacitance CGATE and the body effect are ignored, the voltage difference between the gate nodes when the equilibrium state is reached is several 1, Equation 2.

[0006]

(Equation 1)

[0007]

(Equation 2)

At this time, if the area of the charge pump circuit is defined by the sum of the capacitance parts S = nC, the following equation is obtained.
Is the minimum value (Equation 6) when designed as Equations 4 and 5.

[0009]

(Equation 3)

[0010]

(Equation 4)

[0011]

(Equation 5)

[0012]

(Equation 6)

That is, when VCC is reduced due to the reduction in power supply voltage, the area of the charge pump circuit is significantly increased. When the substrate effect is taken into consideration, the threshold value VTH increases as the switching MOS transistor is closer to the output side, and the charge pump circuit area is determined by the maximum threshold value of the switching MOS transistor MNn closest to the output side. Therefore, at a low power supply voltage, the body effect greatly increases the area of the charge pump circuit.

In a charge pump circuit requiring a large output current IOUT, such as a flash memory for performing hot electron writing, the output current IOUT
Since the threshold value VTH of the switching MOS transistor becomes larger as compared with the case where OUT is small, the circuit area is remarkably increased even at a low power supply voltage.

As a method for solving the above problems, various gate boosting means have been proposed to reduce the effect of VTH by boosting the gate of the switching MOS transistor. For example, the gate boosting means in FIG.
One gate boosting capacitor CG for boosting the gate of the OS transistor by coupling, and two MOS transistors MGA and M for equalizing the potential difference between the gate and the node of the charge pumping capacitor except for the threshold difference.
It is composed of GB.

FIGS. 14 and 15 show examples of the clock generation circuit and the clock waveform. After driving the odd-numbered charge pumping capacitors by the clock CLK1, the clock CLKG1 is driven to boost the gates of the odd-numbered switching transistors. Clock C
After LKG1 and CLK1 fall, the clock CLK
After driving the even-numbered charge-pumping capacitors by 2, the clock CLKG2 is driven to boost the gates of the odd-numbered switching transistors.

According to the circuit shown in FIG. 13, a gate-source potential difference larger than the drain-source potential difference of the switching MOS transistor can be generally generated at the time of driving the gate boosting capacitor. The influence on the charge transfer due to the switching MOS transistor threshold value VTH can be reduced.

FIG. 13 shows a comparison circuit and resistors R1 and R1.
And a ring oscillator circuit RO serving as a clock generation source.
Was also added. The comparison circuit compares a potential VCMP determined by a resistance ratio between R1 and R2 with a reference constant potential VREF,
If the output voltage VOUT of the charge pump circuit is higher than a prescribed voltage, the charge pump circuit control signal CPS
It outputs OFF as TOP, and outputs ON as the charge pump circuit control signal CPSTOP if the voltage is lower than the prescribed voltage. The charge pump circuit control signal CPSTOP
Is off, the clock generation circuit is controlled to control the clock C
The generation of LK1, CLK2, CLKG1, and CLKG2 is stopped, and when it is on, the generation of the clock is continued.

With the above control, the charge pump circuit 1
4 can stably output a prescribed voltage. Examples of the comparison circuit and the ring oscillator circuit are also shown in FIG.

[0020]

However, as the power supply voltage is reduced, the threshold voltage VTH of the switching MOS transistor can be generated by the gate booster even if the charge pump circuit shown in FIG. 13 is used.
It becomes relatively large with respect to the source-to-source potential difference, and an increase in the area of the charge pump circuit cannot be avoided. In addition, since the time constant of charge transfer increases due to an increase in the on-resistance of the switching MOS transistor, the effect of reducing the area of the charge pump circuit by increasing the clock frequency F is limited.

In order to avoid the above problem by using a depletion type MOS having a threshold VTH of 0 or a negative MOS as a switching MOS transistor, the charge pumping clock CLK1 and the gate boosting clock C
LKG1 or charge pumping clock CLK
2 and when the gate boost clock CLKG2 falls, the potential relationship between the nodes of the switching MOS transistor is maintained in the ON state for a while, so that the charge is transferred to the input side in the opposite direction and the boost efficiency is impaired. Problems arise.

FIG. 16 shows an example of a boost efficiency loss when a switching MOS transistor having a threshold value VTH of 0 or a negative value is used.

An object of the present invention is to provide a power supply circuit having a high boosting efficiency and a small area in order to alleviate such problems of the charge pump circuit.

[0024]

In order to achieve the above object, the present invention has the following arrangement.

(1) A charge pumping capacitor and a switching capacitor M having a drain connected to one electrode of the capacitor.
A plurality of unit configurations each including an OS transistor and a booster connected to the gate of the transistor are connected in series, and the other electrode of the capacitor is complementary to the adjacent unit configuration. A clock having a second voltage amplitude, the clock having a second voltage amplitude being switched to a conductive state and a non-conductive state when the charge pumping capacitor is driven by the clock. And a charge pump type booster circuit.

(2) Regarding the amplitude voltage of the clock,
The charge pump type booster circuit according to claim 1, wherein the second voltage is higher than the first voltage.

(3) An external power supply voltage supplied from outside the semiconductor chip, and a booster circuit for generating a second voltage on the semiconductor chip, wherein the first voltage is equal to or less than the power supply voltage.
The charge pump type booster circuit, wherein the second voltage is equal to or higher than the power supply voltage.

(4) A plurality of external power supply voltages supplied from outside the semiconductor chip are provided, and it is specified that a voltage lower than the maximum power supply voltage among the power supply voltages is output, and the output voltage is set as the first voltage. The charge pump type booster circuit according to claim 1, wherein a lower power supply voltage is used as the second voltage and a power supply voltage is higher than the output voltage.

(5) The charge pump type booster circuit according to the above (3), which can output a plurality of different voltages depending on the operation mode.

(6) Among the plurality of operation modes, in an operation mode in which a high output voltage is specified, a second voltage higher than the first voltage is set, and in an operation mode in which a low output voltage is specified, a second voltage is set. A charge pump type booster circuit for applying a second voltage equal to the first voltage.

(7) On a semiconductor chip having a plurality of charge pump type power supply circuits, one or more of the above charge pump type power supply circuits may be selected according to an operation mode.
The charge pump type booster circuit according to (2), wherein the output voltage or the node voltage of the drain of the switching MOS transistor is used as the second voltage.

(8) The output voltage of the charge pump type booster circuit itself or the switching M constituting the booster circuit
The charge pump type booster circuit according to (2), wherein the node voltage of the drain of the OS transistor is used as the second voltage.

(9) Switching MOS with High Threshold
Select the gate booster connected to the transistor
A gate boosting means for connecting a clock having a voltage amplitude of
The charge pump type power supply circuit according to the above (2), wherein a clock having a voltage amplitude of:

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to FIGS. In these figures, the same components are designated by the same reference numerals or reference numerals.

FIG. 1 is a schematic configuration diagram of a charge pump type booster circuit according to one embodiment of the present invention. This charge pump circuit includes switching MOS transistors MN0 to MN having charge pumping capacitances C1 to Cn and a threshold value VTH.
n, gate boosting means GC1 to GCn, a clock generation circuit A, and a clock generation circuit C.

For example, as shown in the waveform diagram of FIG. 4, the clock generation circuit A generates complementary clocks CLK1 and CLK2 having the first voltage amplitude VCC, and the clock generation circuit C
Are the clocks CLKG1 and CLG having the second voltage amplitude VCH.
Generate KG2. Clocks CLK1, CLK2, CL
KG1, CLKG2 have a frequency F and CLK1, CL
The switching MOS transistor is turned on and off while driving the odd-numbered charge pumping capacitance and the gate boosting means by CLK1 and CLKG2 by KG1.

In FIG. 1, clocks CLK1, CL
By separately providing the amplitude voltage of K2 and the clocks CLKG1 and CLKG2, there is an advantage that the amplitude voltage can be adjusted to stabilize the output voltage.

FIG. 2 shows a configuration of a power supply circuit using the charge pump type booster circuit of FIG. The voltage of the first clock in FIG. 1 is an external power supply VCC supplied from outside the semiconductor chip.
The voltage of the second clock is the internal power supply voltage VCH boosted by the booster circuit 13 provided in the chip.

Switching MOS with threshold value VTH> 0
The circuit of FIG. 13 is used as the transistor and the gate boosting means, the boosting circuit 13 and the clock generating circuits A and C, and the circuit of FIG. 3 are used as the ring oscillator circuit RO.
Assuming that VCH is sufficiently larger than VCC + VTH, the minimum value S1 of the capacitance portion of the charge pump circuit 14 is given by
It can be designed as follows.

[0040]

(Equation 7)

On the other hand, assuming that the parasitic gate capacitance of the switching MOS transistor is CGATE1, the output current amount required for the booster circuit 13 is approximately n × CGATE1.
× VCH × F. When the booster circuit 13 is designed using the conventional charge pump shown in FIG.

[0042]

(Equation 8)

Since the area of the power supply circuit is determined mainly by the capacitance of the charge pump circuit, S1 + S is smaller than S in Equation (6).
Under the condition that 2 + n × CG is smaller, the area of the entire power supply circuit can be reduced. The effect of reducing the area of the power supply circuit is the specified value IOUT of the output current or the threshold value VTH
Is remarkable when is large. In particular, when the threshold voltage VTH of the switching MOS transistor becomes substantially equal to or higher than VCC due to a lower power supply voltage or a substrate effect, the power supply circuit which cannot be designed by the conventional charge pump of FIGS. It may be possible.

Further, since the capacitance constituting the charge pump circuit is reduced, the size of the clock driver in the clock generation circuits A and C can be reduced, so that the power consumption can be reduced and the fluctuation of the external power supply voltage VCC during clock supply can be reduced. Becomes Further, according to this method, the effective resistance of the switching MOS transistor is reduced as compared with the conventional charge pumps of FIGS.
The charge transfer time constant proportional to the product of the effective resistance of the OS transistor and the charge pumping capacitance is reduced. Therefore, the clock frequency F can be designed to be large, and the capacitance component of the charge pump circuit area can be reduced.

FIG. 5 is a schematic diagram showing another embodiment of the present invention applied to a case where there are a plurality of external power supplies. The embodiment of FIG. 5 differs from the embodiment of FIG. 1 in that an external power supply (potential VCC2) higher than an external power supply (potential VCC) for driving a charge pumping capacitor is used instead of the internal power supply VCH generated by the booster circuit 13. ).

Generally, the application range of the external power supply voltage is ± 10%
And the required voltage VOUT is equal to the external power supply voltage VCC.
When the voltage is specified in the vicinity of the application range of 2, the voltage step-down circuit cannot output a stable voltage. In such a case, a booster circuit of the external power supply voltage VCC is used. However, according to the circuit of FIG. 5, the power supply circuit area can be designed to be smaller than that of the conventional charge pump shown in FIGS. it can.

Further, the charge pump type booster circuit according to the present invention can be combined with a power supply switching means for switching a power supply voltage supplied to a clock generation circuit for driving the gate booster means in accordance with an output voltage to be generated.

FIG. 6 shows an example of such a case.
The power supply voltage supplied to the clock generation circuit C by VC
An embodiment is shown in which two types, C and VCH, can be switched.

The power supply switching means 15 can be constituted by, for example, a circuit as shown in FIG. When the mode signal SIG is off, the power supply voltage VCC is supplied to the clock generation circuit C to generate VOUT1, and when the mode signal SIG is on, the power supply voltage VCH is supplied to the clock generation circuit C and VOUT2 (VCH> VCC, VOUT2) >
VOUT1). Further, when the mode signal SIG is off, the supply of the clock to the booster circuit 13 can be stopped.

According to the embodiment of FIG. 6, the provision of the power supply switching means 15 can reduce the power consumption when generating the output voltage VOUT1. Also,
In general, in a charge pump circuit, if the boosting capability is too large for a required output, the output voltage fluctuates greatly during control. According to the present embodiment, the output voltage can be stabilized by allocating the clock amplitude according to the output voltage. Further, when a plurality of charge pump circuits are provided to simultaneously generate an output voltage, the area of the booster circuit 13 can be reduced by optimizing the use of VCH to a necessary minimum.

FIG. 8 is a diagram schematically showing another embodiment for applying the present invention to a case where there are a plurality of charge pump circuits. For example, in the case of flash memory,
A required power supply voltage configuration is different between a mode in which data is erased or written and a mode in which data is read, and there may be a charge pump circuit that requires an output voltage only in one of the modes. FIG. 8 shows such a charge pump circuit as a charge pump circuit CP1.

The output voltage VCP1 of CP1 is applied to the internal power supply VO.
In a mode in which it is not necessary to supply the UT1 to the outside of the power supply circuit, the output voltage VCP1 is supplied to the clock generation circuit C as the clock generation circuit internal power supply VCH.

FIG. 9 shows an example of the power supply switching means 16 for switching the supply destination of the VCP1. In FIG. 9, the output voltage VCP1 of the charge pump circuit CP1 is changed to the mode signal S
VCH when IGJ is on, VOUT when off
Supply to 1.

According to the embodiment shown in FIG. 8, the charge pump circuit CP1 which is originally inactive can be replaced with the booster circuit 13 shown in FIG. Thus, the area of the entire power supply circuit can be further reduced.

FIG. 10 is a schematic diagram of a charge pump type booster circuit according to still another embodiment of the present invention. In the present embodiment, the k-th node NODEk (2 ≦ k ≦ n +) from the boost start node VS inside the charge pump circuit 14
The potential VCH of 1) is supplied to the clock generation circuit C as a second potential, and the clocks CLKG1 and CLKG2 having the voltage amplitude VCH are generated.

Assuming that VCH is sufficiently larger than VCC + VTH, the charge pumping capacitors Cy (k ≦ y) connected to the kth and subsequent nodes cover the output current IOUT (as shown in Expression 9). The charge pumping capacitance Cx (x <k) at the beginning is determined by the output current IOUT
And the current consumed by the clock generation circuit C (formula 10). In this case, the capacitance component S3 of the area of the charge pump circuit 14 is given by Expression 11, and S
Under the condition that 3 is smaller than the capacitance component S of the area of the conventional charge pump circuit (FIG. 13), the power supply circuit area can be designed smaller than using the conventional charge pump circuit.

[0057]

(Equation 9)

[0058]

(Equation 10)

[0059]

[Equation 11]

FIG. 11 is a diagram schematically showing another embodiment of the charge pump type booster circuit of the present invention. In the present embodiment, a switching MOS transistor having a large threshold in the charge pump circuit 14 is selected to apply the second voltage VCH (VCC <VCH).

For example, switching M having a large substrate effect
When the OS transistor is used, when the charge pump circuit is driven, the switching M close to the output terminal VOUT is used.
The threshold value VTH increases as the OS transistor increases. Since the current-voltage capability of the charge pump circuit 14 is limited by the MOS having the largest threshold value VTH, the current-voltage capability of the charge pump circuit is improved by selecting a MOS from the side closer to the output terminal and applying VCH. be able to.

In FIG. 10, a clock of VCH amplitude is supplied to the gate boosting means of the MOS from MNk + 1 to MNn. If VCH is set sufficiently higher than VCC + VTH, the threshold voltage VTH of the switching MOS transistor MNn increased by the body effect is avoided, and the current-voltage capability of the charge pump circuit 14 is determined by the smaller threshold voltage of the MOS transistor MNk. can do.

According to the embodiment of FIG. 11, the current required for a clock having a VCH amplitude is (nk) × CGAT
Since E × VCH × F is sufficient, the area of the booster circuit 13 can be designed to be small, and the circuit area of the entire power supply circuit can be reduced.

Although only the case where the charge pump circuit 14 generates a positive voltage has been described above, the charge pump circuit 14 may be replaced with a charge pump circuit that generates a negative voltage. Although the circuit of FIG. 13 has been described as an example of the gate boosting means, it can be replaced with another circuit.

[0065]

As apparent from the detailed description of the preferred embodiments of the present invention with reference to the drawings, the present invention provides a gate boosting means for a switching MOS transistor of a charge pump circuit which has an amplitude greater than a power supply voltage. To increase the voltage generation efficiency of the charge pump circuit by avoiding the limitation on the current voltage generation capability due to the threshold value of the switching MOS transistor forming the charge pump circuit, and increase the voltage for generating the clock voltage. Even if the increase in the circuit area is taken into consideration, the effect of reducing the design area as the whole power supply voltage is provided.

Further, such an effect is remarkable when a plurality of charge pump circuits such as a flash memory and an EEPROM are used, and a charge pump circuit which is not in use is used as the booster circuit. The effect of the present invention can also be obtained by providing the charge pump itself with the function of the booster circuit. Also,
High threshold switching M in charge pump circuit
By selecting the OS transistor and applying the clock, the design area of the booster circuit can be reduced, and the present invention can be effectively implemented.

In the conventional charge pump circuit of FIG. 13, the threshold VTH is 0 or a negative depletion type M.
According to the present invention, when the OS is used for the switching MOS transistor, the charge is transferred in the reverse direction and the boosting efficiency is deteriorated.
K1 and the gate boosting clock CLKG1, or the charge pumping clock CLK2 and the gate boosting clock C
When LKG2 falls, the gate boosting clock has a larger falling voltage amplitude than the charge pumping clock, and the potential relationship of each node of the switching MOS transistor can be turned off, which can be avoided. FIG. 16 shows an example in which the boosting efficiency is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a charge pump type booster circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a power supply circuit using the booster circuit of the embodiment of FIG.

FIG. 3 shows a clock generation circuit, a booster circuit,
FIG. 3 is a circuit diagram illustrating an example of a ring oscillator circuit and a comparison circuit.

FIG. 4 is a clock waveform diagram generated by the clock generation circuit of FIG. 3;

FIG. 5 is a block diagram schematically showing an embodiment when a plurality of external power supplies can be used.

FIG. 6 is a block diagram schematically showing an embodiment provided with power supply switching means.

FIG. 7 is a circuit diagram showing an example of a power supply switching means, a booster circuit, a clock generation circuit, and a comparison circuit used in the embodiment of FIG. 6;

FIG. 8 is a block diagram schematically showing an embodiment when a plurality of charge pump circuits exist.

FIG. 9 is a circuit diagram showing an example of a power supply switching unit used in the embodiment of FIG.

FIG. 10 is a block diagram showing an embodiment in which the charge pump circuit itself generates a boosted power supply of a clock supplied to the gate boosting means.

FIG. 11 is a block diagram of an embodiment in which a supply destination of a clock having an amplitude of a boosted power supply voltage is selected according to a threshold value of a switching MOS transistor.

FIG. 12 is a circuit diagram showing a conventional DICKSON type charge pump circuit.

FIG. 13 is a circuit diagram of a conventional example in which a gate booster is provided in the charge pump circuit of FIG.

FIG. 14 is a circuit diagram illustrating an example of a clock generation circuit, a ring oscillator circuit, and a comparison circuit used in FIG.

FIG. 15 is a waveform diagram of a clock generated by the clock generation circuit of FIG. 14;

FIG. 16 is a characteristic diagram showing an example of the dependency of the output voltage on the threshold value of the switching MOS transistor in the conventional example and the charge pump circuit of the present invention.

[Explanation of symbols]

13 booster circuit, 14 charge pump circuit, 15 2
Power supply switching means of input 1 output, power supply switching means of 16 ... 1 input 2 outputs, VCC, VCC1, VCC2 ... power supplied from outside the chip, internal power supply obtained by boosting VCH ... VCC inside the chip, MN0 to MN0 MNn, MN
C0 to MNCn: switching NMOS transistors,
C1 to Cn: charge pumping capacity, GC1 to GCn
... Gate boosting means, VOUT, VOUT1 to VOUT
m, VCP1... output potential of the charge pump circuit, CLK
1, CLK2: clocks for driving the charge pumping capacitors, CLKG1, CLKG2, CLKGA1, CLK
GA2, CLKGB1, CLKGB2... Clocks for driving the gate booster, F... Clock cycle, CS, CSS
... Smoothing capacitance, SIG, SIGJ ... Mode signal, NODE
1 to NODEn + 1... Internal nodes of the charge pump circuit, MGA1 to MGAn, MGB1 to MGBn... MOS transistors constituting gate boosting means, CG1 to CG
n: a gate boosting capacity constituting the gate boosting means.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masamichi Fujito 5-22-1, Josuihoncho, Kodaira-shi, Tokyo F-term in Hitachi Super LSI Systems Co., Ltd. 5H730 AA14 AA15 AS19 BB02 BB08 DD04

Claims (9)

[Claims] A plurality of units each comprising a charge pumping capacitor, a switching MOS transistor having a drain connected to one electrode of the capacitor, and a booster connected to a gate of the MOS transistor are connected in series. The other electrode of the charge pumping capacitor is supplied with a clock having a first voltage amplitude complementary to the adjacent unit configuration, and the booster is supplied with the first voltage.
A clock having a second voltage amplitude for switching between conduction and non-conduction of the transistor when the charge pumping capacitor is driven by the clock. 2. The charge pump type booster circuit according to claim 1, wherein a voltage amplitude (VCH) of said second clock is larger than a voltage amplitude of said first clock. 3. An external power supply voltage supplied from outside the semiconductor chip, and a booster circuit for generating a voltage amplitude of the second clock on the semiconductor chip, wherein the voltage amplitude of the first clock is the external voltage. 3. The charge pump type booster circuit according to claim 2, wherein the voltage amplitude of the second clock is equal to or lower than the power supply voltage and equal to or higher than the external power supply voltage. 4. It is provided that a plurality of external power supply voltages supplied from outside the semiconductor chip are provided, and a voltage lower than a maximum power supply voltage among the external power supply voltages is output.
4. The charge pump booster according to claim 3, wherein a power supply voltage lower than said output voltage is used as a voltage amplitude of said clock, and a power supply voltage higher than said output voltage is used as a voltage amplitude of said second clock. circuit. 5. The charge pump type booster circuit according to claim 3, wherein a plurality of different voltages can be output according to an operation mode. 6. An operation mode in which a high output voltage is defined among the plurality of operation modes, wherein a voltage amplitude of a second clock higher than a voltage amplitude of the first clock is set to
6. The charge pump booster circuit according to claim 5, wherein in an operation mode in which a low output voltage is specified, a voltage amplitude of a second clock equal to the voltage amplitude of the first clock is applied. 7. On a semiconductor chip having a plurality of charge pump type power supply circuits, an output voltage of one or a plurality of the charge pump type power supply circuits or a node voltage of a switching MOS transistor drain portion is determined according to an operation mode. 3. The charge pump type booster circuit according to claim 2, wherein the booster circuit is used as a voltage of a second clock. 8. The method according to claim 2, wherein an output voltage of the charge pump type booster circuit itself or a node voltage of a drain of a switching MOS transistor constituting the booster circuit is used as a voltage of the second clock. Charge pump type booster circuit. 9. A clock having a second voltage amplitude is selected by selecting a gate booster connected to a switching MOS transistor having a higher threshold value, and a clock having another voltage is applied to the other switching MOS transistor.
3. The charge pump type power supply circuit according to claim 2, wherein a clock having a first voltage amplitude is supplied to a gate booster connected to the transistor.