JP2001154749A - Reference voltage generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reference voltage generation circuit. SOLUTION: The reference voltage generation circuit is provided with a band gap circuit 11 for outputting band gap output voltage from a 1st output terminal, a 1st switch capacitor circuit 12 to be driven by receiving a 1st control clock and a filter means 13 for receiving the band gap output voltage and outputting the output from a 2nd output terminal and the band gap output voltage is controlled by the frequency of the 1st control clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generation circuit, and more particularly to a reference voltage generation circuit capable of finely adjusting an output voltage thereof.

[0002]

2. Description of the Related Art Many conventional circuits for generating a reference voltage use a bandgap voltage using a bipolar transistor for temperature compensation. Such a technique is disclosed in, for example, Japanese Patent Application Laid-Open No. 4-143811, and FIG.
An example of the configuration of a conventional reference voltage generating circuit capable of outputting a reference voltage other than 1.2 V is shown.

FIG. 6 shows a circuit configuration of this conventional reference voltage generating circuit.

Referring to FIG. 6, reference voltage generating circuit 61
Connects the resistor R1 and the diode 65 in series, connects the connection point to the non-inverting input terminal of the operational amplifier 64,
2, a resistor R3 and a diode 66 are connected in series, and a resistor R2
The dividing point between the resistor R3 and the resistor R3 is connected to the inverting input terminal of the operational amplifier 64. In this configuration, a terminal different from the dividing point of R2 and the resistor R3 is connected, and the output voltage VOUT of the reference voltage generating circuit 61 is output from this connecting point.

A current flowing through the diode 65 is defined as a current I1, a saturation current of the diode 65 is defined as a saturation current IS1,
The forward voltage of the diode 65 is defined as a forward voltage VBE1, the current flowing through the diode 66 is defined as a current I2, the saturation current of the diode 66 is defined as a saturation current IS2,
Assuming that the absolute temperature is T, the Boltzmann constant is K, and the unit charge of electrons is q, the output voltage VOUT is expressed as in equation (1).

[0006]

(Equation 1)

At this time, the forward voltage VBE1 of the diode 65 is expressed by the following equation (2).

[0008]

(Equation 2)

The saturation currents IS1 and IS2 of the diodes are
It is proportional to the area of the diode. Also, a resistor R1 and a resistor R
2 and the value of the resistor R3 and the diode 65,
By appropriately setting the area of the output voltage V
OUT can obtain a desired voltage which hardly depends on the power supply voltage and the temperature.

For example, R1 = R2 = 4 kΩ, R3 = 1k
And the area ratio between the diode 66 and the diode 65 is 6
Assuming 5.0, a constant voltage of output voltage VOUT = 1.157V is obtained.

[0011]

However, in the variable reference voltage generating circuit of the prior art, the output voltage of the voltage regulator often has an error from the design value due to variations in diffusion conditions in the process of manufacturing the semiconductor. When this error is used as a reference voltage, it directly affects the subsequent circuit. In the case of variations in diffusion conditions in a normal semiconductor manufacturing process, the limit is to limit the band gap output error to about ± 2%.

A main object of the present invention is to provide a reference voltage generating circuit capable of changing an output voltage by changing a sampling frequency when further accuracy is required.

[0013]

A reference voltage generating circuit according to the present invention comprises a bandgap circuit for outputting a bandgap output voltage from a first output terminal, and a first switched capacitance which operates in response to a first control clock. And a filter means for receiving the bandgap output voltage and outputting the output from a second output terminal, wherein the bandgap output voltage is controlled by the frequency of the first control clock. .

Further, the filter means of the reference voltage generating circuit according to the present invention includes a second switched capacitor circuit which operates in response to a second control clock, and outputs the bandgap output voltage to the second control clock. May be used to control the hold.

[0015] The first control clock and the second control clock of the reference voltage generating circuit of the present invention may be configured to be in-phase signals.

Further, the band gap circuit of the reference voltage generating circuit according to the present invention includes a first resistor, a second resistor,
A third resistor, an operational amplifier, a first diode, and a second diode, wherein one end of the first resistor and the first diode are connected in series at a first contact, One end of a second resistor and one end of the third resistor are connected in series at a second contact, the other end of the third resistor and the second diode are connected in series at a third contact, The first contact is connected to the non-inverting input of the operational amplifier, the second contact is connected to the inverting input of the operational amplifier, the output of the operational amplifier, the other end of the first resistor, and the second The other end of the second resistor is connected to a fourth contact, and the band gap output voltage is output to the fourth contact.

Still further, the second switched capacitor circuit of the reference voltage generating circuit according to the present invention may be configured to receive the bandgap output voltage and output it from the second output terminal. A fourth switched capacitor circuit receiving the bandgap output voltage.
, And output from the second output terminal.

That is, the present invention is characterized in that a switched capacitor circuit is used for a band gap circuit. The output voltage of the voltage regulator can be varied or finely adjusted by externally inputting a drive clock to the switched capacitor circuit and changing the clock frequency (sampling frequency).

[0019]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a reference voltage generating circuit according to a first embodiment of the present invention.

FIG. 1 is a block diagram showing a configuration of a reference voltage generation circuit based on the switched capacitor technique of the present invention.

Referring to FIG. 1, a reference voltage generating circuit 10 according to a first embodiment of the present invention includes a switched capacitor circuit 12 to which a control clock has been input, and a band gap circuit 11 having an output from the switched capacitor circuit 12. , And outputs the output voltage via the switched capacitor circuit 13 having a sample-and-hold function.

More specifically, referring to FIG. 2, a reference voltage generating circuit 10 according to a first embodiment of the present invention is connected to a resistor R3 of a band gap circuit 21 having the same configuration as a conventional reference voltage generating circuit 61. In parallel, switched capacitor circuit 2
2 and a configuration in which the sample-and-hold circuit 23 is provided in the output unit.

That is, the bandgap circuit 21 connects the resistor R1 and the diode 25 in series, and
Is connected to the non-inverting input terminal of the operational amplifier 24, and the resistor R2
, The resistor R3 and the diode 26 are connected in series, the dividing point 28 between the resistor R2 and the resistor R3 is connected to the inverting input terminal of the operational amplifier 24, and the output terminal of the operational amplifier 24, the resistor R1 of the resistor R1 and the diode 25 are connected. And a terminal 29 different from the dividing point 28 of the resistor R2 and the resistor R2 of the resistor R3, and the output voltage of the bandgap circuit 21 is output from the connecting point 29. is there.

Further, the reference voltage generating circuit 10 according to the first embodiment of the present invention comprises switches S1, S2 and a capacitor C1, and a switched capacitor circuit 22 connected in parallel to a resistor R3; Reference voltage generation circuit 10
Between the switches S3 and S4 and the capacitor C2
And a low-pass filter including the switched capacitor circuit 23 and the capacitor C3.

Next, the operation of the reference voltage generating circuit according to the first embodiment of the present invention will be described.

First, the output voltage of the bandgap circuit 21 is represented by the following equation (1).

[0027]

(Equation 3)

The forward voltage VBE1 of the diode 25 at this time is as shown in the following equation (2).

[0029]

(Equation 4)

Then, the equivalent resistance RSC of the switched capacitor circuit is represented by the capacitance value C and the sampling frequency fs as shown in equation (3).

[0031]

(Equation 5)

The reference voltage generating circuit according to the first embodiment of the present invention is realized by the parallel connection of the conventional resistor R3 and the equivalent resistor RSC of the switched capacitor circuit 22. It is represented by (4).

[0033]

(Equation 6)

Therefore, the output voltage of the proposed circuit can be expressed as in equation (5) from equations (1) and (4).

[0035]

(Equation 7)

For example, R1 = R2 = 4 kΩ, R3 = 1k
And the area ratio between the diode 66 and the diode 65 is 6
5.0, C1 = 100 pF, C2 = C3 = 10
Assuming that pF and fs = 200 kHz, the output voltage VOUT
A constant voltage of = 1.160 V is obtained.

Next, the driving clock will be described with reference to FIG. The potential of the contact 28 shown in FIG. 2 is represented by VA, the potential of the contact 27 is represented by VB, and the potential of the contact 29 is represented by VC.

As the driving clock, two clocks as shown in FIG. 4 are required, and the switches S1 and S3 and the switches S2 and S4 are driven in the same phase. This two-phase clock is a clock whose HIGH portions do not cross each other. For example,
After the switches S1 and S3 are turned off, all the switches are temporarily turned off, and then the switches S2 and S4 are turned on.

When the clock φ1 is HIGH, the switch S1 is turned on, and the capacitor C1 is charged with the charge QA = C1 · VA.

Next, when the clock φ2 is HIGH,
The switch S2 is turned on, and the electric charge QB = C1 ·
VB is charged. The differential charge QA-QB = C1 at that time
(VA-VB) is discharged via the diode.

Accordingly, during the sampling period Ts, the contact 28 is connected to the contact 2 via the switched capacitor circuit.
7 is IC1 = QA-QB / Ts = C
1 (VA−VB) / Ts = C1 · fs (VA−VB), and the resistance RC1 is virtually set in the switched capacitor circuit.
= 1 / (C1 · fs).

Since this resistance value depends on the sampling frequency, by changing the sampling frequency from the outside, the resistance value between the contact 28 and the contact 27 is changed, and the output voltage can be adjusted.

Although the voltage at the contact 29 is a complete DC voltage in the conventional band gap circuit, the voltage at the contact 29 is
Switched Capacitor Circuit 2 Existing Between Switch 8 and Contact 27
2 affected by ON / OFF of the switches S1 and S2,
With minor changes.

Further, switching noise is generated, and a stable DC voltage originally desired as a regulator cannot be obtained. The minute change of the potential of the contact 29 and the switching noise are high frequency (1
00 kHz or more), it is possible to easily convert to a stable DC potential by using a low-pass filter.

The use of a sample-and-hold circuit also enables stable conversion to a DC potential. This is because a minute change in the potential of the contact 29 or noise depends on the ON / OFF timing of the switch. Therefore, if sampling is performed at the same timing each time, the same potential can be sampled. This is because a stable potential without potential change or noise can be obtained. This circuit uses the latter sample-hold circuit.

When the clock φ1 is HIGH, the switch S3 is turned on, and the capacitor C2 is charged with the voltage of the contact 29. Although the voltage of the contact 29 slightly changes while the switch S3 is on, the potential at the moment when the switch S3 is turned off and the potential at the moment when the clock φ1 changes from HIGH to LOW are held in the capacitor C2.

Then, when the clock φ2 becomes HIGH, it is transmitted to the capacitor C3 at the subsequent stage. The potential (VOUT) of the capacitor C3 is initially 0 V, but after charging is repeated many times, it rises to a potential that is sampled and held by the capacitor C2 and becomes constant each time.

Switched capacitor circuit 23 of capacitance C2
Also realizes a resistance, so that a first-order RC low-pass filter is formed with the capacitor C3.

When the clock φ1 becomes HIGH and the switch S1 is turned ON, a change occurs in the potential of the contact 29.
However, the potential held by the sample hold is the switch S
3 is OFF (when the clock φ1 changes to LOW), a stable potential whose change has converged can be transmitted to the subsequent stage. Therefore, the VOUT potential becomes DC.

The potential of the capacitor C1 is such that the clock φ1 is HIGH.
, The switch S1 is turned on and charged to the potential of the contact 28. When the clock φ2 becomes HIGH, the switch S1 is turned on.
2 is turned on and charged to the potential of the contact 27.

The switches S1 and S3 set the clock φ1 to H level.
It turns ON only when IGH, and turns OFF when the clock φ1 is LOW. The switches S2 and S4 are turned ON only when the clock φ2 is HIGH, and turned OFF when the clock φ2 is LOW.

Here, the actual clock potential is HIG
H = VDD potential and LOW = GND potential.

FIG. 5 shows the relationship between the sampling frequency and the output voltage obtained from equation (5).

Each parameter is R1 = R2 = 4 kΩ, R
3 = 1 kΩ, the area ratio between the diode 66 and the diode 65 is set to 65.0, C1 = 100 pF, C2 = C
Using values of 3 = 10 pF and fs = 200 kHz, kT /
Calculated as q = 0.0257V, VBE1 = 0.725V.

In practice, the forward voltage VBE1 is equal to the current I1
Is not constant. FIG. 5 shows that the output voltage can be adjusted by changing the sampling frequency. If the sensitivity of the output voltage is set low with respect to the sampling frequency, the output voltage can be finely adjusted.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows a reference voltage generation circuit according to a second embodiment of the present invention.

Referring to FIG. 3, in the reference voltage generation circuit according to the second embodiment of the present invention, the switched capacitor circuit 23 of the reference voltage generation circuit according to the first embodiment of the present invention is replaced with a resistor RX. Only the other components are the same, and the same components are denoted by the same reference numerals.

Therefore, the components and operation thereof are the same as those of the reference voltage generating circuit according to the first embodiment of the present invention, so that the detailed description thereof will be omitted. However, an ordinary RC low-pass filter or integrator can be used instead.

Further, in the present invention, a switched capacitor circuit is connected in parallel only to one resistor to the conventional type, but a switched capacitor is connected to other resistors to increase the number of connections. Examples are possible.

[0060]

As described above, the equivalent resistance RSC of the switched-capacitor circuit is expressed by the following equation (4).
And the sampling frequency fs. Since the resistor R3 is realized by connecting the equivalent resistor RSC of the switched capacitor circuit in parallel, the resistance value R3SC is represented by the equation (5).

Therefore, the output voltage of the circuit of the present invention is
From Expressions (1) and (5), it can be expressed as Expression (6). By changing the sampling frequency fs from the equation (6), there is an effect that the output voltage of the voltage regulator can be changed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a reference voltage generation circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a reference voltage generation circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a reference voltage generation circuit according to a second embodiment of the present invention.

FIG. 4 is a time chart illustrating an operation of the reference voltage generation circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a relationship between an output voltage and a frequency of the reference voltage generation circuit according to the first embodiment of the present invention.

FIG. 6 is a block diagram of a conventional reference voltage generation circuit.

[Explanation of symbols]

 10 Reference voltage generation circuit 11, 21 Band gap circuit 12, 13, 22, 23 Switched capacitor circuit 24, 64 Amplifier 25, 26, 65, 66 Diode 27, 28, 29, 30 Contact R1, R2, R3 Resistance C1, C2 , C3 capacitance S1, S2, S3, S4 switch VOUT output voltage

Claims (7)

[Claims] 1. A bandgap circuit that outputs a bandgap output voltage from a first output terminal; a first switched capacitor circuit that operates in response to a first control clock; A filter means for outputting an output from a second output terminal, wherein the bandgap output voltage is controlled by a frequency of the first control clock. 2. The filter unit includes a second switched capacitor circuit that operates in response to a second control clock, and controls the hold of the bandgap output voltage by the second control clock. The reference voltage generating circuit according to claim 1, wherein 3. The reference voltage generation circuit according to claim 2, wherein said first control clock and said second control clock are in-phase signals. 4. The bandgap circuit includes a first resistor, a second resistor, a third resistor, an operational amplifier, and a first resistor.
And a second diode, one end of the first resistor and the first diode are connected in series at a first contact, and one end of the second resistor and the third resistor Are connected in series at a second contact, the other end of the third resistor and the second diode are connected in series at a third contact, and the first contact is connected to the non-inversion of the operational amplifier. Connected to the input, the second contact is connected to the inverting input of the operational amplifier, and the output of the operational amplifier, the other end of the first resistor, and the other end of the second resistor are connected to a fourth contact. Connect with
4. The reference voltage generation circuit according to claim 1, wherein said bandgap output voltage is output to said fourth contact. 5. The reference voltage generating circuit according to claim 4, wherein said first switched capacitor circuit is connected in parallel to said third resistor. 6. The reference voltage generating circuit according to claim 1, wherein said second switched capacitor circuit receives said bandgap output voltage and outputs from said second output terminal. 7. The reference voltage generating circuit according to claim 6, wherein said second switched capacitor circuit is replaced with a fourth resistor for receiving said bandgap output voltage, and outputs said signal from said second output terminal.