JP2001142737A - Memory management device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a management device with high maintainability which realizes a reliable system to easily be constituted by allowing necessary tasks to share only necessary modules without modifying a program and disabling others to access a memory directly to prevent the contents of tasks stored in the memory from being broken and which can also monitor specific access to the memory. SOLUTION: At a request to access a logical address which is not made to correspond to a physical address, a tracing means 108 performs mapping for making the logical address correspond to a physical address. A history of access to the local address which is not made to correspond is written to the physical address. A history acquiring means 110 obtains the history of access from the specific physical address of the memory in response to notification from the tracing means 108.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory management device used in a multitask system.

[0002]

2. Description of the Related Art In recent years, in a so-called embedded microcomputer control system in which program codes are arranged in a read-only memory (ROM), a program size has been increased along with the complexity of a target system, and a multi-task system is constituted. It is customary.
In a multitasking system, when a certain task has a bug that destroys stored information used in another task, the pursuit of the bug is extremely difficult, and it takes an enormous amount of time to resolve the bug.

[0003] Recently, microprocessors for embedding devices are being equipped with protection mechanisms that function in the execution stage. Therefore, in order to solve the above-mentioned problem, using such a protection mechanism, a program in which a bug can occur can be operated in a non-privileged mode, and a program in which a bug cannot occur can be operated in a privileged mode. A method for preventing malfunction of the multitasking system can be considered.

However, in this method, it is difficult to determine whether each program is operated in a privileged mode or a non-privileged mode. In addition, programs operating in the same mode can be destroyed from each other, so that the problem cannot be completely solved.

Further, in the field of computers such as workstations and personal computers, each task is operated in a different logical address space by using a memory management unit (MMU) so that memory cannot be directly accessed between tasks. Some have solved this problem. Some recent microprocessors for embedded devices have a memory management device, so such microprocessors can directly access memory between tasks like a computer to solve the above problem. It is conceivable to configure so as not to be possible.

However, in an embedded microcomputer control system, many tasks share code and data and operate in close coordination. Therefore, in an embedded microprocessor, tasks are divided into separate logical address spaces. It is very difficult to do.

However, the same problem also exists in the field of computers, and a conventional memory management device implements a shared memory that can be directly accessed between tasks.

FIG. 11 is a block diagram showing the configuration of a conventional memory management device for realizing a shared memory using the shared memory management method described in, for example, Japanese Patent Application Laid-Open No. 7-93210.

A memory management device 800 shown in FIG. 11 holds memory area information 801 and space information 802. The memory area information 801 describes a memory area identifier for identifying a memory area and information about the memory area such as the memory size of the memory area indicated by the memory area identifier for each memory area. Spatial information 802
Describes a space identifier for identifying a logical address space and a memory area belonging to the logical address space indicated by the space identifier for each logical address space.

The memory management device 800 includes an address conversion table 803, a mapping unit 804, and an address conversion table switching unit 805. Mapping means 804
Creates an address conversion table 803 to map a memory area to a logical address space. The address conversion table 803 is provided for each logical address space,
When the conversion between the physical address and the logical address is performed, the correspondence between the physical address and the logical address is indicated. The address conversion table switching means 805 switches the logical address space by switching the address conversion table 803 when switching tasks.

A conventional memory management device 800 shown in FIG.
In, the mapping means 804 is activated in response to a shared memory mapping request issued by the task. The mapping unit 804 refers to the memory area information 801 for the shared memory to be mapped, refers to the space information 802 for the logical address space to be mapped, and creates an address conversion table 803, so that the memory area of the shared memory can be mapped. Map to logical address space. Further, when a mapping request for a shared memory is issued by another task, the memory management device 800 of FIG.
Performs a similar process. In this way, by mapping the memory area sharable among a plurality of tasks to the logical address space, the address conversion table switching means 805
Can share the memory area even when the logical address space is switched.

[0012]

In the conventional memory management device 800 configured as described above, in the memory area secured and shared by a request from a task,
Since each task can only share the buffer memory and data structure that are dynamically allocated and accessed between tasks, the code and data directly written in the program cannot be shared, which does not solve the problem. .

Further, in the memory management device 800, since the logical address space is switched by switching the address conversion table 803, and a plurality of tasks share the shared memory, it is difficult to monitor a specific access to the memory. .

An object of the present invention is to allow only necessary modules to be shared between required tasks without changing a program, otherwise the memory cannot be directly accessed between tasks, and the contents of the tasks stored in the memory are destroyed. An object of the present invention is to provide a highly maintainable memory management device which can easily construct a highly reliable system by preventing such a situation from occurring and can monitor a specific access to a memory.

[0015]

(1) First invention A memory management device according to a first invention is a memory management device for associating physical addresses of a memory with a plurality of logical addresses, and comprises a plurality of logical address spaces. Allocating means for arranging the module in each of the plurality of logical address spaces based on the definition indicating the correspondence between the module and the plurality of modules;
Mapping means for associating a physical address with a logical address in a logical address space in which a module is arranged by an arrangement means based on module information indicating physical addresses of a plurality of modules, and mapping means in response to a task switching instruction. A logical address space switching means for switching between a plurality of assigned logical address spaces, and an access request to an unsupported logical address which is not associated with a physical address in the logical address space switched by the logical address space switching means. If there is, the mapping unit associates the uncorresponding logical address with the first physical address of the memory to execute access to the uncorresponding logical address. History to the second physical address in memory And tracing means for causing written to scan, in which and a history acquisition unit that acquires a history of the access from the second physical address of the memory.

In the memory management device according to the present invention,
The module is arranged in each of the plurality of logical address spaces based on the definition by the arrangement unit, and the physical address is associated with the logical address of the arranged logical address space by the mapping unit based on the module information.
Therefore, when the logical address space is switched by the logical address space switching means in response to the task switching instruction, the correspondence between the logical address space and the module before and after the switching is determined as shown in the definition. Therefore, if the same module required in different tasks is indicated by definition to correspond to different tasks in common, the same modules can be shared. However, modules other than the shared module are not shared because the definition indicates that they correspond to only one of the different tasks. As a result, direct access to the memory between different tasks other than the necessary modules is prohibited, and only the necessary modules can be shared between the different tasks.

Further, triggered by an access request to an unsupported logical address that is not associated with a physical address, the tracing means writes the access history at the unsupported logical address to the second physical address. The history of the access written to the second physical address is obtained by the history obtaining means. Thereby, specific access to the memory can be monitored.

(2) Second invention In the memory management device according to the second invention, in the configuration of the memory management device according to the first invention, the tracing means is provided after the access to the unsupported logical address is completed. , The correspondence between the unsupported logical address and the first physical address is released.

In this case, the tracing means detects an access request to an unsupported logical address which is not repeatedly associated with the logical address, and the history obtaining means can obtain the history of repeated access.

(3) Third invention A memory management device according to a third invention is the same as the memory management device according to the second invention, further comprising a management means for intermittently activating the trace means. is there.

In this case, since the tracing means is started intermittently, the number of times of acquiring the access history can be limited, and the operation of the memory management device can be made efficient.

(4) Fourth Invention In a memory management device according to a fourth invention, in the configuration of the memory management device according to the third invention, the management means activates the trace means and the history acquisition means at predetermined time intervals. Is what you do.

In this case, a specific access to the memory can be monitored at predetermined time intervals.

(5) Fifth invention In a memory management device according to a fifth invention, in the configuration of the memory management device according to the third or fourth invention, when the tracing means is not activated by the management means, The arrangement means arranges the modules and the mapping means associates the unsupported logical address with the first physical address.

In this case, it is possible to access the first physical address even when the tracing means is not activated.

(6) Sixth invention In a memory management device according to a sixth invention, in the configuration of the memory management device according to any one of the first to fifth inventions, the tracing means is associated with a physical address. If there is a write request as an access request to an unsupported logical address that has not been handled, the first physical address is used as the second physical address, and the access history of the logical address that is not supported by the first physical address is stored. What to write.

In this case, the access history is stored in the second memory in the memory.
The function of the tracing means for writing to the physical address can be simplified, and the memory management device can be simplified.

(7) Seventh invention A memory management device according to a seventh invention is the memory management device according to any one of the first to sixth inventions, wherein the definition is defined in a plurality of logical address spaces respectively. The layout means includes a space definition that defines the section to which the section belongs, and a section definition that defines one or more modules that belong to each section. , The logical address of the section defined in the trace definition and the first
And the mapping unit can release the association with the first physical address to the logical address of the section defined in the trace definition. It is a thing.

In this case, the access history can be acquired by a simple operation of defining a section in the trace definition.

[0030]

(Embodiment 1) A memory management device according to Embodiment 1 of the present invention will be described below. FIG. 1 is a block diagram showing a configuration of the memory management device according to the first embodiment.

The memory management device 100 in FIG. 1 holds a plurality of module information 101, a plurality of section definitions 102, and a plurality of space definitions 103.

The module information 101 describes, for each module, a module identifier for identifying the module and information on a program such as a code and a data size of the module indicated by the module identifier.

The section definition 102 defines, for each section, a section identifier for identifying a section and a module identifier for identifying one or a plurality of modules belonging to the section indicated by the section identifier.

Further, the space definition 103 includes a space identifier for identifying the logical address space, a section identifier for identifying one or a plurality of sections belonging to the logical address space indicated by the space identifier, A task identifier for identifying a task to be switched to the logical address space indicated by the identifier is defined for each logical address space.

The memory management device 100 includes
4. Plurality of address conversion tables 105, mapping means 10
6. It comprises an address conversion table switching means 107, a tracing means 108 and a history obtaining means 110.

The arranging means 104 includes the module information 101
And section definition 102 and space definition 103,
A section belonging to each of the plurality of logical address spaces is read, and a module arrangement is determined for each section of the plurality of logical address spaces. That is, the arrangement unit 104 determines the arrangement of the module in each of the plurality of logical address spaces.

The mapping means 106 performs mapping for determining the correspondence between logical addresses and physical addresses for modules arranged for each logical address space by creating the address conversion table 105.

Each of the plurality of address conversion tables 105 has a one-to-one correspondence with one of the plurality of logical address spaces, and thus has a one-to-one correspondence with one of the plurality of tasks. 2 shows the correspondence between logical addresses and physical addresses in a logical address space (task).

The address conversion table switching means 107 switches the address conversion table 105 in response to a task switching instruction. Since the address conversion table 105 has a one-to-one correspondence with the logical address space, the address conversion table 105
Switching means switching of the logical address space.

The trace means 108 detects, during the execution of the program, whether or not there is a write request to an unsupported logical address which is not associated with a physical address in the address conversion table 105 switched by the address conversion table switching means 107. I do. The write request to the unsupported logical address not associated with the physical address is a type of access request to the unsupported logical address not associated with the physical address. Is called an access exception.
When detecting a write request to an unsupported logical address, the tracing unit 108 causes the mapping unit 106 to map the unsupported logical address to a predetermined physical address. After the writing to the physical address is completed, the tracing unit 108 causes the mapping unit 106 to cancel the mapping between the predetermined physical address and the logical address.

The history acquiring means 110 acquires an access history newly written to a predetermined physical address in response to the notification of the occurrence of the access exception.

In this embodiment, the address conversion table 105
The address conversion table switching means 107 corresponds to a logical address space switching means, and the section definition 102 and the space definition 103 correspond to a definition indicating a correspondence.

The arrangement means 104 and the mapping means 1
06, the address conversion table switching means 107, the tracing means 108, and the history obtaining means 110, the CPU (Central Processing Unit) executes a program stored in a storage device such as a ROM (Read Only Memory) or a RAM (Random Access Memory). By executing the program on a memory. Also, module information 101, section definition 10
2 and the space definition 103 are stored in advance in a storage device such as a ROM or a hard disk device as a file. Further, after the address conversion table 105 is created by the mapping means 106, it is stored in a storage device such as a RAM or a hard disk device.

FIG. 2 is a conceptual diagram showing an example of the module information 101, the section definition 102, and the space definition 103 held by the memory management device 100. FIG.
FIG. 3 is a conceptual diagram illustrating an example of mapping performed by a memory management device 100.

The memory management apparatus 100 includes, in the module information 101 of FIG. 2, module identifiers 211 to 213 indicating modules “module 1”, “module 2” and “module 3”, and module identifiers 211 to 213, respectively. Describes the code address, code size, data address, and data size of the module indicated by.

The section definition 102 includes section identifiers 221 to 2 indicating sections “section 1”, “section 2” and “section 3”, respectively.
23, and module identifiers 211 to 213 indicating modules “module 1”, “module 2” and “module 3” respectively belonging to the section indicated by each of the section identifiers 221 to 223.

The space definition 103 includes space identifiers 231 and 232 indicating logical address spaces “space 1” and “space 2”, respectively, and space identifiers 231 and 232.
“Section 1” belonging to the logical address space indicated by
Section identifiers 221 to 223 indicating sections “section 2” and “section 3”, respectively
And task identifiers 241 and 242 respectively indicating tasks “task 1” and “task 2” to which the logical address space indicated by each space identifier 231 and 232 belongs.

Using the module information 101, the section definition 102, and the space definition 103 shown in FIG. 2, the logical address spaces “space 1” and “space 2” indicated by the space identifiers 231 and 232 are shown in Tables 1 and 2, respectively. By creating the address conversion table shown in Table 2, the mapping shown in FIG. 3 is performed. However, when no access exception has occurred, the mapping between the logical address “0x3100000” and the physical address “0x9008000” surrounded by the dotted line in Table 2 is not performed.

[0049]

[Table 1]

[0050]

[Table 2]

FIG. 3 shows the correspondence between the two logical address spaces LA and LB and the physical address space PS. In this example, the logical address space LA corresponds to “space 1”, and the logical address space LB corresponds to “space 2”.

Next, the operation of the memory management device 100 will be described. At the time of system initialization, the memory management device 100 arranges the mapping unit 104 to perform the mapping shown in FIG.
Start The activated arrangement means 104 further activates the mapping means 106.

The arranging means 104 refers to the space definition 103 and reads that “section 1” indicated by the section identifier 221 belongs to the logical address space “space 1” indicated by the space identifier 231.

Next, the arranging means 104 sends the section definition 1
02, it is read that “module 1” indicated by the module identifier 211 belongs to “section 1” indicated by the section identifier 221.

Further, the arranging means 104 refers to the module information 101 and reads the code address, code size, data address and data size of “module 1” indicated by the module identifier 211. Then, the arranging unit 104 arranges the code address and the data address of “module 1” indicated by the module identifier 211 on the logical address space “space 1” indicated by the space identifier 231. Thereby, “module 1” is arranged in “space 1”.

Next, the arranging means 104 sets the space identifier 23
It is read that “section 2” indicated by the section identifier 222 belongs to the logical address space “space 1” indicated by “1”, and the space definition 103, section definition 102, and module information are read in the same manner as in “section 1”. 101, the module identifier 21
The code address and the data address of “module 2” indicated by “2” are arranged on a logical address space of “space 1” indicated by the space identifier 231. Thereby, “module 2” is arranged in “space 1”.

Similarly, the arranging means 104 sets the space definition 10
3 and the section identifier 222 in the logical address space “space 2” indicated by the space identifier 232.
Is read, and based on the space definition 103, the section definition 102, and the module information 101, the code address and the data address of the "module 2" indicated by the module identifier 212 are read by the space identifier 232. It is arranged on a logical address space called “space 2” as shown. Thereby, “module 2” is arranged in “space 2”.

The arranging means 104 generates the space definition 103
, “Space 2” indicated by the space identifier 232
It reads that “section 3” indicated by the section identifier 223 belongs to the logical address space, and based on the space definition 103, section definition 102, and module information 101, the code address of “module 3” indicated by the module identifier 213 and "Space 2" indicated by the data identifier and the space identifier 232
Are arranged in a logical address space. Thereby,
“Module 3” is arranged in “Space 2”.

The mapping means 106 has the space identifier 23
In a logical address space “space 1” indicated by “1”, the allocating unit 104 associates the physical address with the logical address where the code address and the data address are allocated, and creates the address conversion table 105 shown in Table 1.

Next, in the logical address space “space 2” indicated by the space identifier 232, the mapping means 106 associates the physical address with the logical address in which the code address and the data address are arranged by the arranging means 104, and Address conversion table 105 shown in FIG.
Create

In the above case, "space 1" and "space 2"
Of the logical address “0x110000” of the logical address space LA, the “module 2” indicated by the module identifier 212 belongs to both of them.
The code address and the data address of “module 2” are arranged at “00” and “0x2100000”, respectively. Accordingly, the mapping unit 106 converts the physical address “0x80001000” into the logical address “0x11000000” in the logical address space LA and the logical address “0x110000” in the logical address space LB.
00 ”.

Similarly, the mapping means 106 stores the physical address “0x90001000” in the logical address space L
A logical address “0x2100000” and logical address “0x2100000” of logical address space LB
0 ”.

As described above, the logical address space L shown in FIG.
The correspondence between A, LB and the physical address space PS is determined.

When creating the address conversion table 105, the mapping means 106 refers to the space definition 103 to associate a task with a logical address space. The address conversion table switching means 107 holds information that Table 1 corresponds to “Task 1” and Table 2 corresponds to “Task 2”.

After the system initialization is completed, the address conversion table switching means 107 responds to the task switching instruction by
Switching of the address conversion table 105 as shown in Tables 1 and 2 is performed.

For example, when performing “task 1” indicated by the task identifier 241 and then performing “task 2” indicated by the task identifier 242, the address conversion table switching means 107 stores the address conversion table 105 in the space identifier Table 2 corresponding to the logical address space “space 2” indicated by the space identifier 232 from Table 1 corresponding to the logical address space “space 1” indicated by 231
Switch to. In other words, the address conversion table switching unit 107 switches from “space 1” to “space 2” by switching the address conversion table 105.

According to the memory management apparatus 100 of the present embodiment, the same “module 2” belonging to different logical address spaces “space 1” and “space 2” is the same by the arrangement unit 104 and the mapping unit 106. Mapping is performed for each logical address space so as to be assigned to the physical address. As a result, even when the address conversion table switching means 107 switches between “space 1” and “space 2” in response to the task switching, “module 2” can be used in common. That is,
In the memory management device 100, two different tasks such as “task 1” indicated by the task identifier 241 and “task 2” indicated by the task identifier 242 can share the same “module 2”.

Next, the acquisition of the access history to the memory will be described. 1 detects a write request (access exception) to a logical address that is not mapped in the physical address space PS during execution of the program. For example, when the address conversion table 105 in Table 2 is selected by the address conversion table switching unit 107 and a write request is issued to the logical address “0x3100000”, the tracing unit 108 is not mapped to the logical address “0x3100000”. It detects that a write request has been made to a logical address (access exception).

When detecting the access exception, the tracing means 108 causes the mapping means 106 to map the unmapped logical address to a predetermined physical address in the physical address space PS. For example, the mapping unit 106 stores the logical address “0x310” in the physical address “0x9008000” of the physical address space PS.
00000 "is mapped. Then, the tracing unit 108 executes a write request to the logical address. For example, a write instruction to the logical address “0x3100000” is executed. As a result, some data is written to the physical address “0x9008000”.

Thereafter, the tracing means 108 causes the mapping means 106 to release the mapping between the physical address and the logical address mapped in response to the write request. For example, the mapping unit 106 releases the mapping between the physical address “0x90000000” and the physical address “0x3100000”. Thus, when there is a write request to the logical address “0x3100000” again, the access exception can be detected by the trace unit 108.

The access history is acquired by the history acquisition means 1
10 is performed by reading the contents of a predetermined physical address. Since the physical address to which the access history is written is predetermined, the history acquisition unit 110 can acquire the access history even if the mapping is released. For example, a predetermined physical address “0x900
08000 ”is the logical address“ 0 ”
If the flag indicates the presence / absence of a write request to “x3100000”, the physical address “0x900080”
The logical address “0” is read by reading the data “00”.
x3100000 ”can be monitored.

Further, a predetermined physical address “0x9000”
8000 ”is the logical address“ 0x
If the count value indicates the number of write requests to “3100000”, the physical address “0x90008”
By reading the data of "000", the number of accesses to the logical address "0x3100000" can be monitored. In order to make such writing,
During the program, the logical address "0x3100000"
An instruction for writing a flag or an instruction for writing a count value to “0” is described.

According to the memory management device 100 of the present embodiment, the unsupported logical address “0x3100000”
Tracing means 108 triggered by an access request to
When the access history to the logical address “0x31000000” is written to the physical address “0x90000000”, the history acquisition unit 110 acquires the access history to the logical address “0x31000000” from the physical address “0x90000000”, Specific access to memory can be monitored. Thereby, the maintainability of the memory management device 100 can be improved.

In FIG. 2, the case where "module 1" to "module 3" correspond one-to-one with "section 1" to "section 3" has been described. However, as shown in FIG. A plurality of “module 1” and “module 2” indicated by the module identifiers 211 and 212 correspond to one “section 4” indicated by “.”, And the module identifiers 212 and 212 correspond to one “section 5” indicated by the section identifier 225.
A plurality of “module 2” and “module 3” indicated by 213 correspond, and a module identifier 21 corresponds to “section 6” indicated by a section identifier 226.
4 can be configured to correspond.

For example, by defining “section 4” as a set of modules handled in the privileged mode and defining another “section 5” as a set of modules handled in the non-privileged mode, “section 4” and “section” are defined. In "5", a handling rule for "module 2" can be separately provided. As a result, modules that have the same function but must be handled differently are assigned task identifiers 243 and 244 in the logical address spaces “space 3” and “space 4” indicated by the space identifiers 233 and 234, respectively. Can be shared between “task 3” and “task 4”.

(Embodiment 2) FIG. 5 is a block diagram showing a configuration of a memory management device according to Embodiment 2 of the present invention.

The memory management apparatus 300 shown in FIG. 5 includes an arrangement unit 304, a plurality of address conversion tables 105, a mapping unit 306, an address conversion table switching unit 107, and a tracing unit 308.

The memory management device 300 shown in FIG. 5 is similar to the memory management device 100 shown in FIG.
01, a plurality of section definitions 102 and a plurality of space definitions 103. The memory management device 300 differs from the memory management device 100 of FIG.
9 is held.

The memory management device 300 determines that the trace definition 3
09, and the functions of the arrangement unit 304, the mapping unit 306, and the trace unit 308 are different from those of the arrangement unit 104, the mapping unit 106, and the trace unit 108 of the memory management device 100.

The trace definition 309 defines a trace identifier for identifying a trace, and a section identifier for identifying one or a plurality of sections belonging to the section indicated by the trace identifier.

The arranging means 304 stores the module information 101
And section definition 102 and space definition 103,
A section belonging to each of the plurality of logical address spaces is read, and a module arrangement is determined for each section of the plurality of logical address spaces. Also,
The placement unit 304 receives the notification of the detection of the access exception from the tracing unit 308 described later, and
02, the module information 101, and the space definition 103, the module of the section for which the access request has been issued is arranged in the logical space corresponding to the address conversion table 105, and is mapped by the mapping means 306 described later. Further, the arrangement unit 304 instructs the mapping unit 306, which will be described later, a section to be unmapped based on the trace definition 309.

The mapping means 306 creates the address conversion table 105, and performs mapping for determining the correspondence between logical addresses and physical addresses for the modules arranged for each logical address space by the arranging means 304. . Also, the mapping means 30
No. 6 releases the correspondence between the logical address and the physical address of the section specified by the arrangement unit 304.

The trace means 308 detects an access request (access exception) to an unsupported logical address that is not associated with a physical address during execution of the program. An access request to an unsupported logical address includes a read request from the memory in addition to a write request to the memory. When the tracing unit 308 detects an access exception, the tracing unit 308 reports that the access exception has been detected.
Notify. Further, the tracing unit 308 detects the end of the step execution for accessing the unsupported logical address, and instructs the arrangement unit 304 to cancel the mapping.

The history acquisition means 110 is provided by the tracing means 30
In response to the notification of the occurrence of the access exception given from 8,
Before the mapping means 306 cancels the mapping, the access history is acquired from the physical address associated with the unsupported logical address by the mapping of the mapping means 306.

Note that the arrangement means 304 and the mapping means 3
06, tracing means 308 and history acquiring means 310
Is realized by a CPU executing a program stored in a storage device such as a ROM on a memory such as a RAM. Also, the trace definition 309 is stored in the RO
M and stored in a storage device such as a hard disk device in advance.

FIG. 6 is a conceptual diagram showing the configuration of module information 101, section definition 102, space definition 103, and trace definition 309 held by the memory management device 300. FIG. 7 is a conceptual diagram illustrating an example of mapping performed by the memory management device 300.

The configurations of the module information 101, section definition 102 and space definition 103 in FIG. 6 are the same as the module information 101, section definition 102 and space definition 103 in FIG. The trace definition 250 includes a trace identifier 250 indicating a trace “trace 1”.
And a section identifier 251 indicating a section “section 3” belonging to “trace 1”.

Using the module information 101, the section definition 102, and the space definition 103 shown in FIG. 6, the logical address spaces “space 1” and “space 2” indicated by the space identifiers 231 and 232 are shown in Tables 3 and 4, respectively. The mapping shown in FIG. 7 is performed by creating the address conversion table shown in FIG. However, the mapping between the logical address “0x12000000” and the physical address “0x800000000” and the mapping between the logical address “0x2200000” and the physical address “0x9000002” surrounded by the dotted line in Table 4 are in the state where no access exception occurs. Has been released.

[0089]

[Table 3]

[0090]

[Table 4]

The correspondence between the two logical address spaces LA and LB in FIG. 7 and “space 1” and “space 2” is the same as in FIG.

Next, the operation of the memory management device 300 will be described. At the time of system initialization, the memory management device 300 arranges the mapping unit 304 to perform the mapping shown in FIG.
Start The activated arrangement unit 304 further activates the mapping unit 306. The arranging unit 304 and the mapping unit 306 are provided by the memory management device 10 of FIG.
0, the mapping shown in FIG. 3 is performed.

Next, the arranging means 304 sets the trace definition 3
09, the trace “trace 1” indicated by the trace identifier 250 is added to the section identifier 25
Read that "section 3" indicated by 1 belongs.

The arrangement unit 304 refers to the space definition 103 and reads that “section 3” belongs to “space 2”. Next, the arranging means 304 executes the section definition 10
Referring to FIG. 2, it is read that “module 3” belongs to “section 3”. Further, the arrangement unit 304 refers to the module information 101 and reads the code address of “module 3”, the data address, the code size, and the data size. Thereby, the physical address to be released is recognized by the arrangement means 304. Then, the arrangement unit 304 instructs the mapping unit 306 to release the logical address and the physical address for “section 3”.

Next, the mapping means 306 is arranged
04, the logical address “0x” shown in Table 2
12000000 "and physical address" 0x800020 "
00 and the logical address “0x2200”
0000 ”and the physical address“ 0x9002000 ”, and the logical address“ 0x110000 ”is released.
00 "and the physical address" 0x80001000 "and the logical address" 0x2100000 "
The address conversion table shown in Table 4 is created while leaving the mapping between the address and the physical address “0x90001000”.

After the system initialization is completed, the memory management device 3
The address management table switching means 107 of FIG. 1 performs the task switching by switching the address conversion tables 105 as shown in Tables 3 and 4 in response to the task switching instruction. Same as 100.

According to the memory management device 300 of the present embodiment, like the memory management device 100 of FIG. 1, “task 1” indicated by the task identifier 241 and “task 2” indicated by the task identifier 242. Two different tasks can share the same “module 2”.

Next, the acquisition of the access history to the memory will be described. The trace means 308 in FIG. 5 detects that a write request has been made to an unmapped logical address (access exception) during execution of the program. For example, when the address conversion table 105 in Table 4 is selected by the address conversion table switching unit 107 and a write request to the logical address of “section 3” is issued, the trace unit 308 detects an access exception.

When detecting the access exception, the tracing unit 308 instructs the mapping unit 304 on the mapping of “Section 3” that is not mapped. The arranging means 304 determines the section definition 1 in the “space 2”.
02 and the module information 101, the "section 3" is arranged. After that, the arranging unit 304 activates the mapping unit 306 and, based on the arrangement of the “section 3” performed by the arranging unit 304, sets “section 3”
Is performed. For example, the mapping means 30
6 is a logical address “0x12000” as shown in FIG.
000 "is mapped to a physical address" 0x8002000 "and" 0x2200000 "is mapped to a physical address" 0x9000002 ".
Then, by the step execution of “module 3”, the flag indicating the execution of “module 3” is changed to the physical address “0x”.
90002000 ".

The tracing unit 308 notifies the history obtaining unit 310 that an access exception has occurred. The history acquisition unit 310 determines the physical address “0x9002000” based on the mapping performed by the mapping unit 306.
, A flag indicating the execution of “module 3” is obtained.

Thereafter, the tracing unit 308 instructs the arranging unit 304 to release the mapping of “Section 3”. The arrangement unit 304 causes the mapping unit 306 to release the mapping of “section 3”. Thus, when a new access request is made to the logical address of “section 3”, the tracing unit 308 can detect an access exception.

According to the memory management apparatus 300 of the present embodiment, the access request to the unsupported logical address of “section 3” is triggered by the tracing means 308 to access the logical address of “section 3”. Is written to the physical address “0x9002000”, the history acquisition unit 310 can acquire the access history to the logical address of “Section 3” from the physical address and monitor the specific access to the memory. . Thereby, maintainability of the memory management device 300 can be improved.

(Embodiment 3) FIG. 8 is a block diagram showing a configuration of a memory management device according to Embodiment 3 of the present invention.

The memory management device 400 shown in FIG. 8 includes an arrangement unit 304, a plurality of address conversion tables 105, a mapping unit 306, an address conversion table 107, and a tracing unit 40.
8 and a history acquisition unit 410.

The memory management device 400 shown in FIG. 8 is similar to the memory management device 300 shown in FIG.
01, multiple section definitions 102, multiple space definitions 1
03 and the trace definition 309.

The memory management device 400 includes the tracing unit 4
08 and the function of the history acquisition unit 410 are different from those of the memory management device 300 shown in FIG. Memory management device 40
0, the trace unit 408 and the history acquisition unit 4
The configuration other than 10 is the same as that of the memory management device 300.

The trace means 408 detects an access request (access exception) to an unsupported logical address that is not associated with a physical address during execution of a program. When detecting the access exception, the tracing unit 408 causes the arranging unit 304 to refer to the trace definition 309,
For the section for which the access request is issued, module information 101, section definition 102, and space definition 103
Based on the above, the module of the section for which the access request is issued is arranged in the logical space corresponding to the address conversion table 105 currently used by the arrangement means 104.

The tracing means 408 detects the end of the execution of the step for accessing an unsupported logical address, instructs the arranging means 304 to release the mapping, and writes the access history to a predetermined physical address.

The history acquiring means 410 is provided with the tracing means 408
In response to the notification of the occurrence of an access exception given by
The trace unit 308 acquires the access history from a predetermined physical address where the access history is written.

Note that the tracing means 408 and the history obtaining means 410 are realized by the CPU executing a program stored in a storage device such as a ROM on a memory such as a RAM.

The memory management device 400 has the module information 101 and the section definition 10 having the configuration shown in FIG.
2, and holds a space definition 103 and a trace definition 309. FIG. 9 is a conceptual diagram illustrating an example of mapping performed by the memory management device 400.

By creating the address conversion tables shown in Tables 3 and 4, the mapping shown in FIG. 9 is performed as in the case of the memory management device 300.

Next, the operation of the memory management device 400 will be described. At the time of system initialization, the memory management device 400 performs the mapping unit 304 to perform the mapping shown in FIG.
Start The activated arrangement unit 304 further activates the mapping unit 306. The arrangement unit 304 and the mapping unit 306 perform the mapping shown in FIG. 9 in the same manner as the memory management device 300 of FIG.

Next, the arrangement unit 304 refers to the module information 101, the section definition 102, the space definition 103, and the trace definition 309, and refers to the memory management device 3 shown in FIG.
As in the case of 00, the mapping of “section 3” is released.

After the system initialization is completed, the memory management device 4
The reason that the address conversion table switching means 107 of 00 performs the task switching by switching the address conversion tables as shown in Tables 3 and 4 in response to the task switching instruction is the same as that of the memory management apparatus 300 in FIG. Is the same as

According to the memory management device 400 of the present embodiment, similarly to the memory management device 300 of FIG.
2 different from each other such as “task 2” indicated by 2
Two tasks can share the same “module 2”.

Next, acquisition of the access history to the memory will be described. The trace means 408 in FIG. 8 detects an access exception. For example, when the address conversion table 105 in Table 4 is selected by the address conversion table switching unit 107 and an access request is made to the logical address of “Section 3”, the tracing unit 408 outputs the logical address that is not mapped. Is detected (access exception).

When detecting an access exception, the tracing unit 408 instructs the mapping unit 304 to perform mapping on the unmapped “section 3”. The arranging means 304 determines the section definition 1 in the “space 2”.
02 and the module information 101, the "section 3" is arranged. After that, the arranging unit 304 activates the mapping unit 306, and based on the arrangement of “section 3” performed by the arranging unit 304, sets “section 3”
Perform mapping.

The tracing means 308 is "module 3"
, And writes the access history of “module 3” to a predetermined physical address. For example, the physical address “0x90009” in the physical address space PS in FIG.
000 ”.

The trace means 408 notifies the history acquisition means 410 that the access history has been written in response to the access exception. The history obtaining unit 410 obtains the access history from the physical address “0x9000000” to which the trace unit 408 has written the access history. The access history written by the trace unit 408 includes, for example, a flag indicating whether an access exception has occurred, a counter value indicating the number of access exceptions, a program (instruction) in which the access exception has occurred, a time in which the access exception has occurred, Alternatively, there is some state variable at the time when the access exception occurs.

Thereafter, the tracing unit 408 instructs the arranging unit 304 to cancel the mapping of “section 3”. The arrangement unit 304 causes the mapping unit 306 to release the mapping of “section 3”. Thus, when there is a new access request to the logical address of “section 3”, the tracing unit 408 can detect an access exception.

According to the memory management apparatus 400 of the present embodiment, the access request to the unsupported logical address of “section 3” is triggered by the tracing means 408 to access the logical address of “section 3”. Is written to the physical address “0x9000000”, the history acquisition unit 410 stores the access history to the logical address of “section 3” in the physical address “0x90000”.
0009000 "to monitor specific access to the memory. Thereby, maintainability of the memory management device 400 can be improved.

When the mapping means 306 cancels the mapping, the arranging means 304 stores the correspondence between the physical address to be unmapped and the logical address. The correspondence with the logical address may be the same as the previous mapping.

In the above embodiment, the access history is acquired after the step execution is completed. However, the access history may be acquired before the instruction for executing the step is issued.

Although access to the section defined in the trace definition 309 is configured to always be traced, tracing may be performed selectively. For example,
A condition may be added to the trace definition, and the tracing means 408 may write to the trace area only when the condition of the trace definition is true. For example, there is added a condition that an instruction to execute a step execution by accessing an unsupported logical address is ranked, and only when an instruction of a predetermined rank or higher is executed, a trace is performed.

(Embodiment 4) FIG. 10 is a block diagram showing a configuration of a memory management device according to Embodiment 4 of the present invention.

The memory management device 600 shown in FIG. 10 includes an arrangement unit 304, a plurality of address conversion tables 105, a mapping unit 306, an address conversion table switching unit 107, a trace unit 608, a history acquisition unit 410, and a time management unit 611. .

The memory management device 600 of FIG. 10 holds a plurality of module information 101, a plurality of section definitions 102, a plurality of space definitions 103, and a trace definition 309, similarly to the memory management device 400 of FIG.

In the memory management device 600 shown in FIG. 10, the function of the tracing means 608 is different from the function of the tracing means 408 of the memory management device 400. Further, the memory management device 600 is different from the memory management device 400 in that a time management unit 611 is provided.

The time management means 611 repeatedly activates a trace means 608 and a history acquisition means 410, which will be described later, at predetermined time intervals. The trace unit 608, when activated by the time management unit 611, instructs the arrangement unit 304 to release the mapping of the section defined in the trace definition 309. Then, the tracing means 608
Detects an access request (access exception) to an unsupported logical address that is not associated with a physical address during execution of a program. When detecting the access exception, the tracing unit 608 causes the arranging unit 304 to refer to the trace definition 309 and, based on the section definition 102, the module information 101, and the space definition 103,
In step 4, the module of the section for which the access request is issued is arranged in the logical space corresponding to the address conversion table 105 currently used. The tracing unit 608 writes the access history to a predetermined physical address and instructs the arrangement unit 304 to cancel the mapping.

When the time management means 611 instructs the tracing means 608 to stop acquiring the access history, the tracing means 608 changes the mapping of the section defined in the trace definition 309 to the arranging means 304. To instruct.

The history acquisition means 410 is provided by the tracing means 60
In response to the notification of the occurrence of the access exception provided by the tracing means 8 before the tracing means 608 cancels the mapping,
The tracing unit 608 acquires the access history from the physical address where the access history is written.

In this embodiment, the time management means 61
1 corresponds to the management means. The tracing unit 608 and the time management unit 611 are implemented when the CPU executes a program stored in a storage device such as a ROM on a memory such as a RAM.

Next, the operation of the memory management device 600 will be described. The memory management device 600 includes a time management unit 6
When the trace management unit 11 activates the trace unit 608 and acquires the trace history, the same operation as that of the memory management device 400 in FIG. 8 is performed, and the time management unit 611 activates the trace unit 608. If not,
The same operation as when the tracing means 108 in FIG. 1 does not acquire the access history is performed.

In the memory management device 600 of the present embodiment, as in the memory management device 100 of FIG. 1, “task 1” indicated by the task identifier 241 and “task 2” indicated by the task identifier 242 are used. Two different tasks can share the same “module 2”. In addition, the release of the mapping is not always performed every time an access request is made, but the time management means 6 is not used.
11 is performed only when the tracing unit 608 is activated, and the memory management device 600 operates efficiently. In addition,
In the above-described embodiment, the mapping is released every predetermined time. However, the trace unit 608 and the history acquisition unit 410 may be activated intermittently by using another element other than the time as a trigger. Good.

In the memory management apparatuses 100, 300, 400, and 600 according to the first to fourth embodiments, the allocation module 104 or 304 allocates the shared module to the same logical address in different logical address spaces and uses the same module. Although the logical addresses of the modules are allocated to the same physical address, the shared modules may be allocated to different logical addresses in different logical address spaces, and the logical addresses of the same module may be allocated to the same physical address.

Further, in the first to fourth embodiments, the case where information relating to only the code and data of the program is described in the module information 101 has been described, but information such as data having a stack and an initial value is described. Alternatively, such information can be mapped.

[0138]

According to the memory management device of the present invention,
It is possible to prohibit direct access to memory between different tasks except for necessary modules, and to share only necessary modules between different tasks. Further, a specific access to the memory can be monitored, triggered by an access request to an unsupported logical address that is not associated with a physical address.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a memory management device according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an example of module information, a section definition, and a space definition held by the memory management device of FIG. 1;

FIG. 3 is a conceptual diagram showing an example of mapping performed by the memory management device of FIG. 1;

FIG. 4 is a conceptual diagram showing another example of module information, section definition, and space definition held by the memory management device of FIG. 1;

FIG. 5 is a block diagram showing a configuration of a memory management device according to a second embodiment of the present invention.

6 is a conceptual diagram showing an example of module information, section definition, space definition, and task definition held by the memory management device of FIG.

7 is a conceptual diagram showing an example of mapping performed by the memory management device in FIG.

FIG. 8 is a block diagram showing a configuration of a memory management device according to a third embodiment of the present invention.

9 is a conceptual diagram showing an example of mapping performed by the memory management device in FIG.

FIG. 10 is a block diagram showing a configuration of a memory management device according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a conventional memory management device.

[Explanation of symbols]

 100, 300, 400, 600 Memory management device 101 Module information 102 Section definition 103 Space definition 104, 304 Placement means 105 Address conversion table 106, 306 Mapping means 107 Address conversion table switching means 108, 308, 408, 608 Trace means 110, 310, 410 History acquisition means 309 Trace definition 611 Time management means

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B005 LL04 MM32 SS14 VV12 VV24 5B017 BA06 BB08 CA01 5B042 GA23 GA33 GC08 HH30 JJ46 KK07 MA08 MC03 MC15 5B060 AB26 AC06 KA10 5B098 AA04 GA04 GD04 GD14 JJ07 JJ08

Claims (7)

[Claims] 1. A memory management device for associating a physical address of a memory with a plurality of logical addresses, wherein each of the plurality of logical address spaces is defined based on a definition indicating a correspondence between the plurality of logical address spaces and the plurality of modules. Allocating means for arranging a module in a module, mapping means for associating a physical address with a logical address in a logical address space in which a module is allocated by the allocating means based on module information indicating physical addresses of a plurality of modules, and task switching. Logical address space switching means for switching the plurality of logical address spaces associated by the mapping means in response to an instruction; and associating physical addresses in the logical address space switched by the logical address space switching means. Unpaired When there is an access request to the logical address, the mapping unit associates the uncorresponding logical address with the first physical address of the memory, and accesses the uncorresponding logical address. Tracing means for writing a history of access to the unsupported logical address to a second physical address of the memory; and obtaining a history of obtaining an access history from the second physical address of the memory. And a memory management device. 2. The tracing means, after the access to the unsupported logical address is completed, causes the mapping means to release the association between the unsupported logical address and the first physical address. The memory management device according to claim 1, wherein: 3. The memory management device according to claim 2, further comprising management means for intermittently activating said trace means and said history acquisition means. 4. The memory management device according to claim 3, wherein said management means activates said trace means and said history acquisition means at predetermined time intervals. 5. The tracing means, when not activated by the management means, causes the arranging means to arrange a module, and causes the mapping means to determine a correspondence between the unsupported logical address and the first physical address. The memory management device according to claim 3, wherein the memory management device performs association. 6. The tracing means sets the first physical address as the second physical address when there is a write request as an access request to an unsupported logical address not associated with a physical address. 6. The memory management device according to claim 1, wherein an access history of the unsupported logical address is written to the first physical address. 7. The definition indicating the correspondence includes a space definition defining a section belonging to each of the plurality of logical address spaces, and a section definition defining one or a plurality of modules belonging to each section. The mapping unit maps a correspondence between a logical address of a section defined in the trace definition and the first physical address based on a trace definition defining a section for which an access history is acquired. Wherein the mapping unit is capable of causing the mapping unit to associate the logical address of the section defined in the trace definition with the first physical address. Items 1 to 6
The memory management device according to any one of the above.