JP2001039797A - Silicon wafer for laminating epitaxial layer and epitaxial wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an epitaxial layer being a thin film on the surface of which trace of COP and LD are almost not generated when it is formed and whose electrical characteristics are improved and the production yield is high. SOLUTION: A silicon wafer is used for laminating an epitaxial layer of a thin film. In the silicon wafer, the number of particles and the number of interstitial dislocations due to crystallization are controlled to be 0 to 10 per wafer, respectively. The silicon wafer has an electrical resistance of <=0.02 Ωcm, and an epitaxial thin layer being a thin film having an electrical resistance of >=0.1 Ωcm is formed on the wafer by a reduced pressure CVD method. The thickness of the epitaxial thin layer is preferably 0.5 to 5 μm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon wafer for laminating a thin-film epitaxial layer and an epitaxial wafer having an epitaxial layer laminated, which are formed by the Czochralski method (hereinafter referred to as CZ method). It is.

[0002]

2. Description of the Related Art Hitherto, epitaxial wafers have been applied first to high performance bipolar transistors and then to bipolar ICs. In an epitaxial wafer, since a single-crystal silicon epitaxial layer having an arbitrary thickness and resistivity can be formed on a silicon wafer serving as a substrate, for example, by forming a high-resistance epitaxial layer on a low-resistance substrate, a high-speed transistor can be formed. Can be realized. Further, effective separation between pn junction elements, which is essential for a bipolar IC, is effectively performed by forming an epitaxial layer. In recent years, in order to further improve the operation speed of a transistor and achieve high performance, it is required to reduce the thickness of a thin epitaxial layer as much as possible.

However, when the epitaxial layer is made as thin as possible (for example, 3 μm or less) to meet this demand, crystal originated particles (hereinafter, referred to as C) are formed on the surface of a silicon wafer serving as a substrate.
It is called OP. ) And interstitial-type La
rge Dislocation Loop, hereinafter referred to as LD. ) Presents a problem. Here, when the silicon wafer after mirror polishing is washed with a mixed solution of ammonia and hydrogen peroxide, pits are formed on the wafer surface, and when this wafer is measured with a particle counter, the pits are detected as particles together with the original particles. This is a defect caused by the crystal. The LD is one of the lattice defects of the crystal, and is also called a dislocation cluster. Or, when a silicon wafer having this defect is immersed in a selective etching solution containing hydrofluoric acid as a main component, pits are generated. Also called a pit.

That is, if COP exists on the surface of a silicon wafer serving as a substrate, traces of COP appear on the surface of the epitaxial layer, following the shape of the surface of the wafer.
If an LD is present on the surface of a silicon wafer serving as a substrate, when an epitaxial layer is formed on the wafer, the wafer becomes an LD on a wafer (substrate) below the epitaxial layer due to heating in an epi furnace, and this LD is exposed.
Increases the defect density on the epitaxial layer surface.

[0005] Traces of COP on the epitaxial layer surface,
When the LD is exposed, these traces and the like show electrical characteristics, such as the time-dependent dielectric breakdown characteristics (Time Dependent) of the oxide film.
It causes deterioration of dielectric breakdown (TDDB), oxide breakdown voltage characteristics (Time Zero Dielectric Breakdown, TZDB), and the like. In addition, if traces of COP and LD are present on the surface of the epitaxial layer, a step occurs in a wiring process of the device, and this step causes disconnection and lowers the product yield. The present applicant has filed a patent application for “thin film epitaxial wafer and method for manufacturing the same” to solve this problem (Japanese Patent Laid-Open No. 10-2090).
56, 10-209057). That is, the present applicants:
According to JP-A-10-209056, the COP density is 1 × 10 ⁵ / cm ³ or less, and C
A method for producing a single crystal silicon substrate having no or a small number of OPs by a CZ method and forming an epitaxial layer having a thickness of less than 4.0 μm under reduced pressure on the substrate and a thin film epitaxial wafer thereof are proposed. did. According to Japanese Patent Application Laid-Open No. 10-209057, a single-crystal silicon substrate doped with a p-type impurity at a high concentration and having no or a small number of COPs on its surface is manufactured by the CZ method. 4.0μ thick under reduced pressure
A method for forming an epitaxial layer of less than m and a thin film epitaxial wafer thereof have been proposed. According to these methods, for example, by forming an epitaxial layer having a thickness of 1 μm,
The number of COPs of 0.13 μm or more on a 6-inch wafer
It can be zero or less.

[0006]

However, in both of the above two methods, a silicon wafer serving as a substrate is formed by a CZ method using a CZ method.
mm / min, the silicon wafer is manufactured from a silicon single crystal pulled at a relatively low speed.
Although the generation of OP can be suppressed, the above problem that LD is generated and LD becomes apparent on the surface of the epitaxial layer has not been solved. SUMMARY OF THE INVENTION An object of the present invention is to provide a silicon wafer for epitaxial layer lamination, which hardly causes traces of COP and LD on the surface of the epitaxial layer when a thin epitaxial layer is formed. Another object of the present invention is to provide an epitaxial wafer in which electrical characteristics are further improved and a thin epitaxial layer having a large yield during manufacturing is formed.

[0007]

The invention according to claim 1 is
A silicon wafer for laminating a thin-film epitaxial layer, wherein particles caused by crystals (COP)
And interstitial dislocations (LD) are 0 to 1 per wafer, respectively.
It is a silicon wafer for epitaxial layer lamination characterized by being zero. Since both COP and LD are silicon wafers with 0 to 10 wafers per wafer,
Even if the thickness of the thin-film epitaxial layer is made extremely thin, no trace of COP is generated on the surface of this epitaxial layer,
In addition, LD does not appear at all. The number of COPs and LDs per wafer refers to the number of wafers having a diameter of 12 inches or less.

According to a second aspect of the present invention, the resistivity of the silicon wafer according to the first aspect is 0.02 Ωcm or less, and reduced pressure chemical vapor deposition (hereinafter, referred to as CVD) is performed on the silicon wafer. This is an epitaxial wafer on which a thin-film epitaxial layer having a resistivity of 0.1 Ωcm or more is formed by a method. By performing epitaxial growth by a low-pressure CVD method, an epitaxial layer having a uniform thickness can be formed while the epitaxial growth temperature is kept low, and autodoping from a high-concentration substrate (wafer) to a thin-film epitaxial layer can be suppressed. At the same time, an epitaxial wafer manufactured by forming a high-resistance epitaxial layer on a low-resistance silicon wafer can realize a high-speed transistor, and has little trace of COP or LD on the surface of the epitaxial layer. Epitaxial wafers have better electrical characteristics and a higher yield during manufacturing.

The invention according to claim 3 is the invention according to claim 2, wherein the thickness of the epitaxial layer of the thin film is 0.5 to 0.5.
It is an epitaxial wafer that is 5 μm. When a transistor is manufactured from this epitaxial wafer by making the thin-film epitaxial layer extremely thin in the above range without lowering the electrical characteristics due to COP and LD on the surface of the silicon wafer serving as the substrate, the operation of the transistor The speed can be further improved to achieve higher performance.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION A silicon wafer for laminating an epitaxial layer of a thin film according to the present invention has a predetermined pulling rate based on the Voronkov theory based on the Boronkov theory. After being pulled up in profile, this ingot is sliced and made. Generally, when a silicon single crystal ingot is pulled up from a silicon melt in a hot zone furnace by the CZ method, defects in the silicon single crystal are as follows.
Point defects and aggregates of point defects (agglomerat)
es: three-dimensional defect) occurs. Point defects have two general forms: vacancy type point defects and interstitial Si type point defects.
A vacancy-type point defect is one in which one silicon atom has separated from one of the normal positions in the silicon crystal lattice. Such holes become hole type point defects. On the other hand, the position of the atom other than the lattice point of the silicon crystal (interstitial site)
When this is found, this becomes an interstitial Si point defect.

[0011] Point defects are generally formed at the interface between the silicon melt (molten silicon) and the ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface starts to cool down with pulling up. During cooling, vacancy-type point defects or interstitial Si-type point defects merge with each other by diffusion to form vacancy agglomerates or interstitial agglomerates. Is formed. In other words, the aggregate is a three-dimensional structure generated due to the merging of point defects. Aggregates of vacancy-type point defects are as described above for C
In addition to OP, LSTD (Laser ScatteringTomograph De
defects or FPDs (Flow Pattern Defects), and the aggregates of interstitial Si-type point defects include defects such as the LD described above. The FPD is a source of a trace exhibiting a unique flow pattern that appears when a silicon wafer produced by slicing an ingot is chemically etched with a Secco etchant for 30 minutes.
The STD is a source that has a refractive index different from that of silicon and generates scattered light when a silicon single crystal is irradiated with infrared rays.

Boronkov's theory states that in order to grow a high-purity ingot with a small number of defects, the pulling speed of the ingot is V (mm / min), and the temperature gradient of the ingot-silicon melt contact surface in a hot zone structure. G (° C / mm)
Is to control V / G (mm ² / min · ° C.). In this theory, as shown in FIG. 1, V / G graphically represents the vacancy concentration and interstitial Si concentration as functions, and the boundary of the vacancy / interstitial Si region on the wafer is determined by V / G. Is explained. More specifically,
When the V / G ratio is above the critical point, an ingot in which vacancy-type point defects predominantly exists is formed, whereas when the V / G ratio is below the critical point, ingots in which interstitial Si-type point defects predominantly exist are produced. It is formed.

[0013] The predetermined pull rate profile of the present invention is that when the ingot is pulled from the silicon melt in a hot zone furnace, the ratio of the pull rate to the temperature gradient (V / G) is an aggregate of interstitial Si type point defects. Aggregates of vacancy-type point defects which are equal to or higher than the first critical ratio ((V / G) ₁ ) for preventing generation of vacancies are located in the region where vacancy-type point defects predominantly exist in the center of the ingot The limiting second critical ratio ((V /
G) ₂ ) It is decided to be kept below.

The pulling speed profile is determined by simulating the reference ingot in the axial direction experimentally or by combining these techniques, based on the above-mentioned Boronkov theory by simulation. That is, this determination is made by checking the axial slice of the ingot and the sliced wafer after the simulation, and repeating the simulation. For the simulation, a plurality of kinds of pulling speeds are determined within a predetermined range, and a plurality of reference ingots are grown. As shown in FIG. 2, the pulling speed profile for the simulation is from a high pulling speed (a) such as 1.2 mm / min to a low pulling speed (c) of 0.5 mm / min and again a high pulling speed (d). It is adjusted to. The low pull rate may be 0.4 mm / min or less, and the change in pull rates (b) and (d) is preferably linear.

A plurality of reference ingots pulled at different speeds are individually sliced in the axial direction. Optimal V /
G is determined from the correlation of the results of the axial slicing, wafer validation and simulation, followed by the determination of the optimal pulling speed profile, which is used to produce the ingot. The actual pulling speed profile will depend on many variables including but not limited to the desired ingot diameter, the particular hot zone furnace used and the quality of the silicon melt.

FIG. 3 shows the fact that a sectional view of the ingot when V / G is continuously reduced by gradually lowering the pulling speed is shown. In FIG. 3, [V] is an abundant region where vacancy type point defects are predominantly present in the ingot, [I] is a region where interstitial Si type point defects are predominantly present, and vacancy type points Perfect regions where no aggregates of defects and no aggregates of interstitial Si-type point defects are present are indicated as [P], respectively. As shown in FIG. 3, the axial position P ₁ of the ingot contains a region where vacancy type point defects at the center dominantly present. Position P ₂ includes an area smaller vacancy type point defects at the center dominantly present as compared to the position P _1. Position P ₄ includes a ring region and the central perfect area that exists dominantly interstitial Si type point defects. The position P ₃ is neither vacancy type point defects at the center, all because Si type point defects nor between grating edge portion is perfect area.

As is apparent from FIG. 3, the wafer W ₁ corresponding to the position P ₁ includes a region in which vacancy type point defects predominantly exist in the center. Wafer W ₂ corresponding to the position P ₂ is,
It includes a region vacancy type point defects are dominantly present in a small area in the center compared to the wafer W _1. Wafer W ₄ corresponding to position P ₄ includes a ring where interstitial Si type point defects predominantly exist and a central perfect region. Position P
_The wafer W3 corresponding to No. ₃ has no vacancy type point defects at the center and no interstitial Si type point defects at the edge portions, so that all are perfect regions.

In a small area in contact with the perfect area of the area where the vacancy type point defects are predominantly present, and in all the perfect areas, neither COP nor LD occurs in the wafer surface. As shown in FIG. 4, OSF ring is generated in the vicinity of half the radius of the wafer W ₁ in the wafer.
Here, OSF is an oxidation-induced stacking fault.
This is an abbreviation of ced Stacking Fault, which is a defect in which micro defects of oxygen precipitates serving as nuclei during crystal growth are introduced, and become apparent in a wafer state by heat treatment such as an oxidation step in manufacturing a semiconductor device. The heat treatment conditions include:
For example, at a temperature of 1000 ° C. ± 30 ° C. in an oxygen atmosphere,
Heat treatment for 5 hours, then at 1130 ° C ± 30 ° C for 1 hour
Heat treatment for up to 16 hours. COP tends to appear in a region surrounded by the OSF ring and in which vacancy-type point defects are predominantly present. In contrast, in the wafer W ₂ OSF is without being ring-shaped, only occurs in the center of the wafer.

The silicon wafer used in the present invention is:
The wafer W ₂ or all are W ₃ of perfect area. As shown in FIG. 5, this silicon wafer W ₂
The SF is manufactured by slicing an ingot grown with a pulling speed profile selected and determined so that the SF is not ring-shaped but is exposed only at the center. FIG. 6 is a plan view thereof. Since the silicon wafer W ₂ OSF does not form a ring, a COP-free. Also LD
There is no occurrence. The silicon wafer W ₃ being is produced by slicing an ingot grown by pulling-up speed profile which is determined by chosen to make all perfect area as shown in FIG. FIG. 8 is a plan view thereof.
This silicon wafer W ₃ is also a COP-free, there is no occurrence of LD.

Here, "COP-free" means that the number of COPs of 0.12 μm or more is substantially zero. Since the size of the COP may vary depending on the manufacturer and model of the particle counter,
In the present specification, “0.12 μm COP” means 0.12 μm for each of a vertically incident type KLA-Tencor SFS6200 series, ADE CR80 series, or Hitachi Electronics Engineering LS6000 series particle counter. COP indicating the value of The value measured by the particle counter is a converted value of polystyrene latex particles, and is not an actual value measured by an atomic force microscope (AFM).

_On the surface of the silicon wafer W ₂ or W ₃ produced by slicing the ingot pulled under the above conditions, an epitaxial layer is formed by epitaxial growth of silicon. For this epitaxial growth, a CVD method is employed from the viewpoint of the crystallinity of the epitaxial layer, mass productivity, simplicity of the apparatus, ease of forming various device structures, and the like. The epitaxial growth of silicon by the CVD method includes, for example, SiCl ₄ , SiHCl ₃ , SiH ₂ C
A raw material gas containing silicon, such as l ₂ or SiH ₄ , is introduced into the reaction furnace together with H ₂ gas, and the silicon wafer W
_This is performed by depositing silicon generated by thermal decomposition or reduction of the source gas on the surface of ₂ or W ₃ . In particular, when a thin-film epitaxial layer is formed, the epitaxial growth temperature can be kept low to form an epitaxial layer having a uniform thickness, and auto-doping from a high-concentration substrate (wafer) to the thin-film epitaxial layer can be suppressed. CVD (10 to 15 Torr) is preferred.

When the epitaxial wafer is an epitaxial wafer for a high-performance bipolar transistor or a bipolar IC, a silicon wafer serving as a substrate is manufactured with a low resistance and an epitaxial layer is manufactured with a high resistance. Such silicon wafer W ₂ or W _3, resistivity of 0.02Ωcm less, preferably 0.01 to 0.02
Ωcm, more preferably 0.015 Ωcm or less, and such an epitaxial layer has a resistivity of 5 Ωcm or more, preferably 10 Ωcm or less.
The above is used. When a silicon single crystal is pulled by the CZ method, B (boron) as a dopant is 3 × 10 ¹⁸ a in the case of a p-type silicon wafer having a low resistance.
at a concentration of not less than toms / cm ³ , and in the case of n-type, 1 × 10 ¹⁸ atoms of Sb (antimony) as a dopant
It is used at a concentration of s / cm ³ or more. When forming a high-resistance epitaxial layer, B ₂ H ₆ ,
Gases such as PH ₃ and AsH ₃ are used.

The thickness of the epitaxial layer of the present invention is 0.5
When the transistor is manufactured from this epitaxial wafer, the operation speed of the transistor can be further improved and the performance can be improved by making the thickness extremely thin to about 5 μm. If the thickness is less than 0.5 μm, it is difficult to make the thickness of the epitaxial layer uniform, and if it exceeds 5 μm, the performance will not be high. The preferred thickness is 1-4 μm.

[0024]

Next, examples of the present invention will be described together with comparative examples. An area corresponding to the position P ₂ shown in <Embodiment 1> FIG. 3 was pulled ingot to cultivate over ingot length. At this time, B (boron) was added as a dopant to 1 ×
Doping was performed at a concentration of 10 ¹⁹ atoms / cm ³ . The silicon wafer sliced from this silicon single crystal ingot (wafer W _{2 in} FIG. 3) is wrapped, chamfered, and mirror-polished to obtain a silicon wafer having a resistivity of 0.02 Ωcm and a diameter of 8 inches. Was prepared. 0.0 at the surface of this silicon wafer
Defects (including COP) having a size of 9 μm or more are measured with a laser particle counter (manufactured by KLA-Tencor, S
FS6200). As a result, 10 wafers were observed per wafer.

A low pressure CVD is applied to the surface of the silicon wafer.
Method (80 Torr) to obtain SiH ₂ C
l _2, and a B ₂ H ₆ gas for adjusting the resistance of the epitaxial layer, a growth temperature of 1080 ° C. and a growth rate of 1 μm.
Under the condition of m / min, an epitaxial layer having a thickness of 3 μm and a resistivity of 5 Ωcm was formed. Thus, an epitaxial wafer having a high-resistance epitaxial layer on a low-resistance substrate was obtained. 0.09 μm on the surface of this epitaxial wafer
Defects of the above sizes (including COP and LD) were examined using the same laser particle counter as above.
As a result, no detection was possible at 0.09 μm or more and less than 0.13 μm, and three samples per wafer were observed at 0.13 μm or more.

Example 2 The ingot was pulled up so that a region corresponding to the position P ₃ shown in FIG. 3 was grown over the entire length of the ingot. At this time, B (boron) was doped at a concentration of 1 × 10 ¹⁹ atoms / cm ^{3 as} a dopant. The silicon wafer sliced from the silicon single crystal ingot (wafer W _{3 in} FIG. 3) is wrapped, chamfered, and mirror-polished to obtain a silicon wafer having a resistivity of 0.02 Ωcm and a diameter of 8 inches. Was prepared. The surface of a silicon wafer serving as a substrate and the surface of an epitaxial wafer are treated with 0.
Defects (including COP and LD) having a size of 09 μm or more were examined using the same laser particle counter as in Example 1. As a result, 10 wafers were observed on the surface of the silicon wafer serving as the substrate, and 7 wafers were observed on the surface of the epitaxial wafer.

<Comparative Example 1> An ingot was pulled up so as to grow a region corresponding to the position P ₄ shown in FIG. 3 over the entire length of the ingot, and a silicon wafer having a diameter of 8 inches (wafer in FIG. W ₄ ) was obtained. At the time of pulling, B (boron) was doped in the same manner as in the example. Except for this, an epitaxial wafer was manufactured in the same manner as in the example. Defects (including COP and LD) having a size of 0.09 μm or more on the surface of the silicon wafer serving as the substrate and the surface of the epitaxial wafer were examined using the same laser particle counter as in the example.
As a result, on the surface of the silicon wafer as the substrate and the surface of the epitaxial wafer, 100 wafers per wafer were observed, respectively.

[0028]

As described above, according to the present invention, when a thin-film epitaxial layer is formed by using a silicon wafer which hardly generates COP and LD in the wafer plane as a substrate for epitaxial layer lamination. COP and LD hardly occur on the surface of the epitaxial layer. As a result, it is possible to obtain an epitaxial wafer on which a thin-film epitaxial layer having improved electrical characteristics and a high yield during manufacturing is formed.

[Brief description of the drawings]

FIG. 1 Based on Boronkov's theory, when the V / G ratio is above the critical point, a vacancy-rich ingot is formed and V
FIG. 7 is a diagram showing that an interstitial-rich ingot is formed when the / G ratio is lower than the critical point.

FIG. 2 is a characteristic diagram showing a change in pulling speed for determining a desired pulling speed profile.

FIG. 3 is a schematic diagram of an X-ray topography showing a vacancy rich area, an interstitial rich area and a perfect area of a reference ingot according to the invention.

FIG. 4 shows a silicon wafer W ₁ corresponding to a position P ₁ in FIG.
The figure which shows the situation in which an OSF ring appears.

5 is a cross-sectional view of the ingot corresponding to the position P _{2 of} FIG. 3 and the silicon wafer W ₂ , which are selected and pulled up so that the OSF is not formed in a ring shape in the center of the present invention, but is exposed only at the center; FIG.

In the center of the silicon wafer W ₂ of FIG. 6] FIG. 3 OSF
The figure which shows the situation in which appears.

FIG. 7 is a cross-sectional view and illustration of the silicon wafer W ₃ of ingot vacancies mass and interstitial mass corresponds to the position P ₃ in FIG. 3 that the absence of the present invention.

FIG. 8 is a plan view of the wafer.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masaki Kimura F-term (reference) in Mitsui Material Silicon Co., Ltd. 1-5-1, Otemachi, Chiyoda-ku, Tokyo 4G077 AA02 AA03 AB01 AB06 BA04 CF10 DB01 5F052 KA05 5F053 AA12 DD01 FF04 GG01 HH04 JJ01 JJ03 KK03 KK10 RR03 RR04

Claims (3)

[Claims] 1. A silicon wafer for laminating a thin-film epitaxial layer, wherein the number of particles and interstitial dislocations caused by the crystal is 0 to 10 per wafer, respectively. . 2. The silicon wafer according to claim 1, wherein the resistivity of the silicon wafer is 0.02 Ωcm or less, and the epitaxial layer of a thin film having a resistivity of 0.1 Ωcm or more is formed on the silicon wafer by low pressure chemical vapor deposition. The formed epitaxial wafer. 3. The method of claim 1, wherein the thickness of the thin film epitaxial layer is 0.5
The epitaxial wafer according to claim 2, which has a thickness of from 5 to 5 m.