JP2001035855A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gettering layer and to inhibit a contamination on metal films in a semiconductor device of an SOI(Silicon-On-Insulator) structure. SOLUTION: A gettering layer 31 is formed in the main surface of a silicon substrate 21 and thereafter, a silicon dioxide layer 22 is formed on the whole surface of the substrate 21. The side of the above main surface of the substrate 21 formed with the layer 22 is laminated to another silicon substrate 23. After the lamination, the surface of the substrate 21 formed with the layer 31 is ground until the substrate 21 is formed in a prescribed thickness and a silicon active layer 24 is formed on the layer 22. Grooves 25 for element isolation are formed in the layer 24 and, after deteriorated layers 4 formed on the exposed surfaces on the interiors of the grooves 15 at the formation of the grooves are removed before heat treatment, the interiors of the grooves 25 are filled to form element isolation regions 28 in the layer 24. After that, a gate insulating film, a gate electrode and the like are formed on an element formation region 29 and an element, such as a transistor, is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.

Generally, in a semiconductor device including a high breakdown voltage element, in order to prevent a latch-up phenomenon of a transistor,
A large area is required for an isolation region between elements. Therefore, the effective chip area is reduced, which hinders high integration. In order to solve this, SOI (silicon on insulator) technology has been proposed. The SOI technology is a technology in which an element formation region made of Si or the like is formed on an insulator (dielectric) such as SiO ₂ and a high breakdown voltage element is formed in the element formation region. According to this technique, latch-up of a transistor can be prevented, and a high withstand voltage element can be formed at a high density.

[0003]

2. Description of the Related Art FIGS. 7 to 11 are diagrams for explaining a manufacturing process of a conventional semiconductor device having an SOI structure in order. In the following description, p-type silicon (S
i) A case where a substrate is used will be described, but the same applies to a case where an n-type silicon substrate is used.

First, a p-type silicon substrate 11 (hereinafter referred to as a first substrate 11) is thermally oxidized to form a silicon dioxide (SiO ₂ ) layer 12 on the entire surface of the substrate (see FIG. 7). . The first substrate 11 is placed on another p-type silicon substrate 13 (this is referred to as a second substrate 13), and
The two silicon substrates 11 and 13 are bonded by performing a thermal oxidation treatment at a temperature of ° C. (see FIG. 8).

Subsequently, the surface of the first substrate 11 is ground and polished to a predetermined thickness, and the silicon active layer 1 is ground.
Expose 4. Up to this point, the second silicon substrate 13
A first substrate 1 is formed on a silicon base layer made of silicon dioxide via a buried layer made of a silicon dioxide layer 12 as an insulator.
Thus, the substrate 1 having the SOI structure provided with the silicon active layer 14 composed of one silicon region is obtained (see FIG. 9).

Subsequently, reactive ion etching (RI
E) A trench (trench) 15 for element isolation is formed in the SOI substrate 1 by processing (see FIG. 10). After a silicon dioxide layer 16 is formed on the exposed surface inside the groove 15, a polysilicon (polycrystalline silicon) layer 17 is formed in the groove 15.
To form an element isolation region 18 (see FIG. 11).
As a result, a trench isolation structure is completed. Thereafter, an element such as a transistor is manufactured by forming a gate insulating film, a gate electrode, and the like in the element formation region 19 partitioned by the element isolation region 18.

[0007]

In the trench forming step by RIE, the silicon active layer 14 is hit with plasma to form the groove 15, so that an altered layer in which a metal element, hydrogen or the like is implanted on the side wall of the groove 15 is formed. Will be done. Therefore, in the above-described conventional manufacturing process, for example, when heat treatment is performed to activate impurities doped in the transistor manufacturing process, a metal element or the like diffuses from the deteriorated layer of the groove 15 into the substrate, thereby contaminating the substrate. There is a possibility that. In other processes, a metal element may be mixed into the substrate.

In order to prevent such contamination by metal elements, when a silicon bulk crystal is used as a substrate, a gettering center is generally formed inside the substrate, and the gettering center is made to absorb the metal element. I have to. However, in the above-mentioned substrate having the conventional SOI structure, since a buried layer made of silicon dioxide is interposed therein, even if a gettering center is formed inside the substrate, it does not work effectively. That is, since a metal element such as Fe or Ni cannot be gettered on a substrate having a conventional SOI structure, the reliability of the gate is low even if a MOS transistor is manufactured using the substrate. There is.

The present invention has been made in view of the above, and has as its object to provide a method of manufacturing a semiconductor device having an SOI structure having a gettering layer.

[0010]

In order to achieve the above object, according to the present invention, when manufacturing a semiconductor device having an SOI structure, a first conductive type getter is provided on a main surface of a first conductive type semiconductor substrate. After forming the ring layer, an insulating layer is formed on the surface of the gettering layer. Then, the main surface side of the semiconductor substrate on which the insulating layer is formed is bonded to another semiconductor substrate of the first conductivity type. After the bonding, the surface of the semiconductor substrate on which the gettering layer is formed is ground until a predetermined thickness is obtained, and the semiconductor region is exposed to form an element formation region.

According to the present invention, in a semiconductor device having an SOI structure, an insulating layer embedded in a substrate is
That is, since the gettering layer is provided in the active layer,
This gettering layer effectively works for gettering impurities such as metal elements mixed during the manufacturing process.

In the present invention, a groove for element isolation is formed in an element formation region, and the altered layer formed on the exposed surface inside the groove at the time of forming the groove is removed before heat treatment, and then the groove is filled. Alternatively, a configuration in which the element isolation region is formed may be adopted. The two semiconductor substrates may be made of silicon, and the gettering layer may be made of polysilicon. In that case, the altered layer is removed using a mixed solution of hydrofluoric acid, nitric acid, and acetic acid. Preferably, in the mixed solution, the ratio of nitric acid to hydrofluoric acid is 20 and the ratio of acetic acid is 50 in terms of volume ratio.

In this way, when a semiconductor device having a trench isolation structure is manufactured, an altered layer, which is a main cause of contamination by a metal element, is produced along with the formation of the groove. Before the metal element is diffused, the altered layer is removed, and metal contamination can be suppressed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings.

FIGS. 1 to 6 are diagrams for explaining a manufacturing process of a semiconductor device having an SOI structure in order. First, a p-type polysilicon layer 3 having a thickness of, for example, 2 μm is stacked on a surface of a p-type silicon substrate 21 (hereinafter, referred to as a first substrate 21) by, for example, a CVD (chemical vapor deposition) method. . Subsequently, the first substrate 21 is thermally oxidized at, for example, 1050 ° C. to form a silicon dioxide layer 22 having a thickness of, for example, 1 μm on the entire surface of the substrate (see FIG. 1). The surface of the polysilicon layer 3 is also oxidized by this thermal oxidation treatment, and the thickness of the polysilicon layer 3 becomes approximately 1.5 μm.

Subsequently, the first substrate 21 is overlaid on another p-type silicon substrate 23 (this is referred to as a second substrate 23). At that time, the surface of the first substrate 21 on the side on which the polysilicon layer 3 is stacked is made to contact the second substrate 23. Then, a thermal oxidation process is performed at 1100 ° C. for 2 hours in a state where the two silicon substrates 21 are overlapped with each other.
23 (see FIG. 2).

Subsequently, the surface of the first substrate 21 is ground and polished to a predetermined thickness, for example, 10 μm, to expose the silicon active layer 24. So far, the second
A buried layer composed of a silicon dioxide layer 22 as an insulator is provided on a silicon base layer composed of a silicon substrate 23, and a gettering layer 31 composed of a polysilicon layer 3 is provided on the buried layer. SOI in which a silicon active layer 24 is provided on a gettering layer 31
A substrate 2 having the structure is obtained (see FIG. 3).

Subsequently, the SOI substrate 2 is formed by well-known photolithography and reactive ion etching.
In the silicon active layer 24, a trench 25 for element isolation having a depth reaching the silicon dioxide layer 22 as an insulating layer is formed (see FIG. 4). At this time, the altered layer 4 into which the metal element, hydrogen, and the like are implanted by being hit with the plasma is generated on the exposed surface inside the groove 25. The metal element contained in the altered layer 4 may diffuse by the heat treatment and contaminate the substrate. Therefore, before performing the heat treatment, the SOI substrate 2 is subjected to an etching process using an acid etching solution to remove the altered layer 4.

The acid etching solution is a mixed solution of hydrofluoric acid, nitric acid and acetic acid. Using this mixed solution, the etching process proceeds in a two-stage reaction in which silicon is first oxidized and then dissolved. Here, the etching rate depends on the degree of dilution with acetic acid. Also, as the concentration of hydrofluoric acid increases, the oxidizing power of the etchant becomes weaker, so that the etching rate can be reduced by nitric oxide (N
The rate is limited by the supply of O). Also, as the concentration of nitric acid increases, the dissolution rate of silicon dioxide by hydrofluoric acid decreases, so that the etching rate is limited by the diffusion of hydrofluoric acid into silicon dioxide. In order to obtain a smooth mirror surface, it is necessary to consider the balance between the supply of nitric oxide and the diffusion of hydrofluoric acid.

Specifically, when expressed in terms of a volume ratio, it is preferable that the ratio of nitric acid is 20 and the ratio of acetic acid is 50 for 1 hydrofluoric acid. When the inventors investigated using an acid etching solution prepared at this volume ratio, the etching rate was substantially the same for silicon and silicon dioxide, and was 200 nm / m 2.
in. The thickness of the altered layer 4 is determined by
It is 10 to 30 nm when analyzed using MS (secondary ion mass spectrometry), AES (Auger electron spectroscopy), RBS (Rutherford backscattering method), or the like. Therefore, if the etching process is performed for about 9 seconds using the acid etching solution having the above-mentioned volume ratio, the altered layer 4 having a thickness of about 30 nm can be removed. The inner peripheral surface of the groove 25 from which the deteriorated layer 4 has been removed by this etching process
Irregularities are reduced, resulting in a smooth mirror surface. As a result, highly reliable element isolation is possible.

Since this etching process is an isotropic etching, the exposed portion (the bottom portion of the groove 25) of the silicon dioxide layer 22, which is an insulating layer, is also etched together with the deteriorated layer 4. However, since the thickness of the silicon dioxide layer 22 is 1 μm, there is no adverse effect even if it is removed by about 30 nm.

After removing the altered layer 4, the SOI substrate 2
Thermal oxidation treatment is performed at 100 ° C. to form a silicon dioxide layer 26 having a thickness of, for example, 600 nm on the exposed surface inside the groove 25. The heat treatment at this time and the two semiconductor substrates 21
Although the crystallization of the polysilicon layer 3 serving as the gettering layer 31 progresses due to the heat treatment at the time of bonding the 23, the crystal grain boundary finally remains in the gettering layer 31, whereby the gettering effect becomes effective. .

Thereafter, the trench 25 is filled with a polysilicon layer 27 to form an element isolation region 28 (see FIG. 5). As a result, a trench isolation structure is completed. Thereafter, a gate insulating film 51 is formed in the element forming region 29 partitioned by the element isolation region 28, and a source region 52 and a drain region 53 are provided by doping with an n-type impurity, and a gate electrode is formed on the gate insulating film 51. 54 are formed. Then, although not particularly shown, by forming an interconnect, an interlayer insulating film and a passivation film on the surface in the state shown in FIG. 6, an element such as a transistor (not shown) is manufactured.

According to the above embodiment, the first substrate 21
After a polysilicon layer 3 serving as a gettering layer is formed on the surface of the substrate, a silicon dioxide layer 22 is formed on the surface of the substrate, which is bonded to a second substrate 23, and then ground to form a silicon active layer 24. Therefore, the gettering layer 31 can be formed in the silicon active layer 24 of the SOI substrate 2.

Further, according to the above-described embodiment, after the affected layer 4 generated when forming the trench 25 having the trench isolation structure is removed, the trench 25 is filled and the element isolation region 2 is formed.
By forming 8, the contamination of the substrate due to the diffusion of the metal element contained in the altered layer 4 can be prevented.

Therefore, the SOI substrate 2 of the present embodiment
By using this to produce a transistor, the occurrence of punch-through can be avoided. Further, a high withstand voltage element can be formed at a high density. Further, a highly reliable gate oxide film can be stably formed. For example, as a result of verification by the present inventor, the rate of C-mode breakdown in the gate oxide film has been improved from 60% in the prior art to 95%. This value is a normal CZ (Czochralski)
This is equivalent to the rate of C mode breakdown of a gate oxide film formed on a substrate made of a silicon wafer manufactured by the method.

In the above description, the present invention can be similarly applied to an n-type semiconductor substrate, and can also be applied to a semiconductor substrate other than silicon. Further, the polysilicon layer 3, the silicon dioxide layers 22 and 26, and the silicon active layer 24 are not limited to the thickness of the above embodiment, and the temperature of the thermal oxidation treatment is not limited to the above embodiment. Further, the volume ratio of hydrofluoric acid, nitric acid and acetic acid in the acid etching solution is not limited to 1:20:50.

[0028]

As described above, according to the present invention,
After forming a gettering layer on the main surface of the first semiconductor substrate and further forming an insulating layer on the surface of the gettering layer,
The main surface side is bonded to the second semiconductor substrate, and the surface of the first semiconductor substrate is ground to a predetermined thickness to form an element formation region. Therefore, in a semiconductor device having an SOI structure, A gettering layer can be provided in the layer. Therefore, gettering effectively acts on impurities such as metal elements mixed during the manufacturing process, and a highly reliable element can be stably manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a state in one step of a manufacturing process of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing a state in one step of the manufacturing process of the semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view showing a state in one step of the manufacturing process of the semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view showing a state in one step of the manufacturing process of the semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing a state in one step of the manufacturing process of the semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view showing a state in one step of the manufacturing process of the semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view showing a state in one step of a conventional semiconductor device manufacturing process.

FIG. 8 is a cross-sectional view showing a state in one step of a conventional semiconductor device manufacturing process.

FIG. 9 is a cross-sectional view showing a state in one step of a conventional semiconductor device manufacturing process.

FIG. 10 is a cross-sectional view showing a state in one step of a conventional semiconductor device manufacturing process.

FIG. 11 is a cross-sectional view showing a state in one step of a conventional semiconductor device manufacturing process.

[Explanation of symbols]

 Reference Signs List 2 SOI substrate 3,27 polysilicon layer 4 deteriorated layer 21,23 silicon substrate 22,26 silicon dioxide layer 24 silicon active layer 25 groove 28 device isolation region 29 device formation region 31 gettering layer

Claims (5)

[Claims] A first conductive type semiconductor substrate provided with a first conductive type semiconductor substrate;
A first step of forming a gettering layer of the conductive type, a second step of forming an insulating layer on the surface of the gettering layer after forming the gettering layer, and a step of forming the insulating layer on the semiconductor substrate. A third step of bonding the main surface side to another semiconductor substrate of the first conductivity type; and, after bonding the substrates, grinding the surface of the semiconductor substrate on which the gettering layer is formed to a predetermined thickness. And forming a device forming region by exposing the semiconductor region covered with the insulating layer. 2. A fifth step of forming an element isolation groove in the element formation region formed in the fourth step, and exposing the inside of the groove after forming the groove and before performing heat treatment. 2. The semiconductor device according to claim 1, further comprising: a sixth step of removing an altered layer formed on a surface; and a seventh step of filling the trench after removing the altered layer. 3. Manufacturing method. 3. The method according to claim 1, wherein the semiconductor substrate is made of silicon, and the gettering layer is made of polysilicon. 4. The method according to claim 3, wherein, in the sixth step, the altered layer is removed using a mixed solution of hydrofluoric acid, nitric acid, and acetic acid. 5. The method for manufacturing a semiconductor device according to claim 4, wherein in the mixed solution, the ratio of nitric acid to hydrofluoric acid is 20 and the amount of acetic acid is 50 in terms of volume ratio.