JP2001023925A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device, constituted into such a structure that an embedded wiring consisting of a healthy conductor having not a defect can be formed in a microscopic recessed part and the manufacturing method of the device. SOLUTION: In a semiconductor device of a structure, where a wiring is embeddedly formed in a microscopic recessed part 5 provided in the surface of a semiconductor substrate W, wiring is formed in such a way that the wiring is constituted of a plated metal copper film grown in one direction from the bottom of the recessed part 5 toward the end part of an aperture provided in the recessed part 5. Hereby, while the plated metal copper film constituting the wiring grows in the one direction from the bottom of the recessed part 5 toward the aperture provided in the microscopic recessed part 5 and as the growth of the plated metal copper film 7 from the sidewall part of the recessed part 5 is stopped, an embedded wiring consisting of a healthy conductor having no internal defects, such as voids or seams can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which fine wiring recesses formed in a semiconductor substrate are filled with a metal such as copper (Cu) and a method of manufacturing the same. About.

[0002]

2. Description of the Related Art Aluminum or an aluminum alloy is generally used as a metal material for forming a wiring circuit on a semiconductor substrate. In recent years, however, the use of copper has become remarkable. This means that the electrical resistivity of copper is 1.
Since it is 72 μΩcm, which is about 40% lower than the electrical resistivity of aluminum, it is not only advantageous for a signal delay phenomenon, but also has a much higher electromigration resistance of copper than that of current aluminum, and has a dual damascene more than aluminum. This is because the process is easy to adopt, and there is a high possibility that a complicated and fine multilayer wiring structure can be manufactured relatively inexpensively.

Here, there are three methods of embedding a metal such as copper in a wiring groove and a via hole at the same time by a dual damascene method: CVD, sputter reflow, and plating. Among these methods, the plating method has a good tendency to embed into fine recesses and has a strong tendency to enable sound embedding by a relatively easy and inexpensive process. Incorporation into mass production lines is becoming commonplace.

FIG. 3 shows a basic process used for obtaining a semiconductor device in which a copper wiring is formed by plating a surface of a semiconductor substrate with copper. That is, the semiconductor the substrate W, as shown in FIG. 3 (a), an insulating film 2 made of SiO ₂ is deposited on a conductive layer 1a on a semiconductor substrate 1 on which semiconductor devices are formed, lithography etching A fine concave portion 5 composed of a contact hole 3 and a wiring groove 4 is formed by a technique, and a diffusion suppressing (barrier) layer 6 made of TaN or the like is formed thereon.

[0005] Then, as shown in FIG. 3 (b), by plating the surface of the semiconductor substrate W with copper, the recesses 5 of the semiconductor substrate 1 are filled with copper 7 and diffusion is suppressed (barrier). Deposit copper 7 on layer 6. Thereafter, the copper 7 on the diffusion suppression (barrier) layer 6 and the diffusion suppression (barrier) layer 6 are removed by chemical mechanical polishing (CMP), and the copper 7 filled in the contact hole 3 and the wiring groove 4 is removed. And the surface of the insulating film 2 are made substantially flush with each other. Thus, an embedded wiring made of copper 7 is formed as shown in FIG.

Here, when copper 7 is buried in the fine concave portion 5 provided on the surface of the semiconductor substrate W by, for example, electrolytic plating, as shown in FIG. On the surface of the diffusion suppressing layer 6 formed on the semiconductor substrate W, a base film 8 serving as a power supply (seed) layer is widely formed. The main purpose of the base film (power supply layer) 8 is to use the surface of the power supply layer as an electric cathode to reduce metal ions in the liquid and supply a sufficient current to precipitate as metal. In the electroless plating method, a catalyst layer is widely provided as the base film 8 instead of the power supply layer.

[0007]

The base film 8 is generally formed by sputtering, but in the case of film formation by sputtering, as the width of the concave portion 5 becomes narrower and deeper, the entirety of the concave portion 5 becomes larger. It becomes difficult to form the base film 8 covering the surface. For example, when the width _{W 1} of the opening of the recess 5 is 0.25 [mu] m, the limit depth D to form a sound base film 8 on the entire surface of the recess 5, 1.25 .mu.m
It is said that it is about.

For this reason, when the depth exceeds this limit depth, FIG.
As shown in (a), a portion U where the base film 8 is missing or has an incomplete form occurs on a part of the side wall surface of the fine concave portion 5 provided on the surface of the substrate W. Would.
Then, when an electrolytic copper plating operation is performed in this state, the plating metal grows in the same direction from the surface of the base film 8 at a uniform speed.
As a result, the growth of the plating metal from the defective portion U of the base film 8 is suppressed or prevented. As a result, the deposition of the plating film in the U portion depends only on the growth from the adjacent portion in the lateral direction. That is, in this portion, the growth amount within a predetermined time is smaller than the growth of the plating metal from the sound underlying film 8. As a result, as shown in FIG. 4B, voids (cavities) 9 are generated inside the copper 7 embedded in the concave portions 5.

In order to prevent this, as shown in FIG. 5A, when the thickness of the base film 8 is made extremely thicker than usual and the area ratio covered by the base film 8 is greatly increased, The so-called overhang portion O formed at the shoulder of the opening of the recess 5 has a remarkably large overhang. Then, when copper plating is performed in this state, the recess 5
5B, the copper ions supplied to the inside of the recess are depleted during the plating process. Therefore, as shown in FIG.
Often produces 0.

[0010] Since these plating defects, void 9 and seam 10, are both extremely harmful as conductive paths, by eliminating these defects and forming a continuous integrated conductive path, sufficient current capacity can be obtained. It is desired to secure the delay, suppress the signal delay, and improve the electromigration resistance. This is the same when electroless plating is performed using a catalyst layer as a base film instead of the power supply layer in the electrolytic plating.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of forming a buried wiring made of a sound conductor having no defects in fine recesses, and a method of manufacturing the same. And

[0012]

According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device formed by embedding wiring in a fine recess provided on the surface of a semiconductor substrate, the wiring is formed of a plating metal grown in one direction from the bottom of the recess toward the opening end. It is characterized by.

By forming the wiring with a plated metal grown in one direction from the bottom of the fine recess toward the opening end, it is possible to avoid the occurrence of defects such as voids and seams inside the wiring.

According to the method of manufacturing a semiconductor device of the present invention, a diffusion suppressing layer and a base film serving as a power supply layer or a catalyst layer are sequentially formed on a surface of a semiconductor substrate having fine recesses. After a thin film of an insulating substance is formed on the surface except for the surface, plating is performed on the surface of the semiconductor substrate.

As a result, the plating metal grows only from the base film exposed at the bottom of the fine concave portion, and the portion other than the bottom is covered with the thin film of the insulating material, so that the growth of the plating metal from that portion stops. . That is, unlike the usual method, the plating is prevented from growing from the side wall of the concave portion and grows only in one direction from the bottom of the concave portion toward the opening, so that defects such as voids and seams are generated inside the plating. Can be prevented.

Further, the invention is characterized in that the diffusion suppressing layer is a metal nitride, and the underlayer is made of one or more of copper, palladium, and a metal catalyst material. When performing electrolytic plating, the base film is formed of copper or palladium to form a power supply (seed) layer. When performing electroless plating, the base film is formed of a metal catalyst material to form a catalyst layer.

Further, the metal nitride is tantalum nitride. Further, the thin film of the insulating material is characterized by being formed of the same material as the diffusion suppressing layer, another compound, or an insulating elemental element. Further, the plating is copper plating.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. First,
As shown in FIG. 1A, fine recesses 5 for wiring are formed on an insulating film 2 made of SiO ₂ deposited on a semiconductor base material of a semiconductor substrate W by lithography and etching technology. For example, a diffusion suppression (barrier) layer 6 made of tantalum nitride (TaN) or the like is formed. Further, on the surface of the diffusion suppressing layer 6, a base film 8 made of, for example, copper, silver or the like and serving as a power supply (seed) layer is formed. Note that this example shows an example in which electrolytic plating is performed.When performing electroless plating, a catalyst layer made of a metal catalyst material is formed instead of the power supply layer, and this is used as an underlayer. I do. Incidentally, the above-mentioned copper has a function as a catalytic metal together with palladium, platinum and the like.

Then, as shown in FIG. 1B, a thin film 11 of an insulating material is formed only on the surface of the base film 8 excluding the bottom of the recess 5. That is, the underlying film 8 is exposed to the outside only at the bottom of the concave portion 5, and otherwise the underlying film 8 is exposed.
Is covered with a thin film 11 of an insulating material.

In this state, an electrolytic plating solution flows into the recess 5 and an electric field is applied to perform electrolytic copper plating on the surface of the semiconductor substrate W. Then, since power supply is limited to the bottom surface of the deepest portion of the concave portion 5, as shown in FIG. 1C, the deposition of copper 7 by plating proceeds in a state substantially parallel to the bottom surface of the concave portion 5, and Is filled with copper 7. That is, the buried growth of the copper 7 by plating occurs only in one direction from the bottom of the recess 5 to the opening. As described above, the embedding of the copper 7 is completed sequentially from the deepest portion of the concave portion 5 and the growth from the side wall portion toward the center of the concave portion 5 is completely prevented, so that the wiring is formed by being embedded in the fine concave portion 5. It is possible to completely prevent defects such as voids and seals from being generated inside the copper 7.

As the material of the insulating material forming the thin film 11, a ceramic or an intermetallic compound having a low bulk conductivity and a high diffusion suppressing property and adhesion to copper is suitable. Tantalum nitride of the same material as the diffusion suppressing layer 6 may be applied.

Then, by chemical mechanical polishing (CMP),
By removing the copper 7 on the insulating film 2 and making the surface of the copper 7 filled in the concave portion 5 and the surface of the insulating film 2 almost coplanar, the copper 7 is formed as shown in FIG. Form wiring.

FIG. 2 shows an example in which a thin film 11 of an insulating material is formed only on the surface of the base film 8 excluding the bottom of the recess 5. First, as shown in FIG. 2A, a thin film 11 of an insulating material is formed on the surface of the base film 8 by sputtering. Next, as shown in FIG. 2B, the thin film 11 deposited on the bottom surface of the recess 5 is removed by performing sputter etching using Ar ions with the substrate side as a target.

Various methods can be considered for removing the thin film 11 deposited on the bottom surface of the concave portion 5. Since the material of the thin film (insulating layer) 11 generally has little chemical reactivity with a halogen-based gas used in a semiconductor process, it is desirable to mainly carry out etching by physical sputtering. Therefore, this example employs sputter etching using an inert gas with the substrate side as a target.

Strictly, it depends on the equipment used, the operating conditions, the material of the target thin film 11 and the like, but the sputter etching speed by Ar ions is at least 30 to 60.
It is considered to be about Å / min.

Here, since Ar ions have a strong tendency to be incident perpendicular to the substrate surface, A
The probability of collision with r ions is much higher than the probability for the side wall surface (selective etching). In other words, A
By irradiating with r ions, only the thin film 11 on the bottom surface of the concave portion 5 can be selectively removed. Therefore, if the thickness of the thin film 11 deposited on the bottom surface is about 5 nm, the required sputter etching time is within about 1 min.

The thickness of the thin film 11 covering the side wall surface is preferably thinner from the viewpoint of minimizing the reduction of the cross-sectional area of the conductive line, but on the other hand, it is necessary to secure a certain electric insulation. Thicker is more convenient. Therefore, it is considered that a practical film thickness of the thin film 11 of about 5 nm (as an average value guide) is suitable.

Some of the atoms or molecules constituting the thin film sputtered into the air and sputtered by Ar ions are discharged to the vacuum pump side, and the rest is reattached to the surrounding side wall surface, substrate surface, or the like. However, since the amount of redeposition itself is very small, the adverse effect due to it is negligible.

[0029]

As described above, according to the present invention,
The plating metal forming the wiring grows in the fine recess in one direction from the bottom of the recess toward the opening, while the growth of the plating metal from the side wall of the recess is prevented. Buried wiring made of a sound conductor without internal defects can be formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing an example of forming a thin film of an insulating material on the surface of the underlayer except for the bottom of the concave portion in the order of steps.

FIG. 3 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device in the order of steps.

FIG. 4 is a cross-sectional view for explaining generation of voids in a conventional method for manufacturing a semiconductor device.

FIG. 5 is a cross-sectional view for explaining generation of a seam in a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 2 Insulating film 5 Depression 6 Diffusion suppressing layer 7 Copper 8 Base film 11 Thin film W Semiconductor substrate

Claims (6)

[Claims] 1. A semiconductor device formed by embedding a wiring in a fine recess provided on a surface of a semiconductor substrate, wherein the wiring is a plated metal grown in one direction from a bottom of the recess toward an opening end. A semiconductor device characterized by comprising: 2. A diffusion suppressing layer and a base film serving as a power supply layer or a catalyst layer are sequentially formed on a surface of a semiconductor substrate having fine recesses, and a thin film of an insulating material is formed on a surface of the base film excluding the bottom of the recesses. Forming a semiconductor substrate, and then plating the surface of the semiconductor substrate. 3. The method according to claim 2, wherein the diffusion suppressing layer is made of a metal nitride, and the base film is made of one or more of copper, palladium, and a metal catalyst material. Of manufacturing a semiconductor device. 4. The method according to claim 3, wherein the metal nitride is tantalum nitride. 5. The semiconductor device according to claim 2, wherein the thin film of the insulating material is made of the same material as the diffusion suppressing layer, another compound, or an insulating single element. Manufacturing method. 6. The method according to claim 2, wherein said plating is copper plating.