JP2001077198A - Array substrate without short circuit between top wiring and bottom wiring and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent lowering of a manufacturing yield and production efficiency due to short-circuiting between a scanning line and a signal line which overlaps with the scanning line in an array substrate for a flat-panel display device, and to provide its manufacture. SOLUTION: If a layer short 21 is detected in inspection of an array substrate 10, nearly U-shaped bypass wiring 5 for sandwiching a part 3a in the vicinity of the layer short 21 from both sides and mutually inking left and right signal line parts 3b, 3c is formed by the local deposition of a metal that uses laser CVD(chemical vapor deposition). On this occasion, a contact hole 41 that penetrates into a coated insulating film 4 for conductively connecting the signal lines 3b, 3c and the bias wiring 5 is previously provided by laser irradiation. After the bypass wiring 5 is formed, an open circuit portion 31 is provided by the laser irradiation so that the part 3a in the vicinity of the layer short 21 can be isolated from the signal lines 3b, 3c on both sides.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate (thin film wiring substrate) used for a flat display device represented by a liquid crystal display device and a method for manufacturing the same. In particular, the present invention relates to an array substrate that corrects a short circuit generated at an intersection between upper and lower wirings and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, flat display devices such as liquid crystal display devices have been used as display devices such as personal computers, word processors or TVs, and as projection display devices, taking advantage of the features of thinness, light weight, and low power consumption. It is used in various fields.

Among them, an active matrix type display device in which a switch element is electrically connected to each pixel electrode is capable of realizing a good display image without crosstalk between adjacent pixels. Have been done.

[0004] The structure of the active matrix type liquid crystal display device of the light transmission type will be briefly described below.

Generally, in an active matrix type liquid crystal display device, a matrix array substrate (hereinafter, referred to as an array substrate) and an opposing substrate are arranged close to each other at a predetermined interval, and are provided on the surface layer of both substrates during this interval. The liquid crystal layer is held via the aligned alignment film.

In the array substrate, for example, a plurality of signal lines as an upper metal wiring pattern and a plurality of scanning lines as a lower metal wiring pattern are formed on a transparent insulating substrate such as glass via an insulating film. ITO (Indium-Tin-Oxid) is arranged in a grid, and in an area corresponding to each square of the grid.
A pixel electrode made of a transparent conductive material such as e) is provided. At each intersection of the grid, a switching element for controlling each pixel electrode is arranged. When the switching element is a thin film transistor (hereinafter abbreviated as TFT), the gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is electrically connected to the pixel electrode. It is connected to the.

[0007] The opposing substrate is formed by disposing an opposing electrode made of ITO or the like on a transparent insulating substrate such as glass, and a color filter layer for realizing color display.

However, in the process of manufacturing an array substrate as described above, when an upper wiring pattern and a lower wiring pattern intersect or overlap with each other, a defect of an insulating film or a non-insulating foreign substance between them may occur. Due to the presence, interlayer short circuit (short circuit or interlayer leak) between upper and lower wiring patterns
Sometimes occurred.

When such an interlayer short-circuit occurs, the image display performance is significantly impaired. Therefore, by thoroughly controlling the manufacturing process in order to suppress the occurrence of such an interlayer short-circuit, it has been attempted to reduce foreign substances and reduce defects in the insulating film and the metal film.

[0010]

However, the occurrence of interlayer short circuit at a certain rate is still unavoidable.
An array substrate in which an interlayer short was found in the inspection process was discarded as a defective product. The disposal cost increases the manufacturing cost of the array substrate and reduces the production efficiency.

Particularly, in the case of an array substrate used for a large-sized and high-definition flat panel display device, the influence on the production yield due to occurrence of interlayer short-circuit has been a serious problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide an array substrate used for a flat panel display device or the like and a method of manufacturing the same to prevent a reduction in production yield and production efficiency due to occurrence of interlayer short-circuit. Provide what you can.

[0013]

According to a first aspect of the present invention, there is provided an array substrate for a flat panel display device including a three-dimensional intersection where an upper layer wiring and a lower layer wiring cross three-dimensionally via an insulating film. In the above-mentioned three-dimensional intersection part, the upper surface of one wiring including the interlayer short-circuit part which causes a short circuit between upper and lower wiring due to a defect of the insulating film, A pair of contact holes that are exposed at locations sandwiching them from both sides, and a bypass wiring that is electrically connected to the one wiring through each of the pair of contact holes and that is arranged to avoid the interlayer short-circuit portion. In a region interposed between the pair of contact holes, a pair of disconnection portions separating the interlayer short-circuit portion from the one wiring is included.

With the above configuration, it is possible to prevent a decrease in manufacturing yield and production efficiency due to occurrence of interlayer short-circuit.

According to a second aspect of the present invention, there is provided a method for manufacturing an array substrate for a flat panel display device, wherein the upper layer wiring and the lower layer wiring include an intersecting three-dimensional difference portion intersecting three-dimensionally via an insulating film. A detecting step of detecting an interlayer short-circuit portion in which a short circuit occurs between upper and lower wires due to a defect in the insulating film, and detecting an upper surface of one wire including the interlayer short-circuit portion; A step of providing a pair of contact holes by laser irradiation so as to expose the interlayer short-circuit portion at a position sandwiching from both sides, and electrically connected to the one wiring through each of the pair of contact holes,
A step of locally depositing a conductive layer by laser CVD so as to form a bypass wiring disposed avoiding the interlayer short-circuit portion, and forming the interlayer short-circuit portion in a region sandwiched between the pair of contact holes. By laser irradiation, so as to form a pair of disconnected parts separated from one wiring
Removing the one wiring locally.

According to a third aspect of the present invention, in the laser CVD, the energy level of the laser beam is adjusted so that the wiring layer has a wiring width of 1.0 to 10 μm and a film thickness of 1 μm or less. Is deposited, and at the time of laser irradiation for providing the pair of contact holes, only the covering insulating film covering the upper wiring is removed without damaging the metal film forming the upper wiring. It is possible to use a laser beam of an energy level capable of performing the laser irradiation for providing the pair of disconnection portions, and to perform a laser beam of an energy level suitable for removing the upper layer wiring together with the covering insulating film. Is used.

According to the above configuration, a normally operating array substrate can be easily and reliably obtained from the array substrate in which an interlayer short circuit has occurred.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An array substrate according to an embodiment and a method of manufacturing the same will be described with reference to FIGS.

FIG. 1 is a schematic cross-sectional perspective view showing a main part of an array substrate 10. That is, with respect to the interlayer short-circuit generated at the three-dimensional intersection 6 where the signal line 3 straddles the scanning line 1,
This shows a state corrected by providing a substantially U-shaped bypass wiring 5 and a disconnection portion 31.

In the array substrate 10 of the embodiment, a plurality of scanning lines 1 (gate electrode lines) and a plurality of signal lines 3 (drain electrode lines) are arranged on a glass substrate 15 so as to be orthogonal to each other.

The lower metal wiring pattern including the scanning line 1 is formed of, for example, molybdenum-tungsten (Mo-W), and is entirely covered with the gate insulating film 2. The gate insulating film 2 is composed of, for example, a stacked film of a silicon oxide film and a silicon nitride film.

The upper metal wiring pattern including the signal line 3 disposed on the gate insulating film 2 is formed of, for example, a three-layer film of molybdenum-aluminum-molybdenum (Mo / Al / Mo). It is covered with a covering insulating film 4 made of a silicon nitride film.

At a three-dimensional intersection 6 where the signal line 3 straddles the scanning line 1 below, at least the gate insulating film 2 is arranged between the upper and lower wirings 1 and 3. However, a defect such as a pinhole may occur in the gate insulating film 2, and if such a defect occurs in the three-dimensional intersection 6, an interlayer short circuit occurs between the signal line 3 and the scanning line 1. Become.

In the approximate center of FIG.
1 shows a state in which a portion of the signal line 1 near the three-dimensional intersection 6 and the scanning line 1 are electrically connected.

FIG. 1 also shows a state in which disconnection portions 31 are provided by laser cutting on the left and right of the three-dimensional intersection 6 where the interlayer short-circuit has occurred. That is, the signal line 3
, A wiring portion (short-circuit portion) 3 short-circuited to the scanning line 1
a is separated from the other wiring portions (left and right signal line portions) 3b and 3c of the signal line 3 by the disconnection portions 31 on both sides thereof. In other words, one signal line 3 having the interlayer short-circuit portion 21 is formed by a pair of disconnection portions 31 so that a short-circuit portion 3a which is in the vicinity of the interlayer short-circuit portion 21 and is electrically connected to the scanning line 1 and the left and right portions sandwiching the short portion 3a from both sides Signal line portion 3b,
3c. Thus, the left and right signal line portions 3b and 3c are non-conductive to the scanning line 1.

FIG. 1 further shows left and right signal line portions 3.
The bypass wiring 5 for electrically connecting b and 3c to each other is shown. The bypass wiring 5 has a substantially U-shape in plan view, and is disposed on a covering insulating film that covers the signal line 3.
It is electrically connected to the left and right signal line portions 3b and 3c via the contact holes 41 penetrating the coating insulating film 4.

More specifically, a pair of contacts for exposing the upper surfaces of the left and right signal line portions 3b and 3c are provided at positions adjacent to the disconnection portion 31 in the left and right signal line portions 3b and 3c sandwiching the short-circuit portion 3a. A hole 41 is provided. The bypass wiring 5 extends from a portion covering one contact hole 41 to a portion covering the other contact hole 41 while bypassing the laser cut portion 31 and the gate short-circuit portion 3a.

Although not shown, a TFT as a switching element is disposed near the three-dimensional intersection 6 between the scanning line 1 and the signal line 3. The TFT is an inverted stagger type in which a part of the scanning line 1 is used as a gate electrode and a part of the signal line 3 is used as a drain electrode. The source electrode of the TFT is a pixel electrode 4 arranged for each opening defined by the scanning line 1 and the signal line 3.
5 (ITO electrode).

The TFT has, for example, an amorphous silicon (a-Si: H) layer as a semiconductor active layer, and, as an ohmic contact layer between the semiconductor active layer and source and drain electrodes, for example, phosphorus-doped amorphous silicon (n-Si: H).
⁺ a-Si: H) layer. When a manufacturing method in which the semiconductor active layer and the ohmic contact layer are patterned together with the signal line 3 is adopted, these semiconductor layers always exist below the signal line 3.

Next, a specific example of a method of manufacturing an array substrate according to the embodiment, that is, a method of repairing (correcting) an array substrate having an interlayer short-circuit will be described with reference to the process conceptual diagram of FIG.

(A) Detection of Interlayer Short Location First, an array substrate that has been subjected to a plurality of film formation and photoetching steps is subjected to an inspection step. For example, a plurality of probes are connected to connection pads on the periphery of the array substrate,
Inspections are performed for interlayer short-circuits, TFT operation failures, and the like. By this inspection step, the array substrate 10 having the interlayer short-circuit portion 21 is determined, and the position of the interlayer short-circuit portion 21 is specified.

(B) Formation of Contact Hole 41 by Laser Irradiation Next, at two places on the signal line 3 sandwiching the interlayer short-circuiting part 21, a covering insulation is formed so as to expose a part of the upper surface of the signal line 3. A contact hole 41 penetrating through the film 4 is formed. At this time, laser evaporation process (Zapping
Method), the coating insulating film 4 at a predetermined location is removed. That is, a pair of contact holes 4 are cut by laser cutting.
1 is formed.

(C) Formation of bypass wiring 5 by laser CVD The bypass wiring 5 is formed by local deposition of tungsten (W) using laser CVD. The bypass wiring 5 is arranged so as to extend from one of the pair of contact holes 41 sandwiching the interlayer short portion 21 to the other, bypassing the interlayer short portion 21 so as to avoid the interlayer short portion 21.

In this laser CVD, a tungsten-containing carbonyl compound such as WC (C
O) ₆ and argon gas (A) as a carrier gas.
r) was used.

In this embodiment, the reason why the tungsten-containing carbonyl compound is used is that the decomposition / deposition efficiency by laser light is high and the film formation stability is excellent. However, other source gases, such as chromium carbonyl, may optionally be used. Therefore, the bypass wiring 5 can be formed of chromium (Cr) or another metal.

On the other hand, the carrier gas is preferably an inert argon gas, but a nitrogen gas or the like can also be used.

(D) Separation of the Interlayer Short Location 21 by Laser Irradiation Finally, by providing a pair of disconnection portions 31 in the signal line 3, a portion (short portion) 3a near the interlayer short location 21 is formed.
And the other signal line portions 3b and 3c. Specifically, a metal film forming the signal line 3 and a coating insulation covering the metal film at an appropriate point between the three-dimensional intersection 6 including the interlayer short part 21 and the contact hole 41 by a laser evaporation method (Zapping method). The film 4 is removed, and the disconnection part 31 is formed.

Since the disconnection portion 31 is arranged so as not to overlap at least the area of the scanning line 1 and the bypass, the scanning line 1 and the bypass wiring 5 are not damaged when the disconnection portion 31 is formed.

In a series of steps for repairing (defect correction) of the array substrate as described above, at the time of laser CVD for forming the bypass wiring 5, the energy level of the laser beam is adjusted to reduce the wiring width. For example, 1.0 to 10μ
A wiring layer having a thickness of, for example, 1.0 μm or less was deposited. In addition, at the time of laser irradiation for providing the contact hole 41, a laser having an energy level capable of removing only the covering insulating film 4 covering the signal line 3 without damaging the underlying metal film forming the signal line 3. In the case of laser irradiation using light to provide the disconnection portion 31, the coating insulating film 4
At the same time, the metal film of the underlying signal line 3 (for example, Mo / Al
/ Mo) was used with a laser beam at an energy level suitable for removal.

The specific examples of the manufacturing conditions are as follows.

The same Nd ⁺³ : YAG laser device was used for laser irradiation for forming the contact hole 41, laser CVD, and laser irradiation for forming the disconnection portion 31. The metal film forming the signal line 3 is Mo /
It is a three-layer metal film of Al / Mo, and the covering insulating film 4 is an oxygen-containing silicon nitride film (SiNxOy).

At the time of laser CVD, it is a continuous oscillation laser beam having an energy level of 700 mW (10
kHz), and a wiring layer having a wiring width of about 5 μm and a film thickness of about 0.3 μm was deposited. Also,
In the case of laser irradiation for providing the contact hole 41,
A laser beam that is modulated by an ultrasonic Q-switch element and oscillates in a pulse shape, and has an energy level of 1 mJ
(2 Hz). Further, at the time of laser irradiation for providing the disconnection part 31, the laser light is a pulsed laser light having a similar energy level of 1 mJ.
(2 Hz) was used.

As a laser light source, it is preferable to use a YAG laser as in the above specific example, since an energy level in the above range can be easily obtained. However, it is also possible to use carbon dioxide lasers and other lasers.

As in the above example, the contact hole 4
1, the formation of the bypass wiring 5, and the formation of the disconnection portion 31 using the same laser device,
The apparatus load for repairing the array substrate can be reduced. In addition, by setting the energy level of the laser beam as described above, each of the above steps can be performed efficiently and reliably.

According to the embodiment described above, a normally operating array substrate can be obtained from a defective array substrate in which an interlayer short circuit has been detected, so that the product yield of the array substrate can be improved.

In addition, since repair can be reliably performed with almost minimum process load and device load, the manufacturing efficiency of the array substrate can be improved and the manufacturing cost of the array substrate can be reduced as a whole. Also, the process and cost burden for discarding defective products can be reduced.

In the above embodiment, one contact hole 41 is provided in each of the signal line portions 3b and 3c sandwiching the short-circuit portion 3a. However, in order to further secure the electrical connection, A plurality of contact holes may be provided.

[0048]

According to the present invention, in an array substrate used for a flat panel display device or the like and a method of manufacturing the same, it is possible to prevent a decrease in manufacturing yield and production efficiency due to occurrence of interlayer short-circuit.

[Brief description of the drawings]

FIG. 1 is a sectional perspective view schematically showing a main part of an array substrate according to an embodiment.

FIG. 2 is a process conceptual diagram for describing a method of repairing an array substrate according to an embodiment. (A)
It is a top view which shows the mode of the detected interlayer short-circuit part. (B) is a plan view corresponding to (a), showing a state in which a contact hole is formed. (C) is a plan view corresponding to (a), showing a state in which a bypass wiring is formed. (D) is a plan view corresponding to (a), showing a state in which a disconnection portion for separating an interlayer short-circuit portion is formed.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Scanning line 10 Array substrate 2 Gate insulating film 21 Interlayer short-circuit part 3 Signal line 3a Short-circuit part of a signal line electrically connected with a gate electrode 3b, 3c Parts other than short-circuit part of a signal line 31 Disconnection of a signal line by laser cutting Part 4 Covering insulating film covering signal line 41 Contact hole penetrating the covering insulating film 45 Pixel electrode (ITO electrode) 5 Bypass wiring (tungsten wiring) by laser CVD 6 Three-dimensional intersection where signal line and scanning line overlap

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/3205 H05K 1/11 A 5F064 H05K 1/11 H01L 21/88 Z F term (Reference) 2H092 GA29 JA46 JB22 JB31 KA05 KA10 MA07 MA30 NA16 NA29 NA30 4M104 BB02 BB16 CC01 DD03 DD06 DD99 FF17 GG09 HH20 5C094 AA42 AA43 BA03 BA43 CA19 DA15 EA03 EA04 EA07 EA10 GB01 HA08 5E317 AA11 AA24 BB01 BB16 BB17 GG17 GG17 BB18 RR04 RR06 VV15 XX36 5F064 DD26 EE22 EE26 EE27 EE57 FF04 FF42

Claims (4)

[Claims] 1. An array substrate for a flat panel display device including a three-dimensional intersection where an upper layer wiring and a lower layer wiring three-dimensionally intersect via an insulating film. A pair of contact holes for exposing the upper surface of one wiring including the interlayer short-circuit portion at a location sandwiching the interlayer short-circuit portion from both sides, A bypass wiring that is electrically connected to the one wiring through each of the pair of contact holes and that is arranged to avoid the interlayer short-circuit portion; An array substrate, comprising: a pair of disconnection portions for separating a short-circuit portion from the one wiring. 2. A method of manufacturing an array substrate for a flat panel display device, comprising a three-dimensional intersection part in which an upper wiring and a lower wiring intersect three-dimensionally via an insulating film. A detection step of detecting an interlayer short-circuit portion causing a short circuit between upper and lower wiring due to a defect in the insulating film; and exposing an upper surface of one wiring including the interlayer short-circuit portion at a position sandwiching the interlayer short-circuit portion from both sides. Providing a pair of contact holes by laser irradiation, and a bypass line electrically connected to the one line via each of the pair of contact holes and arranged to avoid the interlayer short-circuit portion. Laser CV to form
D. a step of locally depositing a conductive layer by D, in a region sandwiched by the pair of contact holes, by laser irradiation so as to form a pair of disconnection portions separating the interlayer short-circuit portion from the one wiring. And locally removing the one wiring. 3. The method according to claim 1, wherein the laser beam energy level is adjusted during the laser CVD so that the wiring width is 1.0 to 10 mm.
μm, so that a wiring layer having a thickness of 1 μm or less is deposited, and at the time of laser irradiation for providing the pair of contact holes, the metal film forming the upper wiring is not damaged, and Using laser light of an energy level capable of removing only the coating insulating film that covers the wiring, and removing the upper wiring together with the coating insulating film at the time of laser irradiation for providing the pair of disconnection portions. 3. The method for manufacturing an array substrate according to claim 2, wherein a laser beam having an energy level suitable for the laser beam is used. 4. The method according to claim 2, wherein in the laser CVD, a tungsten-containing carbonyl compound is used as a source gas and an argon gas is used as a carrier gas.