JP2001077160A - Tester for semiconductor substrate - Google Patents
Tester for semiconductor substrateInfo
- Publication number
- JP2001077160A JP2001077160A JP24890599A JP24890599A JP2001077160A JP 2001077160 A JP2001077160 A JP 2001077160A JP 24890599 A JP24890599 A JP 24890599A JP 24890599 A JP24890599 A JP 24890599A JP 2001077160 A JP2001077160 A JP 2001077160A
- Authority
- JP
- Japan
- Prior art keywords
- contact
- semiconductor substrate
- needle
- test
- probe card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
- G01R31/3191—Calibration
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2882—Testing timing characteristics
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
- G01R31/318511—Wafer Test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体集積回路素
子などが造り込まれた半導体基板(以下、代表的にウェ
ハと称する。)をテストするための半導体基板試験装置
に関し、特にテスタ本体から送出されるテスト信号の波
形を高精度で測定できる半導体基板試験装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate test apparatus for testing a semiconductor substrate (hereinafter, typically referred to as a wafer) on which semiconductor integrated circuit elements and the like are built, and more particularly, to a semiconductor substrate test apparatus which is sent from a tester body. The present invention relates to a semiconductor substrate test apparatus capable of measuring a waveform of a test signal to be measured with high accuracy.
【0002】[0002]
【従来の技術】半導体集積回路素子は、シリコンウェハ
やガラスプレートなどの基板に多数個造り込まれたの
ち、ダイシング、ワイヤボンディングおよびパッケージ
ングなどの諸工程を経て電子部品として完成する。この
ようなICデバイスは、出荷前に動作テストが行われる
が、こうしたテストは、完成品の状態でもウェハ状態で
も行われる。2. Description of the Related Art After a large number of semiconductor integrated circuit elements are formed on a substrate such as a silicon wafer or a glass plate, they are completed as electronic components through various processes such as dicing, wire bonding and packaging. An operation test is performed on such an IC device before shipment, and such a test is performed both in a finished product state and in a wafer state.
【0003】特に近年においては、半導体製造技術の進
展にともなって、ボールグリッドアレイ(BGA:Ball
Grid Aray)型ICデバイスのようなチップサイズパッ
ケージ(CSP:Chip Size Package)を採用したデバイ
スが広く普及しており、この種のICデバイスでは、ウ
ェハの状態でパッケージングを行い、その後にダイシン
グが行われる。したがって、デバイスの動作テストをウ
ェハ状態で行うことが少なくない。In recent years, in particular, with the development of semiconductor manufacturing technology, a ball grid array (BGA: Ball
Devices employing a chip size package (CSP), such as a Grid Aray type IC device, have become widespread. In this type of IC device, packaging is performed in a wafer state, and then dicing is performed. Done. Therefore, the operation test of the device is often performed in a wafer state.
【0004】ウェハ状態のICデバイスをテストする半
導体基板試験装置としては、たとえば実開平5−154
31号公報に開示されたものが知られている。この種の
半導体基板試験装置では、ウェハチャックに被試験物で
あるウェハを真空吸着し、プローブカードに設けられた
ニードル(針状接点)をウェハに造り込まれた接点に接
触させることで試験が行われる。As a semiconductor substrate testing apparatus for testing an IC device in a wafer state, for example, Japanese Utility Model Application Laid-Open No. 5-154
One disclosed in Japanese Patent Publication No. 31 is known. In this type of semiconductor substrate testing device, the test is performed by vacuum-absorbing a wafer to be tested on a wafer chuck and bringing a needle (needle-shaped contact) provided on a probe card into contact with a contact formed on the wafer. Done.
【0005】[0005]
【発明が解決しようとする課題】ところで、ICデバイ
スの動作テストにあたっては、テスタ本体からテストヘ
ッドを介してICデバイスの各接点に1種またはそれ以
上の所定のテスト信号が送出される。たとえば、図4に
示すようなテスト信号aとテスト信号bが送出される。
このような異種のテスト信号a,bの位相がずれている
と、高いクロック周波数でのデバイス試験ができなくな
るので、実際のテストを行う前に同図に示すようなテス
ト信号の波形を観測し、これにより両テスト信号の位相
補正を行うのが一般的である。In the operation test of an IC device, one or more predetermined test signals are transmitted from the tester body to each contact of the IC device via a test head. For example, a test signal a and a test signal b as shown in FIG. 4 are transmitted.
If the different test signals a and b are out of phase, the device test cannot be performed at a high clock frequency. Therefore, the waveform of the test signal shown in FIG. In general, the phase of both test signals is corrected.
【0006】ハンドラと称される、完成品であるICデ
バイスを試験対象とする試験装置において、一般的な位
相補正は、テストヘッドのコンタクトピンに波形観測用
のオシロスコープを接続することにより行われるが、テ
ストヘッドのコンタクトピンと接地点(アース,GN
D)とが離れすぎると、オシロスコープに出力される波
形にノイズ等が混入し、正確な波形を得ることができな
い。たとえば、図5に示すように正規の波形xに対し
て、波形yや波形zのような波形が観測される。このた
め、コンタクトピンの近傍に接地点があればそれが用い
られ、近くに接地点がないときは別途接地パッドを設け
たりしていた。In a test apparatus called a handler, which tests a completed IC device, general phase correction is performed by connecting an oscilloscope for observing a waveform to a contact pin of a test head. , Test head contact pin and ground point (earth, GN
If D) is too far away, noise or the like is mixed in the waveform output to the oscilloscope, and an accurate waveform cannot be obtained. For example, as shown in FIG. 5, a waveform such as a waveform y and a waveform z is observed for a normal waveform x. For this reason, if there is a ground point near the contact pin, it is used, and if there is no ground point nearby, a separate ground pad is provided.
【0007】しかしながら、ウェハを試験対象とする半
導体基板試験装置では、ハンドラのコンタクトピンに相
当するニードルが、150μmといった狭い間隔で並ん
でいるため、ニードルの近傍に接地点を設けることはき
わめて困難であった。However, in a semiconductor substrate testing apparatus for testing a wafer, the needles corresponding to the contact pins of the handler are arranged at a narrow interval of 150 μm, so that it is extremely difficult to provide a ground point near the needle. there were.
【0008】このため、比較的広間隔で配置されたプロ
ーブカードの配線パターン部を用いるなどして、テスト
信号の波形を観測していたが、この方法ではウェハのデ
バイスの接点に入力されるテスト信号そのものを観測し
ている訳ではく、そこから離れた接点を入力部としてテ
スト信号の波形を計測しているので、得られる波形の正
確性に問題があった。For this reason, the waveform of the test signal has been observed by using the wiring pattern portions of the probe card arranged at relatively wide intervals, but in this method, the test signal inputted to the contact of the device on the wafer is used. Since the waveform of the test signal is measured by using a contact far from the input as an input unit instead of observing the signal itself, there is a problem in the accuracy of the obtained waveform.
【0009】[0009]
【課題を解決するための手段】本発明は、テスタ本体か
ら送出されるテスト信号の波形等の信号特性を高精度で
測定できる半導体基板試験装置を提供することを目的と
する。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor substrate testing apparatus capable of measuring a signal characteristic such as a waveform of a test signal sent from a tester main body with high accuracy.
【0010】(1)本発明の第1の観点によれば、半導
体基板に形成されたデバイス部に複数のテスト信号を送
出してテストを行い、その結果に応じて前記デバイス部
の良否を判別する半導体基板試験装置であって、前記デ
バイス部に電気的に接触する複数の第1針状接点と、こ
の第1針状接点の近傍に設けられた接地部とが一主面に
設けられ、テストヘッド基板に電気的に接続されるプロ
ーブカードと、前記第1針状接点に電気的に接触する接
触部と、前記接地部に電気的に接触する第2針状接点と
が一主面に設けられた測定用チップと、を備えた半導体
基板試験装置が提供される。(1) According to a first aspect of the present invention, a test is performed by sending a plurality of test signals to a device section formed on a semiconductor substrate, and the pass / fail of the device section is determined according to the result. A plurality of first needle-shaped contacts that are in electrical contact with the device portion, and a ground portion provided near the first needle-shaped contacts is provided on one main surface, A probe card electrically connected to the test head substrate, a contact portion electrically contacting the first needle contact, and a second needle contact electrically contacting the ground portion are provided on one main surface. A semiconductor substrate test apparatus including the provided measurement chip is provided.
【0011】本発明において、前記測定用チップは、前
記プローブカードの前記第1針状接点および接地部の配
列に応じて、一又はそれ以上の対をなす第2針状接点お
よび接触部を有することがより好ましい。In the present invention, the measuring chip has one or more pairs of second needle-like contacts and contact portions according to the arrangement of the first needle-like contacts and ground portions of the probe card. Is more preferable.
【0012】また本発明において、前記測定用チップを
前記プローブカードの第1針状接点および接地部に対し
て移動させる測定用チップステージをさらに備えること
がより好ましい。Further, in the present invention, it is more preferable that the apparatus further comprises a measuring chip stage for moving the measuring chip with respect to the first needle-like contact and the ground portion of the probe card.
【0013】さらに本発明において、前記半導体基板を
保持して前記プローブカードの第1針状接点に前記デバ
イス部を接触させる基板ステージをさらに備え、前記測
定用チップが前記基板ステージに設けられていることが
より好ましい。Further, according to the present invention, there is further provided a substrate stage for holding the semiconductor substrate and bringing the device portion into contact with a first needle contact of the probe card, and the measuring chip is provided on the substrate stage. Is more preferable.
【0014】本発明において、前記測定用チップの出力
端子に接続され、前記テスト信号の特性を出力する信号
特性測定装置をさらに備えることもできる。In the present invention, the apparatus may further include a signal characteristic measuring device connected to an output terminal of the measuring chip and outputting a characteristic of the test signal.
【0015】本発明における前記テスト信号の特性は、
特に限定はされないが、たとえばテスト信号の信号波形
を挙げることができる。The characteristics of the test signal in the present invention are as follows:
Although not particularly limited, for example, a signal waveform of a test signal can be given.
【0016】(2)本発明の第2の観点によれば、半導
体基板試験装置のテストヘッド基板に電気的に接続さ
れ、半導体基板のデバイス部に電気的に接触する複数の
針状接点が一主面に設けられた半導体基板試験装置用プ
ローブカードであって、前記針状接点の近傍に接地部が
設けられている半導体基板試験装置用プローブカードが
提供される。(2) According to a second aspect of the present invention, a plurality of needle-like contacts electrically connected to a test head substrate of a semiconductor substrate testing apparatus and electrically contacting device portions of the semiconductor substrate are provided. A probe card for a semiconductor substrate testing device provided on a main surface, wherein a grounding portion is provided near the needle contact.
【0017】本発明において、前記接地部は、一つの針
状接点に対して一つの接地部を設けても、あるいは複数
の針状接点に共通して設けることも可能である。In the present invention, the grounding portion may be provided with one grounding portion for one needle-like contact, or may be provided in common with a plurality of needle-like contacts.
【0018】(3)本発明の第3の観点によれば、半導
体基板試験装置用プローブカードに設けられた第1針状
接点に電気的に接触する接地部と、前記第1針状接点の
近傍に設けられた接地部に電気的に接触する第2針状接
点とを備えた半導体基板試験装置の測定用チップが提供
される。(3) According to a third aspect of the present invention, a grounding portion for electrically contacting a first needle-like contact provided on a probe card for a semiconductor substrate testing device, A measurement chip for a semiconductor substrate test apparatus, comprising: a second needle contact that is in electrical contact with a ground portion provided in the vicinity.
【0019】(4)本発明の第4の観点によれば、半導
体基板に形成されたデバイス部に複数のテスト信号を送
出してテストを行い、その結果に応じて前記デバイス部
の良否を判別する半導体基板試験装置の、前記テスト信
号の特性を測定する方法であって、前記半導体基板試験
装置の前記デバイス部に接する部分の少なくとも近傍を
接点として、前記テスト信号の特性を測定する半導体基
板試験装置におけるテスト信号特性の測定方法が提供さ
れる。(4) According to a fourth aspect of the present invention, a plurality of test signals are sent to a device section formed on a semiconductor substrate to perform a test, and the pass / fail of the device section is determined according to the result. A method for measuring characteristics of the test signal, wherein the semiconductor substrate test device measures characteristics of the test signal by using at least a portion near a portion of the semiconductor substrate test device that contacts the device section as a contact point. A method for measuring test signal characteristics in an apparatus is provided.
【0020】本発明において、前記テスト信号の特性
は、特に限定はされないが、たとえばテスト信号の信号
波形を挙げることができる。In the present invention, the characteristics of the test signal are not particularly limited, and examples thereof include a signal waveform of the test signal.
【0021】本発明において、前記半導体基板試験装置
は前記デバイス部にテスト信号を送信する針状接点と、
前記針状接点の近傍に設けられた接地部とを有し、これ
ら針状接点および接地部を入力部として前記テスト信号
の特性を計測することがより好ましい。In the present invention, the semiconductor substrate testing apparatus includes a needle contact for transmitting a test signal to the device section;
It is more preferable to have a grounding portion provided near the needle-like contact, and to measure the characteristics of the test signal using the needle-like contact and the grounding portion as input portions.
【0022】[0022]
【作用】上記発明では、試験対象であるウェハやガラス
基板などの半導体基板を試験する前あるいは試験途中に
おいて、測定用チップの第2針状接点をプローブカード
の接地部に、測定用チップの接触部をプローブカードの
第1針状接点にそれぞれ接触させ、この状態でテスト信
号を送出する。測定用チップの第2針状接点および接触
部には、試験対象である半導体基板のデバイス部に入力
されるのとほぼ同等のテスト信号が入力され、これがオ
シロスコープなどの信号特性測定装置に出力される。し
たがって、実際のテストと同等の電気的環境でテスト信
号の特性を測定することができ、測定結果の信頼性が著
しく高くなる。また、本発明ではプローブカードの第1
針状接点の近傍に接地部が設けられているので、接地部
から測定用チップを介して得られるテスト信号にノイズ
等が混入するおそれもきわめて小さい。In the above invention, before or during testing a semiconductor substrate such as a wafer or a glass substrate to be tested, the second needle-like contact of the measuring chip is brought into contact with the ground portion of the probe card and the contact of the measuring chip is brought into contact. The portions are brought into contact with the first needle contacts of the probe card, and a test signal is transmitted in this state. A test signal, which is substantially the same as that input to the device portion of the semiconductor substrate to be tested, is input to the second needle-like contact and the contact portion of the measurement chip, and is output to a signal characteristic measuring device such as an oscilloscope. You. Therefore, the characteristics of the test signal can be measured in the same electrical environment as in the actual test, and the reliability of the measurement result is significantly increased. In the present invention, the first probe card is used.
Since the grounding part is provided near the needle-shaped contact, there is a very small possibility that noise or the like is mixed in the test signal obtained from the grounding part via the measuring chip.
【0023】こうした測定は、プローブカードの第1針
状接点毎又は幾つかのグループ(対)毎に行われ、その
ために測定用チップを各第1針状接点に移動させる。測
定用チップに多数対の第2針状接点および接触部を設け
ておけば、多数の第1針状接点それぞれに送出されるテ
スト信号を一度に測定することができ、全ての第1針状
接点に対する測定時間を短縮することができる。逆に、
測定用チップに一対又は少数の対の第2針状接点および
接触部を設けた場合には、オシロスコープなどの信号特
性測定装置に対するケーブルが簡素なもので足りる。Such a measurement is performed for each first needle-like contact or several groups (pairs) of the probe card, and for this purpose, the measuring chip is moved to each first needle-like contact. If a large number of pairs of second needle-shaped contacts and contact portions are provided on the measuring chip, the test signals sent to each of the large number of first needle-shaped contacts can be measured at once, and all the first needle-shaped contacts can be measured. The measurement time for the contacts can be reduced. vice versa,
When a pair or a small number of pairs of second needle contacts and contact portions are provided on the measurement chip, a simple cable for a signal characteristic measuring device such as an oscilloscope is sufficient.
【0024】また、測定用チップを半導体基板の基板ス
テージに設けることで、測定用チップの移動を基板ステ
ージで行うことができ、測定用チップ専用のステージ装
置が不要となって、コスト的にもスペース的にも有利に
なる。Further, by disposing the measuring chip on the substrate stage of the semiconductor substrate, the measuring chip can be moved on the substrate stage, so that a dedicated stage device for the measuring chip is not required and the cost is reduced. It is also advantageous in terms of space.
【0025】[0025]
【発明の実施の形態】以下、本発明の実施形態を図面に
基づいて説明する。図1は、本発明の半導体基板試験装
置を示す全体図、図2は、図1の半導体基板試験装置の
要部を示す断面図、図3は、図1のプローブカードを示
す平面図である。なお、図3において、測定用チップを
2つ示しているが、右側の測定用チップ35は左側の測
定用チップを裏返して示した図である。Embodiments of the present invention will be described below with reference to the drawings. 1 is an overall view showing a semiconductor substrate test apparatus of the present invention, FIG. 2 is a cross-sectional view showing a main part of the semiconductor substrate test apparatus of FIG. 1, and FIG. 3 is a plan view showing the probe card of FIG. . In FIG. 3, two measurement chips are shown, and the right measurement chip 35 is a diagram in which the left measurement chip is turned upside down.
【0026】図1に示すように、本実施形態の半導体基
板試験装置1は、テスト信号を出力しテストを実行する
テスタ本体10と、このテスタ本体10にケーブルなど
を介して接続されたテストヘッド20と、被試験物であ
るウェハWが供給され、当該ウェハWに造り込まれた複
数のデバイス部をテストヘッド20のニードル(針状接
点)に接触させるように逐次移動させるプローバ30と
を備えている。As shown in FIG. 1, a semiconductor substrate testing apparatus 1 of the present embodiment includes a tester body 10 for outputting a test signal and executing a test, and a test head connected to the tester body 10 via a cable or the like. And a prober 30 to which a wafer W to be tested is supplied and a plurality of device parts built in the wafer W are sequentially moved so as to contact a needle (needle-shaped contact) of the test head 20. ing.
【0027】プローバ30において、被試験物であるウ
ェハWは、1枚のウェハに多数の半導体回路(デバイス
部)が集積されたものであり、テストを行う場合にはウ
ェハチャック(図示を省略する。)に真空吸着され、高
精度に位置出しされた状態で保持される。このため、ウ
ェハチャックはウェハステージ31に設けられ、このウ
ェハステージ31は、ベースプレート32に対して同図
に示すXY平面内を高精度で移動可能とされ、またウェ
ハステージ31全体又はウェハチャックのみがZ軸方向
に昇降可能とされている。In the prober 30, a wafer W to be tested has a large number of semiconductor circuits (device units) integrated on a single wafer. When a test is performed, a wafer chuck (not shown) is used. )) And is held in a state where it is positioned with high precision. For this reason, the wafer chuck is provided on the wafer stage 31, and the wafer stage 31 can be moved with high precision in the XY plane shown in FIG. It can move up and down in the Z-axis direction.
【0028】なお、図示は省略するが、ウェハWに所定
の温度を印加して高温テストを実行する場合には、ウェ
ハチャックに内装されたヒータを介してウェハWが加熱
されるようになっている。Although not shown, when a high temperature test is performed by applying a predetermined temperature to the wafer W, the wafer W is heated via a heater built in the wafer chuck. I have.
【0029】また、本実施形態のプローバ30には、ウ
ェハステージ31上部にカードホルダ33が設けられ、
ここにプローブカード34が保持されている。本例のプ
ローブカード34は、セラミックス又はシリコンからな
る、矩形状に形成された基板341を有し、その一主面
(図1,2において下面、図3において表面)に、複数
本のニードル342(本発明の第1針状接点に相当す
る。)が設けられ、図3に示すように複数列に並んで配
置されてなる。また、基板341の同じ主面には、アー
スに接続される接地部343のパターンがニードル34
2の列の間に形成されている。In the prober 30 of the present embodiment, a card holder 33 is provided above the wafer stage 31.
Here, a probe card 34 is held. The probe card 34 of the present example has a substrate 341 made of ceramics or silicon and formed in a rectangular shape, and a plurality of needles 342 are provided on one main surface (the lower surface in FIGS. 1 and 2 and the upper surface in FIG. 3). (Corresponding to the first needle-shaped contact of the present invention), and are arranged in a plurality of rows as shown in FIG. On the same main surface of the substrate 341, a pattern of a ground portion 343 connected to the ground is provided with the needle 34.
It is formed between two rows.
【0030】ニードル342は、ウェハWに集積形成さ
れた1個のデバイス部の端子(ワイヤボンディングする
前の状態の接点)に接触するように、たとえば直立して
設けられ、上述したウェハステージ31をXYZ空間内
で逐次移動させることにより試験を行うべきデバイス部
の各端子に接触することができる。The needle 342 is provided, for example, upright so as to come into contact with a terminal (a contact in a state before wire bonding) of one device unit integratedly formed on the wafer W. By sequentially moving in the XYZ space, it is possible to contact each terminal of the device section to be tested.
【0031】また、本実施形態のプローブカード34
は、基板341の反対側の主面(図1および図2では上
面、図3では裏面)に、ゼロ挿抜力コネクタ等からなる
コネクタの一方344が実装されている。Further, the probe card 34 of the present embodiment
Is mounted on a main surface on the opposite side of the substrate 341 (the upper surface in FIGS. 1 and 2 and the lower surface in FIG. 3), one of connectors 344 including a zero insertion / extraction force connector or the like.
【0032】なお、ゼロ挿抜力コネクタ(Zero Insersi
on Force Connector)とは、後述するテストヘッド20
側に設けられた他方のゼロ挿抜力コネクタ221と互い
に挿抜する際に、挿抜方向(本例では上下方向)に力を
加える必要がないタイプのコネクタをいい、たとえばコ
ネクタ内に長手方向に組み込まれているレールをシリン
ダにより前後に駆動させて、レールと係合しているカム
を上下させ、そのカムの上下によりピンコンタクトを挟
むソケットコンタクトの間隔を狭めたり広げたりする方
式、あるいはその他の方式のものを用いることができ
る。The zero insertion / extraction force connector (Zero Insersi
on Force Connector) is a test head 20 described later.
A connector that does not need to apply a force in the insertion / removal direction (vertical direction in this example) when the connector is inserted into and removed from the other zero insertion / removal force connector 221 provided on the side. The rail that is engaged with the rail is driven back and forth by the cylinder to raise and lower the cam that engages with the rail, and the pitch of the socket contact sandwiching the pin contact is narrowed or widened by the vertical movement of the cam, or other methods. Can be used.
【0033】各ニードル342とゼロ挿抜力コネクタ3
44の各接点とは、プローブカード34の基板341に
形成された配線パターンやスルーホール(何れも図示を
省略する。)により電気的に接続されている。Each needle 342 and zero insertion / extraction force connector 3
The contacts 44 are electrically connected to each other by wiring patterns and through holes (both not shown) formed on the substrate 341 of the probe card 34.
【0034】なお、本発明の半導体基板試験装置では、
プローブカード34とテストヘッド20とを電気的に接
続する手段は上述したゼロ挿抜力コネクタにのみ限定さ
れることはなく、他の種類のコネクタや接続端子であっ
ても何ら問題はない。In the semiconductor substrate testing apparatus of the present invention,
Means for electrically connecting the probe card 34 and the test head 20 are not limited to the zero insertion / extraction connector described above, and there is no problem even if other types of connectors or connection terminals are used.
【0035】一方、ウェハステージ31の上部には、半
導体基板試験装置1のテストヘッド20が位置し、図示
は省略するがここにパフォーマンスボードなどの各種基
板が設けられている。このテストヘッド20の最下面に
は、図1および図2に示すようにトップパネル21が固
定されており、さらにこのトップパネル21の下面にコ
ンタクトリング22が固定されている。また、このコン
タクトリング22には、上述したゼロ挿抜力コネクタの
他方221が固定されている。図2の断面図にこのゼロ
挿抜力コネクタ221,344の取り付け状態を示す。On the other hand, a test head 20 of the semiconductor substrate test apparatus 1 is located above the wafer stage 31. Although not shown, various substrates such as a performance board are provided here. As shown in FIGS. 1 and 2, a top panel 21 is fixed to the lowermost surface of the test head 20, and a contact ring 22 is further fixed to a lower surface of the top panel 21. Further, the other side 221 of the above-described zero insertion / extraction force connector is fixed to the contact ring 22. A cross-sectional view of FIG. 2 shows a state where the zero insertion / extraction force connectors 221 and 344 are attached.
【0036】なお、詳細な図示は省略するが、上述した
プローブカード34とコンタクトリング22との位置出
しは、プローブカード34側に設けられたガイドピン
を、コンタクトリング22側に設けられたガイドブッシ
ュに係合させるなどして行われる。Although not shown in detail, the positioning of the probe card 34 and the contact ring 22 is performed by using a guide pin provided on the probe card 34 side and a guide bush provided on the contact ring 22 side. And the like.
【0037】また、コンタクトリング22側に取り付け
られたゼロ挿抜力コネクタ221と、テストヘッド20
内のパフォーマンスボードとは、多数の配線あるいはド
ータボードにより電気的に接続されている。A zero insertion / extraction force connector 221 attached to the contact ring 22 side and a test head 20
Are electrically connected to each other by a number of wires or daughter boards.
【0038】特に本実施形態のプローバ30では、図3
に示す測定用チップ35が、図2に示すようにウェハス
テージ31のフランジ311に上向きに設けられてい
る。この測定用チップ35は、プローブカード34の基
板341と同じセラミックスやシリコンからなる基板3
51を有し、この基板351の一主面(図1および図2
では上面、図3の左図では下面、同図右図では上面)
に、1本のニードル352(本発明の第2針状接点に相
当する。)と、アースに接続される一つの接触部353
のパターンが形成されている。これらニードル352と
接触部353との間隔は、上述したプローブカード34
のニードル342と接地部343との間隔とほぼ等しく
設定されており、図2に示すように、測定用チップ35
をプローブカード34の一対のニードル342および接
地部343に接近させると、測定用チップのニードル3
53がプローブカード34の接地部343に、プローブ
カード34のニードル342が測定用チップ35の接触
部353にそれぞれ同時に接触する。In particular, in the prober 30 of this embodiment, FIG.
2 is provided on the flange 311 of the wafer stage 31 in an upward direction as shown in FIG. The measurement chip 35 is made of a substrate 3 made of the same ceramics or silicon as the substrate 341 of the probe card 34.
1 and one main surface of the substrate 351 (FIGS. 1 and 2).
Then, the top view, the bottom view in the left view of FIG. 3, and the top view in the right view of FIG.
In addition, one needle 352 (corresponding to a second needle contact of the present invention) and one contact portion 353 connected to the ground.
Is formed. The distance between the needle 352 and the contact portion 353 is determined by the probe card 34 described above.
The distance between the needle 342 and the grounding part 343 is set substantially equal to that of the measurement tip 35 as shown in FIG.
Is brought closer to the pair of needles 342 and the ground part 343 of the probe card 34, the needle 3
53 contacts the ground portion 343 of the probe card 34 and the needle 342 of the probe card 34 simultaneously contacts the contact portion 353 of the measurement chip 35.
【0039】なお、測定用チップ35のニードル352
および接触部353は、図3の右図に示すようにケーブ
ル等を介してオシロスコープ40に接続され、その測定
されたテスト信号の波形が観測される。The needle 352 of the measuring chip 35
The contact section 353 is connected to the oscilloscope 40 via a cable or the like as shown in the right diagram of FIG. 3, and the waveform of the measured test signal is observed.
【0040】次に作用を説明する。ウェハWをテストす
る場合には、まずそのウェハWをウェハチャックに位置
決めしながら吸着保持した状態で、目的とするウェハW
のデバイス部の接点にプローブカード34のニードル3
42が接触するように、ウェハステージ31をXY平面
において位置出ししながら上昇させる。これにより、あ
る幾つかのデバイス部のテストが実行されるが、ここで
のテストを終了すると、ウェハステージ31を僅かに下
降させ、次のデバイスの接点にプローブカード34のニ
ードル342が接触するように、ウェハステージ31を
XY平面において位置出ししながら再び上昇させる。順
次この動作を繰り返し、全ての領域におけるウェハWの
デバイス部のテストを行う。また、このウェハWに対し
て高温テスト行う場合には、ウェハチャックに内装され
たヒータを作動させてウェハWをたとえば100℃まで
加熱昇温させる。Next, the operation will be described. When testing the wafer W, the target wafer W is first held while being suction-held while being positioned on the wafer chuck.
Needle 3 of probe card 34
The wafer stage 31 is moved up while being positioned on the XY plane so that the wafer stage 42 comes into contact with the wafer stage 31. As a result, a test of some of the device sections is executed. When the test is completed, the wafer stage 31 is slightly lowered, and the needle 342 of the probe card 34 comes into contact with the contact of the next device. Then, the wafer stage 31 is raised again while being positioned on the XY plane. This operation is sequentially repeated to test the device portion of the wafer W in all regions. When a high-temperature test is performed on the wafer W, the heater inside the wafer chuck is operated to heat and raise the temperature of the wafer W to, for example, 100 ° C.
【0041】特に本実施形態の半導体基板試験装置1で
は、上述したウェハテストを行う前に、あるいはウェハ
テストを行っている途中で必要が生じたときに、テスタ
本体10からテストヘッド20を介してデバイス部へ送
出されるテスト信号の波形を測定し、各テスト信号の位
相補正を行う。In particular, in the semiconductor substrate testing apparatus 1 of the present embodiment, before the above-described wafer test is performed or when the need arises during the wafer test, the tester main body 10 transmits the test data via the test head 20. The waveform of the test signal sent to the device section is measured, and the phase of each test signal is corrected.
【0042】すなわち、ウェハステージ31をXY平面
内で移動させ、フランジ311に固定された測定用チッ
プ35をプローブカード34の下方に位置させる。ここ
で、プローブカード34の一つのニードル342と、そ
の近傍に形成された接地部343とのそれぞれに、測定
用チップの接触部353とニードル352とが接触する
ようにウェハステージを上昇させる。そして、この状態
でテスタ本体10から所定のテスト信号を送出し、これ
をオシロスコープで観測する。That is, the wafer stage 31 is moved in the XY plane, and the measurement chip 35 fixed to the flange 311 is positioned below the probe card 34. Here, the wafer stage is raised so that the contact part 353 of the measurement chip and the needle 352 are in contact with one needle 342 of the probe card 34 and the ground part 343 formed in the vicinity thereof. Then, in this state, a predetermined test signal is transmitted from the tester main body 10, and this is observed with an oscilloscope.
【0043】本例では、実際のテスト信号が入力される
ウェハWのデバイス部とほぼ同じ位置において、つまり
プローブカード34のニードル342の先端をテスト信
号のオシロスコープ40への入力部としているので、当
該オシロスコープにて観測されるテスト信号の波形は実
際に入力されるものとほぼ等しくなる。また、プローブ
カード34には、ニードル342の近傍に接地部343
が設けられているので、オシロスコープ40にて観測さ
れる信号波形にノイズ等が混入することも極力抑制さ
れ、その結果、正確なテスト信号波形を得ることができ
る。In this example, the test signal is input to the oscilloscope 40 at substantially the same position as the device section of the wafer W to which the actual test signal is input, that is, the tip of the needle 342 of the probe card 34 is used as the input section to the oscilloscope 40. The waveform of the test signal observed by the oscilloscope is substantially equal to the waveform actually input. The probe card 34 has a grounding portion 343 near the needle 342.
Is provided, noise and the like are prevented from being mixed in the signal waveform observed by the oscilloscope 40, and as a result, an accurate test signal waveform can be obtained.
【0044】なお、本例では測定用チップ35の基板3
51として、プローブカード34の基板341と同じ材
料を採用しているが、こうすることで、少なくともプロ
ーブカード34と同じ微細なニードルおよび接地部は形
成可能だからである。したがって、プローブカード34
のニードルおよび接地部のパターンに応じた微細なもの
が製造できるのであれば、特に材質は限定されない趣旨
である。In this embodiment, the substrate 3 of the measuring chip 35
The same material as that of the substrate 341 of the probe card 34 is adopted as the material 51, but by doing so, at least the same fine needles and ground portions as those of the probe card 34 can be formed. Therefore, the probe card 34
The material is not particularly limited as long as it is possible to manufacture a fine material according to the pattern of the needle and the grounding portion.
【0045】なお、以上説明した実施形態は、本発明の
理解を容易にするために記載されたものであって、本発
明を限定するために記載されたものではない。したがっ
て、上記の実施形態に開示された各要素は、本発明の技
術的範囲に属する全ての設計変更や均等物をも含む趣旨
である。The embodiments described above are described for facilitating the understanding of the present invention, and are not described for limiting the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention.
【0046】[0046]
【発明の効果】以上述べたように本発明によれば、テス
タ本体から送出されるテスト信号の波形等の信号特性を
高精度で測定できる半導体基板試験装置を提供すること
ができる。As described above, according to the present invention, it is possible to provide a semiconductor substrate testing apparatus capable of measuring signal characteristics such as a waveform of a test signal transmitted from a tester main body with high accuracy.
【図1】本発明の半導体基板試験装置を示す全体図であ
る。FIG. 1 is an overall view showing a semiconductor substrate test apparatus of the present invention.
【図2】図1の半導体基板試験装置の要部を示す断面図
である。FIG. 2 is a cross-sectional view showing a main part of the semiconductor substrate test apparatus of FIG.
【図3】図1のプローブカードを示す平面図である。FIG. 3 is a plan view showing the probe card of FIG. 1;
【図4】IC試験装置(テスタ本体)から出力されるテ
スト信号の一例を示す波形図である。FIG. 4 is a waveform diagram illustrating an example of a test signal output from an IC test apparatus (tester main body).
【図5】本発明の課題を説明するための波形図である。FIG. 5 is a waveform chart for explaining the problem of the present invention.
1…半導体基板試験装置 10…テスタ本体 20…テストヘッド 30…プローバ 31…ウェハステージ 34…プローブカード 342…ニードル(第1針状接点) 343…接地部 35…測定用チップ 352…ニードル(第2針状接点) 353…接触部 40…オシロスコープ(信号特性測定装置) DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate testing apparatus 10 ... Tester main body 20 ... Test head 30 ... Prober 31 ... Wafer stage 34 ... Probe card 342 ... Needle (first needle contact) 343 ... Ground part 35 ... Measurement chip 352 ... Needle (Second) Needle-shaped contact) 353 contact part 40 oscilloscope (signal characteristic measuring device)
Claims (12)
のテスト信号を送出してテストを行い、その結果に応じ
て前記デバイス部の良否を判別する半導体基板試験装置
であって、 前記デバイス部に電気的に接触する複数の第1針状接点
と、この第1針状接点の近傍に設けられた接地部とが一
主面に設けられ、テストヘッド基板に電気的に接続され
るプローブカードと、 前記第1針状接点に電気的に接触する接触部と、前記接
地部に電気的に接触する第2針状接点とが一主面に設け
られた測定用チップと、を備えた半導体基板試験装置。1. A semiconductor substrate test apparatus for transmitting a plurality of test signals to a device section formed on a semiconductor substrate to perform a test, and for determining whether the device section is good or bad according to a result of the test. Probe card electrically connected to a test head substrate, having a plurality of first needle-like contacts electrically contacting the first head-like contact and a grounding portion provided near the first needle-like contact on one main surface. A semiconductor chip comprising: a contact portion electrically contacting the first needle contact; and a measurement chip provided on one main surface with a second needle contact electrically contacting the ground portion. Substrate testing equipment.
の前記第1針状接点および接地部の配列に応じて、一又
はそれ以上の対をなす第2針状接点および接触部を有す
る請求項1記載の半導体基板試験装置。2. The measuring chip has one or more pairs of second needle-like contacts and contact portions according to the arrangement of the first needle-like contacts and ground portions of the probe card. 2. The semiconductor substrate test apparatus according to claim 1.
第1針状接点および接地部に対して移動させる測定用チ
ップステージをさらに備えた請求項1または2記載の半
導体基板試験装置。3. The semiconductor substrate testing apparatus according to claim 1, further comprising a measurement chip stage for moving said measurement chip with respect to said first needle-like contact and ground portion of said probe card.
ードの第1針状接点に前記デバイス部を接触させる基板
ステージをさらに備え、 前記測定用チップが前記基板ステージに設けられている
請求項1〜3記載の半導体基板試験装置。4. The apparatus according to claim 1, further comprising a substrate stage for holding said semiconductor substrate and bringing said device portion into contact with a first needle-like contact of said probe card, wherein said measuring chip is provided on said substrate stage. 4. The semiconductor substrate testing device according to any one of items 1 to 3.
前記テスト信号の特性を出力する信号特性測定装置をさ
らに備えた請求項1〜4記載の半導体基板試験装置。5. The measurement chip is connected to an output terminal of the measurement chip,
5. The semiconductor substrate testing apparatus according to claim 1, further comprising a signal characteristic measuring device for outputting characteristics of the test signal.
請求項5記載の半導体基板試験装置。6. The semiconductor substrate testing apparatus according to claim 5, wherein the characteristic of the test signal is a signal waveform.
電気的に接続され、半導体基板のデバイス部に電気的に
接触する複数の針状接点が一主面に設けられた半導体基
板試験装置用プローブカードであって、 前記針状接点の近傍に接地部が設けられている半導体基
板試験装置用プローブカード。7. A probe for a semiconductor substrate testing apparatus, wherein a plurality of needle-shaped contacts electrically connected to a test head substrate of the semiconductor substrate testing apparatus and electrically contacting device parts of the semiconductor substrate are provided on one main surface. A probe card for a semiconductor substrate testing device, comprising: a card, wherein a ground portion is provided near the needle contact.
設けられている請求項7記載の半導体基板試験装置用プ
ローブカード。8. The probe card for a semiconductor substrate test apparatus according to claim 7, wherein said ground portion is provided in common for a plurality of needle-like contacts.
けられた第1針状接点に電気的に接触する接触部と、前
記第1針状接点の近傍に設けられた接地部に電気的に接
触する第2針状接点とを備えた半導体基板試験装置の測
定用チップ。9. A contact portion provided on a probe card for a semiconductor substrate testing apparatus, the contact portion being in electrical contact with a first needle-like contact, and an electrical contact being made with a ground portion provided near the first needle-like contact. A measurement chip of a semiconductor substrate test device, comprising: a second needle-like contact.
数のテスト信号を送出してテストを行い、その結果に応
じて前記デバイス部の良否を判別する半導体基板試験装
置の、前記テスト信号の特性を測定する方法であって、 前記半導体基板試験装置の前記デバイス部に接する部分
の少なくとも近傍を接点として、前記テスト信号の特性
を測定する半導体基板試験装置におけるテスト信号特性
の測定方法。10. A characteristic of the test signal of a semiconductor substrate test apparatus for transmitting a plurality of test signals to a device portion formed on a semiconductor substrate to perform a test, and determining whether the device portion is good or bad according to the result. A method of measuring a test signal characteristic in a semiconductor substrate test apparatus, wherein a characteristic of the test signal is measured by using at least a vicinity of a portion of the semiconductor substrate test apparatus that contacts the device section as a contact point.
る請求項10記載の半導体基板試験装置におけるテスト
信号特性の測定方法。11. The method according to claim 10, wherein the characteristic of the test signal is a signal waveform.
部にテスト信号を送信する針状接点と、前記針状接点の
近傍に設けられた接地部とを有し、これら針状接点およ
び接地部を入力部として前記テスト信号の特性を計測す
る請求項10または11記載の半導体基板試験装置にお
けるテスト信号特性の測定方法。12. The semiconductor substrate testing apparatus has a needle-like contact for transmitting a test signal to the device section, and a grounding section provided near the needle-like contact. The method for measuring test signal characteristics in a semiconductor substrate test apparatus according to claim 10, wherein characteristics of the test signal are measured as an input unit.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24890599A JP4183859B2 (en) | 1999-09-02 | 1999-09-02 | Semiconductor substrate testing equipment |
TW89117199A TW541430B (en) | 1999-09-02 | 2000-08-25 | Test device for semiconductor wafers |
DE2000143193 DE10043193B4 (en) | 1999-09-02 | 2000-09-01 | Tester for semiconductor substrates |
KR10-2000-0051602A KR100478261B1 (en) | 1999-09-02 | 2000-09-01 | Semiconductor substrate testing apparatus |
Applications Claiming Priority (1)
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JP24890599A JP4183859B2 (en) | 1999-09-02 | 1999-09-02 | Semiconductor substrate testing equipment |
Publications (2)
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JP2001077160A true JP2001077160A (en) | 2001-03-23 |
JP4183859B2 JP4183859B2 (en) | 2008-11-19 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP24890599A Expired - Fee Related JP4183859B2 (en) | 1999-09-02 | 1999-09-02 | Semiconductor substrate testing equipment |
Country Status (4)
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---|---|
JP (1) | JP4183859B2 (en) |
KR (1) | KR100478261B1 (en) |
DE (1) | DE10043193B4 (en) |
TW (1) | TW541430B (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US7332916B2 (en) | 2005-03-03 | 2008-02-19 | Semiconductor Technology Academic Research Center | On-chip signal waveform measurement apparatus for measuring signal waveforms at detection points on IC chip |
US8144045B2 (en) | 2009-07-01 | 2012-03-27 | Semiconductor Technology Academic Research Center | Timing signal generator circuit for use in signal waveform measurement system for measuring multi-channel on-chip signals flowing on VLSI |
US8207744B2 (en) | 2007-06-29 | 2012-06-26 | Advantest Corporation | Testing apparatus |
US8513962B2 (en) | 2009-08-07 | 2013-08-20 | Advantest Corporation | Wafer tray and test apparatus |
US9287476B2 (en) | 2008-09-03 | 2016-03-15 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US7319335B2 (en) | 2004-02-12 | 2008-01-15 | Applied Materials, Inc. | Configurable prober for TFT LCD array testing |
US7535238B2 (en) | 2005-04-29 | 2009-05-19 | Applied Materials, Inc. | In-line electron beam test system |
US7786742B2 (en) | 2006-05-31 | 2010-08-31 | Applied Materials, Inc. | Prober for electronic device testing on large area substrates |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB8515025D0 (en) * | 1985-06-13 | 1985-07-17 | Plessey Co Plc | Calibration apparatus |
JP2576233Y2 (en) * | 1991-08-05 | 1998-07-09 | 株式会社アドバンテスト | Connection mechanism between test head and sample of IC test equipment |
US5565788A (en) * | 1994-07-20 | 1996-10-15 | Cascade Microtech, Inc. | Coaxial wafer probe with tip shielding |
JPH08139142A (en) * | 1994-11-09 | 1996-05-31 | Tokyo Electron Ltd | Probe unit |
JP3188935B2 (en) * | 1995-01-19 | 2001-07-16 | 東京エレクトロン株式会社 | Inspection device |
US5729150A (en) * | 1995-12-01 | 1998-03-17 | Cascade Microtech, Inc. | Low-current probe card with reduced triboelectric current generating cables |
-
1999
- 1999-09-02 JP JP24890599A patent/JP4183859B2/en not_active Expired - Fee Related
-
2000
- 2000-08-25 TW TW89117199A patent/TW541430B/en not_active IP Right Cessation
- 2000-09-01 DE DE2000143193 patent/DE10043193B4/en not_active Expired - Fee Related
- 2000-09-01 KR KR10-2000-0051602A patent/KR100478261B1/en not_active IP Right Cessation
Cited By (13)
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US7609100B2 (en) | 2005-03-03 | 2009-10-27 | Semiconductor Technology Academic Research Center | On-chip signal waveform measurement apparatus for measuring signal waveforms at detection points on IC chip |
US7332916B2 (en) | 2005-03-03 | 2008-02-19 | Semiconductor Technology Academic Research Center | On-chip signal waveform measurement apparatus for measuring signal waveforms at detection points on IC chip |
US8207744B2 (en) | 2007-06-29 | 2012-06-26 | Advantest Corporation | Testing apparatus |
US9490411B2 (en) | 2008-09-03 | 2016-11-08 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US9287476B2 (en) | 2008-09-03 | 2016-03-15 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US9537071B2 (en) | 2008-09-03 | 2017-01-03 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US10115870B2 (en) | 2008-09-03 | 2018-10-30 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US10573789B2 (en) | 2008-09-03 | 2020-02-25 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US10573788B2 (en) | 2008-09-03 | 2020-02-25 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US10700241B2 (en) | 2008-09-03 | 2020-06-30 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US11094854B2 (en) | 2008-09-03 | 2021-08-17 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US8144045B2 (en) | 2009-07-01 | 2012-03-27 | Semiconductor Technology Academic Research Center | Timing signal generator circuit for use in signal waveform measurement system for measuring multi-channel on-chip signals flowing on VLSI |
US8513962B2 (en) | 2009-08-07 | 2013-08-20 | Advantest Corporation | Wafer tray and test apparatus |
Also Published As
Publication number | Publication date |
---|---|
JP4183859B2 (en) | 2008-11-19 |
KR100478261B1 (en) | 2005-03-23 |
DE10043193B4 (en) | 2007-05-03 |
KR20010050313A (en) | 2001-06-15 |
DE10043193A1 (en) | 2001-04-12 |
TW541430B (en) | 2003-07-11 |
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