JP2001075862A - Computer application device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable different systems to use the same memory chip by arranging programs unique to machines so that they correspond to start addresses varied from an address supplied to the memory chip. SOLUTION: The memory chip 14 is provided which stores a 1st program for device actuation in a 1st area 12 including a start address SA after resetting corresponding to a CPU 10 while including the start address SA in its address range. The address on the memory chip 14 specified by the start address SA can be varied to multiple kinds by varying the values of the most significant bit or multiple bits of an address supplied directly from the CPU 10 to the memory chip 14 through an address varying means 18 like an inverter. In a 2nd area 16 including the start address SA1 after the change on the memory chip 14, a 2nd program for device actuation can be stored.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer application device such as a program display device, and more particularly to a computer application device characterized by a method for accessing a memory chip.

[0002]

2. Description of the Related Art Conventionally, in this type of device, various data that does not need to be changed after the device is constructed, such as various programs such as a boot program and various data such as character fonts, are stored in a ROM. It is generally used.

Here, data such as fonts is generally used regardless of the type of device, and generally has a large data amount. On the other hand, the program depends on the model, the address position is often specified in advance for each model, and the data amount is smaller than the data such as fonts.

[0004]

In recent years, however, the capacity of a mask ROM composed of one chip has increased,
Even if all data to be ROMized, including programs used in one model, are stored on one memory chip, there is still room for memory capacity.

[0005] Furthermore, since the proportion of programs occupying the mask ROM tends to be smaller and smaller, programs corresponding to a plurality of types of models are also stored at the same time.
It is also conceivable to share OM chips.

[0006] However, in a boot program that needs to be ROMized most, a CPU to be used is used.
As a result, the start address is fixed.
It has been considered that it is impossible to store programs of a plurality of models on the same ROM at the same time because it is necessary to store the same program in the same address on the OM.

As a result of studying the above problem, the present inventor has found that the address output from the CPU is the same between the case where the upper bits of the address are inverted and supplied to the memory chip from the CPU and the case where the address is supplied as it is. R
By accessing different addresses on the OM and storing necessary programs corresponding to the addresses, it has been found that a plurality of models-dependent programs can be stored simultaneously.

The present invention has been made on the basis of such knowledge, and a computer application device capable of sharing parts by reducing the manufacturing cost by enabling a ROM chip to be used in a plurality of different systems. The purpose is to provide.

[0009]

FIG. 1 schematically shows the configuration of a computer application apparatus according to the present invention.
Start address SA after reset for CPU 10
Is included in its own address range, and a memory chip 14 storing a first program for activating the device is provided on a first area 12 including the start address SA.

Further, by changing the value of the most significant one or more bits in the address directly supplied from the CPU 10 to the memory chip 14 through the address changing means 18 such as an inverter, for example. The address on the memory chip 14 specified by the start address can be changed to a plurality of types. On the other hand, a second program for activating the device is stored in a second area 16 on the memory chip 14 including the changed start address SA1.

The above-mentioned memory chip 14 is a mask ROM.
The upper plural bits of the address signal output from the CPU 10 are used for selecting the memory chip 14 as shown in FIG. 3, and the address is specified on the memory chip 14 by using the remaining lower plural bits. As shown in FIG. 5, the most significant bit position in the plurality of lower bits supplied to the memory chip 14 is inverted and supplied.

The first on the memory chip 14
General-purpose data commonly used in a plurality of systems is stored in an area other than the area storing the second program.

The program and data stored in the memory chip 14 are for realizing a function as a programmable display device illustrated in FIG. 2 which enables a display corresponding to a control state of predetermined control means. It is.

[0014]

According to the present invention, as described above, the memory chip 14
The same memory chip 14 can be used in a plurality of different systems by changing the address supplied to the system and providing a plurality of start addresses and arranging a model-specific program corresponding to the start address. Therefore, manufacturing costs are reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A computer application apparatus according to the present invention will now be described with reference to FIG.
C22 to which a program-type display device 24 is connected for performing display and control corresponding to the status data handled there.
A specific description will be given based on an example implemented in (1). However, it is needless to say that the present invention can be carried out in substantially the same manner by using a general-purpose or special-purpose computer or other control device as a computer application device, or a device for controlling the operation of various electric appliances at home.

The programmable display device 24 includes a PLC 22
In addition, they are integrated into an operation console or the like of the target system 20 or are independently provided and used as an operation and display panel for the target system 20.

PLC for controlling the target system 20
A circuit 22 is a unit for each required function such as a CPU unit and a memory unit, and the functions achieved as a whole in the PLC 22 are connected in parallel so that each unit can be increased or decreased as necessary. The configuration is substantially the same as that of the related art that can be changed.

The storage location of various information input / output to / from the target system 20 is controlled by various sensors provided on the target system 20 to be controlled or displayed, passive components such as level meters and limit switches, relays, and the like. Active devices such as motors are allocated on the memory unit, and word devices are specified for word data whose input / output is numerical values, and bit devices are specified for bit data such as on / off information. Is done. Furthermore,
By preliminarily setting a device address such as “D100” specific to each device, a state data necessary for specifying a storage location by designating the device address is stored in the memory unit.

Therefore, only by specifying a device address from a device inside or outside the PLC 22 to an arbitrary word device or bit device in the memory unit and without knowing the actual address in the PLC 22, The position is controlled or data relating to the operation state can be individually taken out.

On the other hand, in the programmable display device 24, a display screen using, for example, a liquid crystal display device as the display 26 is arranged on the front side of the substantially rectangular main body case, and the touch panel 2 is brought into close contact with the display screen.
8 and the display control circuit 3 inside the main body case.
0, the display corresponding to the control state of the PLC 22 is performed on the display screen, and at the same time, the data input by the fingertip via the touch panel 28 and the PLC 2
Control on two sides is possible.

The display control circuit 30 is basically the same as a personal computer as shown in FIGS.
The PU 10 is provided as a center of control, and various memories such as a RAM 40 and a ROM 42 or a graphic controller 44 are connected via a bus line 38 such as an address bus 32, a data bus 34, or a control bus 36. The contents are developed on the video RAM 46 via the graphic controller 44 and the corresponding contents are displayed on the screen of the display 26.

Here, an application program for performing a predetermined display operation on the display screen and a PLC referenced from the program are stored in the RAM 40.
Like the state data on the 22 side, data whose contents may be changed are stored.

On the other hand, in the ROM 42, data which does not need to be changed or which should not be changed after the system is constructed, such as a boot program, a system program such as an OS, or font data, is stored in ROM. ing.

The present invention has the above-mentioned structure and further comprises RO
A feature is that two types of boot programs of the first and second systems are stored simultaneously on the M42, and the ROM 42 can be shared by two systems having different configurations.

In the following, a mask ROM having a capacity of 8 Mbytes is used as the ROM 42, the address bus 32 has a 32-bit width, and the CPU 10
Will be described based on an example in which the start address accessed after resetting is preset to the address “FFFFFFF0” in hexadecimal. However, these values are merely examples, and it is needless to say that the values can be appropriately changed and implemented. is there.

Here, in the first system, as shown in FIG. 3, in the 32-bit addresses A0 to A31 output from the CPU 10, a 23-bit address required to access an 8-Mbyte ROM area is used. Minute address A0
To A22 are supplied directly to the ROM 42.

On the other hand, the remaining 9 in the above address
Addresses A23 to A31 for the bits are supplied to a decoder 48, and when all 9 bits are "1", a select signal 50 is sent to the ROM 42 to select a corresponding memory chip.

In the address configuration as described above, C
Since the address bus 32 between the PU 10 and the ROM 42 is directly connected without data conversion in substantially the same manner as in the prior art, the ROM 42 viewed from the CPU 10 as shown in FIG.
The address configuration in the lowermost address is “FF8000
00 "to the highest address" FFFFFFFF ".

Therefore, "FEB00000" including "FFFFFFF0" which is the start address of the CPU 10 is used.
To “FFFFFFFF” are allocated as dedicated areas of the first system, and a first program such as a boot program necessary for operating the first system is stored.

On the other hand, in the second system, as shown in FIG. 5, the other parts are the same as those in the first system, but the highest address A22 in the addresses A0 to A22 supplied to the ROM 42 is used. Is supplied through the inverter 52 after being inverted.

Then, as shown in FIG.
The address arrangement looking at the OM42 side is “FFBFFFF
"F" and "FFC00000", the start address is "FFFFFFF0"
Is output from the CPU 10, the address "FFBFFFF0" on the ROM 42 is accessed.

Therefore, "FF" including the start address
The area from address "B80000" to the address "FFBFFFFF" is allocated exclusively for the second system, and the second
Stores system-specific programs.

Further, in the area excluding the above-mentioned first and second system-dedicated areas, the first type of font data, such as two types of font data including a Japanese font and a foreign language font, is provided.
The ROM 42 that can be shared by the first and second systems is configured by storing various data that can be commonly used by the first and second systems.

In the above-described embodiment, since only one bit of the address signal supplied to the ROM is converted, the start address becomes two types and can be stored on one ROM chip. The system programs are also limited to two types.

However, if data is converted for the upper two bits of the address bus supplied to the ROM, the number of start addresses can be increased to four, and the number of system programs that can be stored simultaneously can be further increased. is there.

In the above embodiment, the same ROM chip is used for two display devices having different system configurations. However, by providing a function to enable the above-mentioned address change by a switch operation in one display device and supplying an application program by an IC card or the like, a different system can be realized by one display device. it can.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a basic configuration of the present invention.

FIG. 2 is a block diagram showing an example in which the present invention is applied to a programmable display device.

FIG. 3 is an explanatory diagram showing a memory device structure in the first system.

FIG. 4 is an explanatory diagram showing a relationship between an address arrangement as viewed from a CPU and an address arrangement on a ROM in the first system.

FIG. 5 is an explanatory diagram showing a memory device structure in a second system.

FIG. 6 is an explanatory diagram showing a relationship between an address arrangement viewed from a CPU and an address arrangement on a ROM in the second system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 CPU 12 1st area 14 Memory chip 16 2nd area 18 Address change means 20 Target system 22 PLC 24 Programmatic display device 26 Display 28 Touch panel 30 Display control circuit 32 Address bus 34 Data bus 36 Control bus 38 Bus line 40 RAM 42 ROM 44 Graphic controller 46 Video RAM 48 Decoder 50 Select signal 52 Inverter

Claims (4)

[Claims] 1. A start address after reset for a CPU (10) is included in its own address range, and a first program for starting the apparatus is stored in a first area (12) including the start address. A computer application device having a memory chip (14), wherein the value of one or more most significant bits is changed in an address directly supplied from the CPU (10) to the memory chip (14). Thereby, the address on the memory chip (14) specified by the start address can be changed to a plurality of types, and the second area (16) including the changed start address on the memory chip (14) Above, a second for device activation
A computer application device characterized by storing the above program. 2. The memory chip (14) is a mask ROM, and uses a plurality of upper bits of an address signal output from a CPU (10) for selecting a memory chip (14) and a remaining lower bit. 2. An address designation on a memory chip using a plurality of bits, wherein an uppermost bit position in a plurality of lower-order bits supplied to the memory chip is inverted and supplied.
The computer application device according to claim 1. 3. An area other than the area where the first and second programs are stored on the memory chip (14) stores general-purpose data commonly used in a plurality of systems. Item 3. A computer application device according to item 2. 4. The program and data stored in the memory chip (14) are for realizing a function as a programmable display device that enables display corresponding to a control state of a predetermined control means. The computer application device according to claim 3.