JP2001067822A - Ecc circuit and disk-reproducing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a disk-reproducing apparatus which can improve an ECC- processing speed while holding a high error-detecting efficiency and can reproduce disks at high speed with a high reliability. SOLUTION: The disk-reproducing apparatus includes a pickup 12 and an RF amplifier 13 for reading out information recorded to an optical disk 11, a signal-processing circuit 14 for processing signals generated by the RF amplifier 13, a decoder 20 for carrying out an error-correcting process for data supplied from the signal-processing circuit, and transferring error-corrected data outside, and a buffer RAM 25 to which data from the signal-processing circuit is temporarily written to be accessed at the error-correcting process. In this case, the decoder has a syndrome calculation circuit 201 for syndrome calculating a P correcting sequence with the utilization of an ECC parity concurrently with writing data to the buffer RAM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ECC circuit for executing an error correction process during reproduction of an optical disc, and a disc reproducing apparatus provided with the ECC circuit.

[0002]

2. Description of the Related Art As an optical disk reproducing apparatus reproduces a CD-ROM or the like at a high speed, it is required to improve a reproducing speed and transfer data at a high rate. Generally, data on a disc is transferred to a decoding system through an error correction system on the player side. The data on the disk is divided into blocks of data called sectors and sent to the decoding system. The data for each sector sent to the decoding system includes, for example, SYNC of a synchronization signal indicating the beginning of a block, HEADER and SUBHEADER having information on a position and a mode form, USERDATA having user information, and an error detection code E.
DC, ECC parity which is a code for error correction, and the like are included. The contents of these data differ depending on the format mode.
1 shows the data content of one sector in the CD-ROM format. A decoder in the decoding system, for example, a CD-ROM decoder performs access such as data writing to a buffer RAM as a memory to which data is written, transfer to a host computer, and error correction within a time inversely proportional to the playback speed of the disk. It is important to end.

[0003] With respect to data for each sector sent into the decoding system, the decoder performs error correction processing based on a predetermined algorithm. Conventional examples of the defined algorithm include the following. First, the error correction process is always performed regardless of the presence or absence of an error.
In the first case, it is necessary to increase the access capability to the buffer RAM as the reproduction speed of the disk increases. This is because it is desirable to complete a series of access operations for error correction always performed for each sector before data of the next sector is transferred. Also the second
Is to execute an error correction process only when it is determined that an error is included by error detection. That is, EDC (error detection code) previously included in the data for each sector sent into the decoding system,
And IPF such as a C2 correction flag, a C2 uncorrectable flag or a correction flag, to determine the necessity of the error correction process. This allows data transfer to the host computer without performing the error correction processing, if the error correction processing is not necessary.

[0004] Here, the EDC is included as data on the disk. The IPF is added via an error correction system in data processing on the player side. Therefore,
The use of EDC or IPF can be said to be an error detecting means that does not require access to the buffer RAM in the decoding system. With such an error detection means, there is no need to worry about improving the performance of the buffer RAM, that is, improving the processing speed of ECC. According to the decoding system employing the second algorithm, at least a part of the data transfer can be expected to save the time for executing the error correction processing, and thus the data transfer to the host computer can be performed quickly. Becomes possible. As a result, a decoding system having a fast access time can be constructed.

[0005]

With respect to data for each sector sent from the player side of the disc into the decoding system, the conventional decoder performs error correction processing on all data regardless of the presence or absence of an error. First
And a second algorithm in which an error correction process is executed only when it is determined that an error is included by error detection. As the playback speed of the disc increases, it is better to employ the second algorithm for determining whether or not to perform error correction processing using EDC and IPF, rather than the first algorithm, which is more difficult to improve the processing speed of ECC. It is advantageous. This is because adopting the second algorithm increases the data transfer speed, does not require changing the circuit size of the buffer RAM, and is inexpensive. However, EDC has an ECC of an error correction code added for error correction of data for each sector.
It is not concerned with the correctness of data including parity. This is because the ECC parity itself is not a target of error detection by the EDC. Also IPF
Is information added by the player using an original algorithm, and is not absolute in terms of reliability. Therefore, it is not necessarily sufficient to determine that error correction is not performed only from the EDC or IPF with the improvement of the reproduction speed of the disk to obtain high reliability in the reproduction of the disk.

[0006] In addition to these, an RA exclusive to ECC is used.
By incorporating M in the decoder, access to the buffer RAM at the time of error correction can be made unnecessary and the processing speed of ECC can be improved. But in this case,
Since it is necessary to newly add a very large-capacity dedicated RAM, a problem occurs in that the circuit scale of the decoder becomes very large. Therefore, in view of the circumstances described above, the present invention can improve the processing speed of the ECC while having a high error detection capability without significantly increasing the circuit scale. It is an object of the present invention to provide an ECC circuit and a disk reproducing device that enable reproduction of a disk.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an apparatus for performing error correction on data containing ECC parity for error correction processing which is sent from a disc player to a decoding system and written into a memory. An ECC circuit comprising: an error correction circuit for performing the calculation; and a syndrome calculation circuit for performing a syndrome calculation of a P correction sequence using the ECC parity in parallel with writing data to the memory. Also, the present invention provides a head unit for reading information recorded on a disk and generating a signal based on the information, a signal processing circuit for processing a signal generated by the head unit, and data supplied from the signal processing circuit. And a decoder for transferring the error-corrected data to the outside after executing the error correction processing described above, and the data from the signal processing circuit is written once, and the written data is accessed during the error correction processing by the decoder. A disk reproducing apparatus, comprising: a memory for performing a P-correction sequence syndrome calculation using ECC parity for error correction processing in parallel with writing data to the memory. . In other words, in the present invention, upon error correction and buffering processing on the decoding system side, syndrome calculation of a P correction sequence using ECC parity is performed in parallel with writing of data to a memory such as a buffer RAM. It is characterized by. With this configuration, according to the present invention, it is possible to execute error correction processing with high error detection capability using ECC parity while shortening the time required for access for error correction.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the ECC of the present invention.
FIG. 2 is a block diagram showing a CD-ROM system as a disk reproducing device including a circuit. In FIG. 1, a disk motor 10 drives an optical disk 11 to rotate. The pickup 12 and the RF amplifier 13 correspond to a head that reads information recorded on the optical disk 11 and generates an RF signal based on the information. That is, pickup 1
2 irradiates a pit row on the optical disk 11 with a light beam from a built-in semiconductor laser, detects a reflected beam with a built-in photodiode, and converts the obtained reproduced signal into an R signal.
It is supplied to the F amplifier 13. The reproduction signal is equalized in waveform by the RF amplifier 13 and is generated as an RF signal. Then RF
The signal is supplied to a signal processing circuit 14 and a servo circuit 15 of a pickup system. The signal processing circuit 14 includes a data slicer, a PLL, a synchronization signal separation circuit, an error correction processing circuit, and the like. The data signal that has undergone the error correction processing on the player side is sent to the decoder 20 on the decoding system side. The signal processing circuit 14 may be integrated with the servo circuit 15 as shown in FIG. 1 to form a DSP (disk servo processor) 100.

[0009] The decoder 20 includes a block 200 as an ECC circuit.
Reference numeral 00 includes a syndrome calculation circuit 201 and an error correction circuit 202. A system controller 26 composed of a microcomputer or the like controls the signal processing circuit 14 and the servo circuit 15 on the player side, and also supplies a control signal to the decoder 20 on the decoding system side. After the data sent to the decoding system is input to the decoder 20, the data is buffered in a buffer RAM (memory) 25 via an interface circuit (I / F) 204 composed of, for example, a FIFO buffer, and is then stored in a disk. The data is transferred at high speed to the host computer 27 outside the drive mechanism. When a disk on which digital audio data is recorded is reproduced, data is sent to an audio D / A converter (DAC) 28 to reproduce an audio signal. In the present invention, the buffer R
The decoding system is controlled so that the syndrome calculation circuit 201 performs the syndrome calculation of the P correction sequence in parallel with the writing of the data to the AM 25.
The error correction circuit 202 corrects data written in the buffer RAM 25 with reference to the result of the syndrome calculation. At this time, the buffer RAM 25 is used after being divided into two storage areas so as to simultaneously support access from the decoder 20 for error correction to written data and writing of data sent from the player side. Is done.
The buffer RAM 25 is not limited to this, and may have three or more storage areas.

FIG. 2 is a schematic diagram showing the objects to be processed in the two storage areas of the buffer RAM over time. FIG. 2 also shows the progress of the error correction processing on the data sent to the decoding system. As shown in FIG. 2, for example, when an error correction process for data of n-1 sectors is performed on the first surface, buffer transfer (writing) of data for n sectors is performed on the second surface.
Is performed. After the error correction on the first surface is completed and the error correction data is transferred to the outside, input of data of the next sector is started. Buffer transfer of data is performed, and error correction processing of data of n sectors is performed on the second surface. In this system, when data is sent from the player side to the system decoder side, in parallel with the buffer transfer of data to any storage area of the buffer RAM, the P correction is performed in the syndrome calculation circuit in the decoder in the order of data input. A series syndrome calculation is performed. That is, as shown in FIG. 2, during a period in which data of n sectors is buffer-transferred to the second surface of the buffer RAM, data of n sectors is transferred to the P in the decoder.
It is also used for syndrome calculation of the correction sequence. Thereafter, similarly, during a period in which the buffer transfer of the data of the (n + 1) th sector is performed to the first surface of the buffer RAM, n
The data of the +1 sector is used for the syndrome calculation of the P correction sequence in the decoder, and during the buffer transfer of the data of the n + 2 sector to the second surface of the buffer RAM, the data of the n + 2 sector is converted to the P correction sequence in the decoder. Provided for syndrome calculations.

In other words, in the present invention, after data is written to the buffer RAM, the buffer RA
When the error correction process is executed by accessing M, the syndrome calculation of the P correction sequence has already been completed, and if the syndrome calculation requires P correction, the error location of the P correction sequence is first calculated. Then, the error data may be corrected. Therefore, at the time of error correction processing within each period shown in FIG. 2, at least the time required for the syndrome calculation of the first P correction sequence and the end of error correction can be shortened by the amount that the buffer access for the calculation is not required. ECC processing speed is increased. Depending on the data, P correction and Q correction may be repeated a plurality of times when correcting an error in a specific sector. At this time, in the second and subsequent P corrections, the error correction circuit accesses the buffer RAM to access the P correction sequence. In FIG. 2, only the first P correction and Q correction are shown for convenience. Here, for comparison with the present invention, FIG. 3 shows the progress of the error correction processing in the conventional system. As shown in FIG. 3, conventionally, after data is written to the buffer RAM (buffer-transferred), both the P-correction sequence and the Q-correction sequence always undergo error calculation through calculation of error locations (not shown) from syndrome calculation as necessary. Even data correction is performed, and it takes a long time for error correction processing in each period. For this reason, especially when high-rate data transfer is requested, the time for transferring the error-corrected data after the error correction ends becomes insufficient, and the transfer of the error-corrected data to the outside (host transfer) is not completed. Then, the next data is sent from the player side, and the operation of the decoding system may be broken.

On the other hand, in the present invention, the time for the error correction processing in each period shown in FIG.
If the shortened portion is used for transferring the error correction data to the outside, the next data is sent before the error correction data is transferred to the outside, and the error correction data is overwritten and destroyed. It can be effectively avoided. Therefore, it is possible to construct a decoding system which can sufficiently cope with further high-rate data transfer. Note that the error correction of the P correction sequence and the Q correction sequence in each of the hatched periods in the drawing can be further omitted depending on the syndrome calculation result of each correction sequence. Next, referring to FIG. 4, the above-described error correction processing will be specifically described in comparison with the format of a CD-ROM. FIG. 4 shows each format defined by the CD-ROM.
The data structure of one sector is shown. As shown in the figure, the format of the CD-ROM is from mode 0 to mode 2, and the format to which the correction code is added is mode 1 and mode 2 form 1. Therefore, the format modes of mode 1 and mode 2 form 1 will be representatively described below. The sync (SYNC) indicates the head of the block, and is provided with 12 bytes in the area. Header (H
EADER) and subheader (SUBHEADER)
Is a data area having position and mode form information. In the case of mode 2 form 1, these are provided with 4 bytes and 8 bytes, respectively. Next, an area for user data (USERDATA) having user information is provided by 2048 bytes. Subsequently, the area of the error detection code EDC is provided by 4 bytes, and the area of the ECC parity which is a code for error correction is provided by 276 bytes. The ECC parity is divided into P parity 172 bytes and Q parity 104 bytes.

In mode 1, the subheader (SUBHEADER) area is not provided.
It has an unused data area (digital 0) of 8 bytes. ECC in Mode 1 and Mode 2 Form 1
The arrows of (P) and ECC (Q) indicate the range of the syndrome calculation of the P correction sequence and the range of the syndrome calculation of the Q correction sequence, respectively. As described above, the format of the CD-ROM to which the correction code is added is mode 1 and mode 2 form 1, in other words, the CD-RO
In the M format, error correction is performed in mode 1 and mode 2 form 1. Here, first, the procedure of syndrome calculation in mode 1 is conceptually shown in FIG. In the error correction algorithm of the mode 1 of the CD-ROM, 2340 bytes (d) obtained by removing 12 bytes of the synchronization pattern from 2352 bytes of data of one sector.
_{0 to} d ₂₃₃₉ ) are 1170 bytes each of an even-numbered input data array (e _{0 to} e ₁₁₆₉ ) and an odd-numbered input data array (f _{0 to} f ₁₁₆₉ ) as shown in FIG. , And thereafter, error correction processing is executed simultaneously on the two surfaces. The syndrome calculation for error correction is performed in the same manner for both surfaces.

FIG. 5B shows each of these two surfaces 1170.
FIG. 3 shows a conceptual diagram of a data array for each data configuration. Header (HEADER), user data (USERDATA) and unused data area (digital
Data data, including 0), 24 bytes (u ₀ ~u ₂₃₎
It is composed of a data array of × 43 columns. For this data array, a code for error correction of a Reed-Solomon code defined by a Galois field (Galois field) GF (2 ⁸ ) in two directions of a P correction sequence and a Q correction sequence, ie, P parity and Q parity is arranged. FIG.
In (b), the direction in which two syndrome calculations of a P correction sequence and a Q correction sequence are performed on such data is as follows.
Indicated by arrows. As shown, the P parity has 2 bytes (u ₂₄ , u ₂₅ ) × 43 columns of data, and after all, the above-mentioned 24 bytes (u _{0 to} u ₂₃ ) × 43 columns of data and the P parity The syndrome calculation of the P correction sequence is performed on the data of 26 × 43 bytes including the array part of. Here, the syndrome of the P correction sequence is represented by the following equations (1) and (2). Here, α is the root of the Galois field. S0 = the _{u 0 + u 1 + ... +} u 24 + u 25 ... (1) S1 = α 25 u 0 + α 24 u 1 + ... + αu 24 + u 25 ... (2) FIG. 6, the syndrome calculation circuit shown in FIG. 1 A specific configuration will be described. This syndrome calculation circuit is a circuit for performing syndrome calculation of a P correction sequence in mode 1, and sequentially calculates input data according to the above equations (1) and (2).

That is, in FIG. 6, an S0 syndrome calculation circuit 301 for calculating S0 of 43 columns of the P correction sequence is:
It is composed of an EX-OR 303 as an adder, 43 shift registers 304 on the front stage side, and 43 shift registers 305 on the rear stage side. The first-stage shift register 304 is controlled by the output signal of the 43-base counter 306, and the second-stage shift register 305
It is controlled by the output signal of the octal counter 307. These 43-base counter 306 and 1118-base counter 307
Is supplied with a clock signal CLK. The 43-ary counter 306 outputs a high-level signal while counting, for example, 43 clock signals CLK, and outputs a low-level signal each time 43 clocks have been counted. Also 11
The octal counter 307 outputs the clock signal CLK to 111
A high-level signal is output while counting eight, and 11
A low level signal is output every time the count of 18 is completed. The S1 syndrome calculation circuit 302 that calculates S1 of the 43 columns of the P correction sequence includes an EX-OR 308 as an adder.
And 43 shift registers 309 and a multiplier 3
10 and 43 shift registers 311 on the subsequent stage. The previous-stage shift register 309
The shift register 311 on the subsequent stage is controlled by the output signal of the 43-ary counter 306 and the 1118-base counter 30
7 is controlled by the output signal.

FIG. 6 shows only a circuit for calculating the syndromes of S0 and S1 for the data e _{0 to} e ₁₁₁₇ on the LSB byte side shown in FIG. However, actually, the data f _{0 to} f on the MSB byte side shown in FIG.
Similarly, for _1117, it is necessary to calculate the syndromes of S0 and S1. Therefore, two circuits shown in FIG. 6 are required, and a total of 43 × 2 × 2 × 2 = 344 registers are required. In such a syndrome calculation circuit, when calculating the syndrome of S0, based on the signal output from the 43-base counter 306, the input data e ₀
To e ₄₂ are supplied to the shift register 304 is latched. Next, the data e _{0 to} e ₄₂ latched by the shift register 304 and the input data e _{43 to} e ₈₅ are EX-OR3
03 and are latched in the shift register 304, respectively. These operations are repeated, and when the input of the P parity data e ₁₀₇₅ to e ₁₁₁₇ is completed, the syndromes of S0 satisfying the above equation (1) are calculated for 43 columns. The syndrome of S0 calculated here is 111
The data is supplied to and latched by 43 shift registers 305 controlled by the output signal of the octal counter 307. That is, while the data of the next sector is sent to the system decoder side and is written into the buffer RAM and is calculated by the syndrome calculation circuit, the data of the immediately preceding sector which is the subject of error correction processing is The syndrome calculation result continues to be held by the shift register 305 at the subsequent stage.

When calculating the syndrome of S1,
As in the case of S0, the output from the 43-base counter 306 is
Based on the input signal e₀~ E₄₂Shift
The data is supplied to the register 309 and latched. Next, shift
Data e latched in the register 309₀~ E₄₂Is
Multiplied by α by multiplier 310 and supplied to EX-OR 308
And input data e₄₃~ E₈₅And then added
The result is latched in the shift register 309, respectively.
These operations are repeated to obtain P parity data e. ₁₀₇₅From
e₁₁₁₇When the input up to is completed, the above equation (2) is satisfied.
The syndrome of S1 is calculated for 43 columns. This calculation
The syndrome of S1 is also the 1118 base counter 30
43 shift registers controlled by the output signal of 7
311 and latches while the error correction process is executed.
Is touched. Further, FIG.
Syndrome meter that calculates syndrome of P correction sequence
3 shows an arithmetic circuit. As shown in FIG.
Header 2 (HEA)
2336 bytes (d)₀~
d_Three= 0, so e₀= E₁= F₀= F₁= 0)
It is subject to error correction.

The calculation of the syndrome of S0 is performed in the mode 1
Calculation results and data e₀, E₁, F ₀, F₁Each
Data, and finally latch the data from the calculation result of mode 1.
Ta e ₀, E₁, F₀, F₁Subtract one of
Thus, the syndrome can be calculated. About this reason
This will be described below. E of the above equation (1)₀, E₁To
When “0” is substituted, the following equations (3) and (4) are obtained.
You. 0th row S0₀= 0 + e₄₃+ ... + e₁₀₃₂+ E₁₀₇₅ = E₄₃+ ... + e₁₀₃₂+ E₁₀₇₅ … (3) First row S0₁= 0 + e₄₄+ ... + e₁₀₃₃+ E₁₀₇₆ = E₄₄+ ... + e₁₀₃₃+ E₁₀₇₆ ... (4) On the other hand, from the calculation result of mode 1, e₀, E₁Difference minus
The minutes are represented by the following equations (5) and (6). 0th row S0₀= E₀-E₀+ E₄₃+ ... + e₁₀₃₂+ E₁₀₇₅ = E₄₃+ ... + e₁₀₃₂+ E₁₀₇₅ … (5) First row S0₁= E₁-E₁+ E₄₄+ ... + e₁₀₃₃+ E₁₀₇₆ = E₄₄+ ... + e₁₀₃₃+ E₁₀₇₆ (6) That is, Expression (3) = (5) and Expression (4) = (6).
Thus, it is proved that the equations (5) and (6) are correct. Ma
Data f₀, F₁Can be proved in the same way
So, the syndrome of S0 in mode 2 form 1
Can be calculated.

The calculation of the syndrome in S1 is based on the same reason.
Yields α^{twenty five}e₀, Α^{twenty five}e₁, Α ^{twenty five}f₀, Α^{twenty five}f₁
Latch the calculation result of
Then subtract the calculated result. That is,
E of (2)₀, E₁Substituting “0” into
(7) and (8). 0th row S1₀= Α^{twenty five}× 0 + α^{twenty four}e₄₃+ ... + αe₁₀₃₂+ E₁₀₇₅ = Α^{twenty four}e₄₃+ ... + αe₁₀₃₂+ E₁₀₇₅ … (7) First row S1₁= Α^{twenty five}× 0 + α^{twenty four}e₄₄+ ... + αe₁₀₃₃+ E₁₀₇₆ = Α^{twenty four}e₄₄+ ... + αe₁₀₃₃+ E₁₀₇₆ (8) On the other hand, from the calculation result of mode 1, α^{twenty five}e₀, Α^{twenty five}e₁To
The subtracted difference is as shown in the following equations (9) and (10). 0th row S1₀= Α^{twenty five}e₀−α^{twenty five}e₀+ Α^{twenty four}e₄₃+ ... + αe₁₀₃₂+ E_{107 Five} = Α^{twenty four}e₄₃+ ... + αe₁₀₃₂+ E₁₀₇₅ … (9) First row S1₁= Α^{twenty five}e₁−α^{twenty five}e₁+ Α^{twenty four}e₄₄+ ... + αe₁₀₃₃+ E_{107 6} = Α^{twenty four}e₄₄+ ... + αe₁₀₃₃+ E₁₀₇₆ (10) Therefore, Expression (7) = (9) and Expression (8) = (10).
Thus, it is proved that Expressions (9) and (10) are correct. Ma
Data f₀, F₁Can be proved in the same way
So, the syndrome of S1 in mode 2 form 1
Can be calculated.

The syndrome calculation circuit for calculating the syndrome of the P correction sequence in the mode 2 form 1 shown in FIG. 7 sequentially converts the input data based on the above equations (5), (6), (9) and (10). It is to calculate. More specifically, the syndrome calculation circuit includes a P correction sequence 43
S0 syndrome calculation circuit 401 for calculating S0 of a column
And an S1 syndrome calculation circuit 402 for calculating S1 of 43 columns of the P correction sequence. Furthermore, P
The S0 syndrome calculation circuit 401 for calculating S0 of the 43 columns of the correction sequence includes an EX-OR 403 as an adder, 43 shift registers 404 on the front stage, and two sets of shift registers 405 and 406 on the rear stage. Shift registers 405 and 406 and corresponding subtracters 407,
408, 41 shift registers 409 for latching the calculation results of the second to 42th columns, and the calculation result S of the 0th column
A shift register 410 for latching 0 _0, it is more configuration as the shift register 411 for latching the first column of the calculation result S0 _1. One shift register 4 on the subsequent stage
05 latches data e ₀ , and the other shift register 406 latches data e ₁ . One subtractor 40
7 subtracts the data e ₀ latched in one of the shift register 405 of the rear stage from S0 ₀ calculation result of the mode 1 output from the first-stage shift register 404, the other of the subtractor 408 is mode 1 S0 _The data e ₁ latched in the other shift register 406 at the subsequent stage is subtracted from _one calculation result.

The 43-ary counter 412 receives the clock signal CL
K is counted 43 times, and the 1118 decimal counter 413 counts 1118 clock signals CLK. The preceding shift register 404 is controlled by the output signal of the 43-ary counter 412. The detection circuit (DET ₀ ) 414 is constituted by, for example, a decoder, and includes a 1118-base counter 4
Twelve output signals are decoded to detect "0". The detection circuit (DET ₁ ) 415 is composed of, for example, a decoder, and decodes the output signal of the 1118 decimal counter 412 to detect “1”. The output signal of the detection circuit 414 is supplied to one shift register 405 on the subsequent stage,
The output signal of the second shift register 406
Supplied to Furthermore the final stage, each mode 1 of the calculation result, the shift register latches the calculation result S0 ₁ 0 column of calculation results S0 ₀ and 1 row 409,41
0 and 411 are controlled by the output signal of the 1118 base counter 412. The S1 syndrome calculation circuit 402 for calculating S1 of the 43 columns of the P correction sequence includes an EX-OR 416 as an adder, 43 shift registers 417 on the preceding stage, two sets of multipliers 418 and 419, and And two sets of shift registers 420 and 421 on the subsequent stage for latching the output data of the multiplier 419, and subtracters 422 and 42 corresponding to the shift registers 420 and 421, respectively.
3 and 41 to latch the calculation results from the second column to the 42nd column
Shift registers 424 and the calculation result S1 of the 0th column
A shift register 425 for latching the _0, it is more configuration as the shift register 426 for latching the first column of the calculation result S1 _1.

One multiplier 419 multiplies the output data of the previous-stage shift register 417 by α ²⁵ , and the other multiplier 419 multiplies the output data by α ^25.
Numeral 18 multiplies the output data of the previous-stage shift register 417 by α times. One shift register 420 at the subsequent stage latches output data α ²⁵ e ₀ of one multiplier 419,
The other shift register 421 latches the output data α ²⁵ e ₁ of the multiplier 419. One subtractor 422 is
Mode 1 output from shift register 417 at the previous stage
From S1 ₀ computed by subtracting the data alpha ²⁵ e ₀ latched in one of the shift register 420 of the second-stage, the other of the subtractor 423 and the other shift register 421 from S1 ₁ calculation result of the second-stage mode 1 subtracting the latched data α ²⁵ e _1. Shift register 417 on the previous stage
Is controlled by the output signal of the 43-ary counter 412.
One of the shift registers 420 at the subsequent stage includes the detection circuit 41
4, and the other shift register 421 on the subsequent stage is controlled by the output signal of the detection circuit 415. Further, in the final stage, the calculation result of the mode 1, the calculation result S10 of the _0th column, and the calculation result S
Shift registers 409, 410, 4 for latching 1 ₁
11 is controlled by the output signal of the 1118 base counter 412.

FIG. 7 shows only a circuit for calculating the syndromes of S0 and S1 for the data e _{0 to} e ₁₁₁₇ on the LSB byte side shown in FIG. However, actually, the data f _{0 to} f on the MSB byte side shown in FIG.
Similarly, for _1117, it is necessary to calculate the syndromes of S0 and S1. Therefore, two circuits shown in FIG. 7 are required. In such a syndrome calculation circuit, S
When calculating the syndrome of 0, the 43-ary counter 412
Input data e _{0 to} e ₄₂ based on the signal output from
Is supplied to the shift register 404 and latched. Next, the data e ₀ latched by the shift register 404
To e ₄₂ and the input data e ₄₃ to e ₈₅ are added by the EX-OR403, it is latched into the shift register 404. At this time, when the detection circuit 414 decodes the output signal of the 1118 base counter 412 and detects “0”, the shift register 405 latches the data e ₀ according to the output signal of the detection circuit 114. When the detection circuit 415 decodes the output signal of the 1118 base counter 412 and detects “1”, the shift register 406 latches the data e ₁ according to the output signal of the detection circuit 115.

The calculation result of mode 1 is obtained by adding all the input data. The input data is repeatedly added by the EX-OR 403 and the shift register 404, and when the input of the P parity data e ₁₀₇₅ to e ₁₁₁₇ is completed, the syndrome of S0 is calculated for 43 columns. Subtractor 407, the data e ₀ latched from the calculation results S0 ₀ to the shift register 405 in this case by subtracting, subtractor 408 subtracts the calculation result data e ₁ latched in the shift register 406 from S0 ₁ .
Of the syndromes of S0 calculated in this manner, the 0th column and the 1st column are latched by shift registers 410 and 411 controlled by the output signal of the 1118 base counter 413, and the other 41 bytes are the 1118 base counter 413.
Is latched by the shift register 409 in response to the output signal. On the other hand, when calculating the syndromes S1, as in the case of S0, based on the signal output from the 43-ary counter 412, the input data e ₀ to e ₄₂ are supplied to the shift register 417 is latched. Next, the data e _{0 to} e ₄₂ latched by the shift register 417 are
After being multiplied by α by 18 and supplied to the EX-OR 416 and added to the input data e _{43 to} e ₈₅ , the addition result is latched in the shift register 417. At this time, when the detection circuit 414 decodes the output signal of the 1118 base counter 412 and detects “0”, the detection circuit 11
In response to the output signal of No. 4, the shift register 420 latches the data α ²⁵ e ₀ multiplied by α ²⁵ by the multiplier 419. Further, the detection circuit 415 has a 1118 base counter 412
When the output signal is decoded to detect “1”, the shift register 421 latches the data α ²⁵ e ₁ multiplied by α ²⁵ by the multiplier 419 according to the output signal of the detection circuit 115.

EX-OR 416 and shift register 417
, The input data is repeatedly added, and when the input of P parity data e ₁₀₇₅ to e ₁₁₁₇ is completed, S1
Are calculated for 43 columns. Subtractor 422
The shift register 420 from the calculation result S1 ₀ here
Is subtracted from the data α ²⁵ e ₀ latched by
Subtracts the latched from the calculation result S1 ₁ in the shift register 421 data α ²⁵ e _1. Of the syndromes of S1 calculated in this way, the 0th and 1st columns are 1
The other 41 bytes are latched by the shift register 424 in accordance with the output signal of the 1118 base counter 413, while the other 41 bytes are latched in the shift registers 425 and 426 controlled by the output signal of the 118 base counter 413. The error correction circuit 202 shown in FIG.
1 and calculates the error location based on the calculation result of step 1.
P correction for the error data in. However, when the syndrome calculation result of the P correction sequence based on the above equations (1) and (2) is 0 in all 43 columns and it is found that there is no error in each column, the error correction circuit 202 It is also possible to omit the (first) P correction and perform an algorithm based on the syndrome calculation of the Q correction sequence. As described above, in the mode 1, the calculation result of the syndrome calculation circuit 201 is the shift register 305 in the S0 syndrome calculation circuit 301 and the S1 syndrome calculation circuit 3
02 is latched in the shift register 311 in the S0 syndrome calculation circuit 40 in the mode 2 form 1.
1 shift registers 409, 410, 411 and S
Shift register 42 in one syndrome calculation circuit 402
4, 425 and 426 are latched.

Further, the error correction circuit 202 accesses the data written in the buffer RAM 25 thereafter, calculates the syndrome of the Q correction sequence based on the following equations (11) and (12), and calculates the error location if necessary. And correction of error data. Here, if the error correction is performed due to the need for the Q correction as a result of the syndrome calculation of the Q correction sequence, the data after the error correction is again provided to the syndrome calculation of the P correction sequence. In this case, the error correction circuit 202
It is necessary to perform the syndrome calculation of the P correction sequence while accessing the data in the AM 25. S0 = u ₀ + u ₁ +... + U ₄₃ + u ₄₄ (11) S1 = α ⁴⁴ u ₀ + α ⁴³ u ₁ +... + Α u ₄₃ + u ₄₄ (12) In the system described above, the buffer RAM 2 is used.
Since the syndrome calculation of the P correction sequence is in progress at the same time as the writing of the data to the P.5, the error correction circuit 202 executes the error correction processing, and the error correction processing does not involve access to the buffer RAM 25 for the P correction sequence. Can be calculated immediately. Therefore, the time required for the error correction processing can be shortened, and even when the reproduction speed of the disk is increased, it is possible to transfer data to the external host computer 27 with a margin.

FIG. 8 is a block diagram showing another example of a CD-ROM system as a disk reproducing apparatus including the ECC circuit of the present invention. As is clear from FIG. 8, in this example, the data is written in the block 200 of the ECC circuit in the decoder 20 of the decoding system based on the result of the syndrome calculation using the ECC parity in parallel with the writing of the data to the buffer RAM 25. The difference from the system shown in FIG. 1 is that an error detection circuit 300 for performing the error detection is provided. Here, when there is no error in the data for each sector sent from the player side, the P correction sequence is calculated by the two syndrome calculations of the P correction sequence and the Q correction sequence indicated by arrows in FIG. Of all 43
The error detection circuit 300 determines the presence or absence of an error in the data by utilizing that all the 26 columns of the column and the Q correction sequence become 0. That is, the error detection circuit 300 calculates the total sum of the syndromes of the P correction sequence and the Q correction sequence based on the above equations (1), (2), (11), and (12) in the input order of the data sent from the player side. When the total is zero, it is determined that no error data is included in the sector, and the flag FRG is output to the system controller 26. A specific example of the error detection circuit 300 is shown in FIGS. 5 and 10 of Japanese Patent Application No. 10-56924 filed by the present applicant.

In the system shown in FIG. 8, when the error detection circuit 300 determines that there is an error in the data written in the buffer RAM 25, the error correction circuit 202 controls the P correction sequence under the control of the system controller 26. Of error locations and correction of error data, and calculation of syndromes of Q correction sequences or correction of error data. On the other hand, the error detection circuit 30
If the result of calculation based on 0 is 0 for both the P correction sequence and the Q correction sequence and it is determined that there is no error, the decoder 2
0 transfers the data written in the buffer RAM 25 to the host computer 27 as it is. When the error detection circuit 300 determines that only the sum of the syndromes of the P correction sequence is 0, the error correction circuit 20
The system configuration may be such that the Q correction is performed on Q2. Alternatively, when the error detection circuit 300 determines that there is an error in the data, and when the syndrome calculation result of the P correction sequence by the syndrome calculation circuit 201 is 0 in all 43 columns, the system shown in FIG. Similarly to the above, the error correction circuit 202 may omit the first (first) P correction, and first calculate the syndrome of the Q correction sequence, calculate the error location based on the result, and correct the error data. Good.

According to such a system, when the error detection circuit 300 determines that there is no error in the data, the error correction circuit 202 does not execute the error correction processing, so that the data is transferred to the external host computer 27 at high speed. it can. In particular, when cached data is transferred to the host in a non-real-time manner, it is possible to prevent performance degradation due to useless error correction. FIG. 9 shows a CD-R as a disk reproducing apparatus including the ECC circuit of the present invention.
FIG. 4 shows a block diagram of yet another example of the OM system. In this example, as an error detection circuit, in addition to the circuit that performs error detection using ECC parity as described above, ED
A circuit for performing error detection using C or IPF is also used. That is, the ECC error detection unit 21 in FIG. 9 calculates the total sum of the syndromes of the P-correction sequence and the Q-correction sequence in the order of inputting the data, and determines whether the total sum of these is 0 or not in the data. This is to determine whether there is an error. As the ECC error detecting section 21, for example, the circuits shown in FIGS. 5 and 10 of Japanese Patent Application No. 10-56924 can be used as in the case of the CD-ROM system shown in FIG. Next, the EDC error detection unit 22 detects an EDC (error detection code) included in data output from the signal processing circuit 14. That is, the EDC error detector 22 calculates the following equation (13).
Is calculated to detect the presence or absence of an error in the data.

P (x) = (x ¹⁶ + x ¹⁵ + x ² + x) (x ¹⁶ + x ² + x + 1) (13) The IPF error detection unit 23 detects an error during signal processing by the signal processing circuit 14. In this case, an IPF (for example, a C2 correction flag, a C2 correction impossible flag, a correction flag, or the like) added to the data by the signal processing circuit 14 is detected. The IPF has, for example, one bit added to 1-byte data. The IPF error detector 23 counts the number of IPFs in one sector, and if this count value is “0”, no error occurs. Judge. The ECC error detection unit 21, the EDC error detection unit 22, and the IPF error detection unit 23 output the flags FRG1, FRG2, and FRG3 based on the error detection results to the system controller 26 in response to a request from the system controller 26. I do. The system controller 26 determines these flags FRG1, FRG2, FRG
According to 3, it is determined whether or not error correction is necessary. If correction is required, the error correction circuit 202 of the decoder 20 is activated. If there is no need for error correction, the buffer R
The decoder 20 is instructed to transfer the data written in the AM 25 to the host computer 27 as it is.

In the system shown in FIG. 9, when the error detection circuit 300 determines that there is no error in the data, the error correction processing is omitted, so that the data can be transferred to the external host computer 27 at high speed. It becomes possible. Moreover, the error detection circuit 300 can improve the error detection accuracy by using the error detection results of the ECC error detection unit 21, the EDC error detection unit 22, and the IPF error detection unit 23 in combination.

[0032]

As described in detail above, according to the present invention, it is possible to provide an ECC circuit which has a high error detection capability and improves the processing speed of ECC.
By using the circuit, further high-speed disk playback,
It is possible to realize a highly reliable disk reproducing device that can sufficiently follow high-rate data transfer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a CD-ROM system as a disk reproducing apparatus including an ECC circuit of the present invention.

FIG. 2 is a schematic diagram showing an object to be processed in two storage areas of a buffer RAM over time.

FIG. 3 is a diagram showing a progress state of an error correction process in a conventional system.

FIG. 4 is a diagram showing each format defined in a CD-ROM.

FIG. 5 is a diagram conceptually showing a procedure of syndrome calculation in a mode 1;

FIG. 6 is a diagram illustrating a syndrome calculation circuit that performs syndrome calculation of a P correction sequence in mode 1;

FIG. 7 is a diagram showing a syndrome calculation circuit that performs syndrome calculation of a P correction sequence in mode 2 form 1;

FIG. 8 is a block diagram showing another example of a CD-ROM system as a disk reproducing device including the ECC circuit of the present invention.

FIG. 9 is a block diagram showing still another example of a CD-ROM system as a disc reproducing apparatus including the ECC circuit of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Optical disk 12 ... Pickup 13 ... RF amplifier 14 ... Signal processing circuit 20 ... Decoder 25 ... Buffer RAM 200 ... ECC circuit block 201, 301, 302, 401, 402 ... Syndrome calculation circuit 202 ... Error correction circuit 300 ... Error detection circuit

Claims (5)

[Claims] 1. An error correction circuit for performing error correction on data including ECC parity for error correction processing sent from a player side of a disc into a decoding system and written into a memory, and writing data to the memory. A syndrome calculation circuit for performing a syndrome calculation of the P correction sequence using the ECC parity in parallel. 2. An ECC circuit, further comprising an error detection circuit for detecting an error in the data based on a result of a syndrome calculation using the ECC parity in parallel with writing data to the memory. 3. A head section for reading information recorded on a disc and generating a signal based on the information, a signal processing circuit for processing a signal generated by the head section, and data supplied from the signal processing circuit. And a decoder for transferring the error-corrected data to the outside after executing the error correction processing described above, and the data from the signal processing circuit is written once, and the written data is accessed during the error correction processing by the decoder. A disk reproducing apparatus including a memory for performing a P-correction sequence syndrome using an ECC parity for error correction processing in parallel with writing data to the memory. A disk reproducing apparatus characterized by the above-mentioned. 4. The apparatus according to claim 3, wherein said decoder performs error detection of said data based on a result of a syndrome calculation using said ECC parity in parallel with writing of data to said memory. Disc playback device. 5. When the decoder detects an error in the data and determines that there is no error in the data,
5. The disk reproducing apparatus according to claim 4, wherein the data written in the memory is transferred to the outside as it is.