JP2001067864A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the scattering or deviation of the parallel interface operation timing of a plurality of interface circuits. SOLUTION: A plurality of interface circuits to be interfaced to the outside in parallel are divided into a plurality of groups OAL and OAR, and a timing signal for controlling an interface operation is supplied in series from a timing control line W6 in group units. The difference (skew) of the propagation delay of the timing signal between the base and end edges of timing control wiring can be reduced as compared with a case where a plurality of interface circuits used for parallel interface to the outside are not divided into groups and are bound at one point for supplying the timing signal in series with common timing control wiring, thus reducing the skew of the timing signal for each group.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an interface means for interfacing a plurality of bits of information with the outside in parallel, and more particularly to a timing for defining a plurality of bits of signals which are interfaced in parallel by the interface means. Regarding the technology to suppress the deviation, for example,
SDRAM (Synchronous Dynami) that can operate DDR (Double Data Rate)
c Random Access Memory).

[0002]

2. Description of the Related Art The operation timing of a synchronous memory such as an SDRAM is controlled based on an external clock signal such as an external system clock signal. This type of synchronous memory is characterized in that the setting of internal operation timing is relatively easy by using an external clock signal, and relatively high-speed operation is possible.

For example, as an SDRAM, a so-called SDR (Single Data Ra) in which data input and output are performed in synchronization with a rising edge of an external clock signal.
te) type SDRAM (SDR-SDRAM), and a so-called DDR type SDRAM in which data input and output are performed in synchronization with both rising and falling edges of an external clock signal or a data strobe signal
(DDR-SDRAM) is known.

As an example of a document describing such an SDRAM, there is a 64 Meg DDR-SDRAM.
JEDDDRDS. pm65-Rev. 7/5/99
JEDEC (Joint Electron Devi)
There is a data sheet of "ce Engineering Council".

A clock synchronous memory typified by an SDRAM has an output timing control circuit such as a latch circuit for determining data output timing in a data output circuit, and an input timing for a latch circuit or the like for determining data input timing. A control circuit is included in the data input circuit. For example, in a data input circuit of an SDRAM, a data input buffer inputs data supplied in synchronization with an external clock signal or a data strobe signal, and the input data is latched by an input data latch circuit and transmitted to a subsequent stage. To go. The latch operation of the input data latch circuit is controlled by an internal timing signal (input latch timing signal) synchronized with the external clock signal or data strobe signal. The data output circuit of the SDRAM latches data to be output by an output latch timing signal generated internally in synchronization with an external clock signal, and outputs the data from the output buffer to the outside. The DDR-SDRAM outputs a data strobe signal in synchronization with the output latch timing signal together with the data output.

The data input circuit and the data output circuit are generally arranged along the arrangement of external data terminals such as bonding pads and bump electrodes on the semiconductor chip and in the vicinity thereof. In such a layout, the output timing signals are serially transmitted to the output timing control circuits of the data output circuits arranged in parallel along the external data terminals, and are arranged in parallel along the external data terminals. An input timing signal is sequentially propagated serially to each input timing control circuit of the data input circuit.

[0007]

SUMMARY OF THE INVENTION The present inventor has studied the difference between the output latch timing and the input latch timing at the base end and the end of the timing control wiring through which the timing signal is serially propagated.

First, since the output latch timing is shifted between the base end and the end of the timing control wiring through which the output timing signal is propagated, the time range in which the output data is valid or determined is sequentially shifted at each data terminal. Go. For this reason, the time range (output data valid window) in which the output data of all the data terminals performing the parallel data output are all valid or determined is a common divisor range for each valid time range of the output data. It becomes narrower as the deviation of the output latch timing between the base end and the end of the control wiring increases. If the output data valid window is relatively narrow with respect to the respective valid time ranges of the output data, the time margin for receiving the read data of the SDRAM decreases, and
In a data processing system using a DRAM, timing design becomes difficult, and it is impossible to cope with an increase in operation speed.

Similarly, since the input latch timing is shifted between the base end and the end of the timing control wiring through which the input timing signal is propagated, the input circuit can latch the input data supplied in parallel to each data terminal. Time ranges shift sequentially. For this reason, the time range (input data valid window) for validating or determining all the bits of the input data to be supplied in parallel to all the data terminals corresponds to the valid time range in which each input circuit can latch the input data. It becomes a common multiple time range, and becomes wider as the shift of the input latch timing between the base end and the end of the timing control wiring increases. If the input data valid window is relatively wide relative to the valid time range in which each input circuit can latch the input data, the setup and hold time of the input data cannot be made relatively large, and the operation speed can be increased. become unable.

Considering the above problem from a layout point of view, when the pairs of input circuits and output circuits are alternately arranged in correspondence with the arrangement of the data terminals, the timing control wiring through which the input timing signal is propagated. As a result, the input data valid window tends to be relatively wide, and the output data valid window tends to be relatively narrow, as a result of the fact that the timing control wiring for transmitting the output timing signal is laid along the arrangement of the input circuit and the output circuit. It has been found that it tends to be noticeable. In particular, since the DDR-SDRAM has a data rate twice that of the SDR-SDRAM even if the operation clock frequency is the same, it is indispensable to cope with an increase in the speed of the input data valid window and the output data valid window.

It is clear from the present inventors that the sizes of the input data valid window and the output data valid window depend not only on the length or the time constant of the timing control wiring but also on the configuration of the latch circuit. Was. That is, assuming a latch circuit including an input gate formed of a first clocked inverter and a static latch having a second clocked inverter activated in a phase opposite to that of the first clocked inverter, When a clock signal and a clock signal obtained by inverting the clock signal by an inverter are used for the activation control of both clocked inverters, the first clocked inverter of the input gate changes from the inactive state to the active state, In a transient response state until the clocked inverter of FIG. 1 transitions from the active state to the inactive state, a change in input may not be reflected on the output. Such a transient response condition causes the input data valid window to be undesirably wide and the output data valid window to be undesirably narrow.

An object of the present invention is to provide a semiconductor device capable of reducing variation or deviation of data input timing in a plurality of data input circuits to which data is supplied in parallel. Another object of the present invention is to provide a semiconductor device capable of narrowing an input data valid window.

Another object of the present invention is to provide a semiconductor device capable of reducing variation or deviation of data output timing in a plurality of data output circuits that output data in parallel. Further, the present invention provides
An object of the present invention is to provide a semiconductor device capable of increasing an output data valid window.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] A first aspect of the present invention focuses on reducing the skew of timing signals for interface operation of interface circuits operated in parallel on timing control wiring.

That is, the semiconductor device has a plurality of interface terminals for interfacing a plurality of bits of information in parallel with the outside, and a plurality of interface circuits provided corresponding to each of the plurality of interface terminals. , In a semiconductor chip, the plurality of interface circuits are arranged in a plurality of groups, and a timing control wiring for supplying a timing signal for controlling an interface operation in series to each group of interface circuits in a group unit. Are connected.

According to the above, a plurality of interface circuits used for a parallel interface with the outside are grouped without grouping and a timing control wiring is supplied in series with a common timing control wiring. The difference (skew) in the propagation delay of the timing signal between the base end and the end can be reduced. In other words, the variation in data input timing in a plurality of data input circuits to which data is input in parallel and the variation in data output timing in a plurality of data output circuits to output data in parallel are determined by the group. Can be distributed every time. In short, it is possible to reduce the skew of the timing signal for each group. As a result, it is possible to reduce the input data valid window as compared with the case where no grouping is performed, and it is possible to increase the output data valid window.

The more the interface circuits of each group are collectively arranged for each group, the smaller the difference in the propagation delay of the timing signal between the base end and the end of the timing control wiring in the group. In other words, the skew of the timing signal within the group is reduced.

The interface terminal includes a data terminal, and the interface circuit includes a data output circuit connected to the data terminal. Further, the interface circuit includes a data input circuit connected to the data terminal. For example, the data terminal is a data input / output terminal that is also used for data input and output, and each data terminal is coupled on one side to the input terminal of the data input circuit and on the other side to the output terminal of the data output circuit. .

The layout of the groups of circuits operated in parallel interface can be symmetrical or asymmetrical about the base end of the control wiring. In the case of asymmetry, the skew of the timing signal between the groups can be reduced. A driver having a driver at a base end of the timing control wiring for each group may be connected to a timing control line having a relatively large load.

When the interface circuit includes a buffer circuit connected to a corresponding interface terminal, and a latch circuit connected to the corresponding buffer circuit and performing a latch operation of information to be interfaced, the timing signal is It is a latch control signal of the latch circuit. In the case of an input circuit, for example, data supplied in synchronization with a change in a data strobe signal is input to a buffer circuit, and is latched in a latch circuit in response to the latch control signal in synchronization with a change in the data strobe signal. Is transmitted to In the case of an output circuit, for example, data to be output obtained by an internal operation is latched by a data latch circuit by a latch control signal synchronized with an external clock signal, and output to the outside through an output buffer.

In addition to the means for reducing the skew of the timing signal, an interface signal wiring connecting the buffer circuit and the interface terminal has at least substantially equal delay components (time constants) in each of the groups. With this setting, it is possible to easily reduce a situation in which the input data valid window and the output data valid window are adversely affected by variations in delay due to interface signal wiring. Here, setting the same delay component means to match the delay time of the route requiring the longest delay time.

Assuming application to an SDRAM, the semiconductor device further includes a plurality of memory cells for storing data input from the data terminal and enabling the stored data to be output from the data terminal. In the data read operation, data read from a memory cell selected from the plurality of memory cells is latched by a latch circuit of the data output circuit and provided to the data terminal. Then, in the data write operation, data latched from the plurality of data terminals to the latch circuit of the data input circuit is written to a memory cell selected from the plurality of memory cells.

In particular, when the semiconductor device is applied to a DDR type SDRAM, the semiconductor device outputs a data strobe signal in synchronization with a timing signal for latching the latch circuit of the output circuit in response to a data read operation, and performs a data write operation. An external signal terminal for inputting a data strobe signal for synchronizing a timing signal for latching the latch circuit of the input circuit in response to an operation is further provided as the interface terminal.

[2] A second aspect of the present invention focuses on a transient response operation by a clocked inverter constituting a latch circuit on an interface circuit operated in parallel.

That is, focusing on a plurality of input circuits arranged on a semiconductor chip, each input circuit has an input buffer and an input latch circuit connected thereto, and the input latch circuit is connected to the input buffer. Input gate and a static latch connected to the input gate. The input gate is activated and controlled in response to a complementary clock signal whose edge change timing is aligned.
The static latch includes a second clocked inverter that receives the complementary clock signal and is activated and controlled in a phase opposite to that of the first clocked inverter.

According to the above, since the complementary clock signal having the same edge change timing is used, both the first and second clocked inverters are deactivated due to the shift of the edge change timing. The transient response period is shortened, and the period during which a change in the input is not reflected in the output during such a transient response period can be shortened. This allows
This helps to prevent the input data valid window from undesirably expanding.

Focusing on a plurality of output circuits arranged on a semiconductor chip, each output circuit includes an output latch circuit and an output buffer connected thereto, and the output latch circuit includes an input gate and the input gate. And a static latch whose output is connected to the output buffer. At this time, the input gate includes a clocked inverter that is activated and controlled by receiving a complementary clock signal whose edge change timing is aligned.

According to the above, since the complementary clock signal having the same edge change timing is used, the transient response period in which the clocked inverter is changed from the inactive state to the active state is shortened, and the output data valid window is thereby reduced. This is useful for suppressing an undesired narrowing.

The complementary clock signal having the aligned edge change timing may be formed by a signal generation circuit on a semiconductor chip. The signal generation circuit includes a pair of differential amplifier circuits, and a clock terminal is commonly connected to one of the pair of differential amplifier circuits having different polarities, and the pair of differential amplifier circuits is A reference voltage terminal is connected to the other differential input terminal having a different polarity from each other, and a complementary clock signal having the same edge change timing is output from an output node having the same polarity of the pair of differential amplifier circuits. is there.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Outline of DDR-SDRAM FIG. 1 shows a DDR-SDRAM as an example of a semiconductor device according to the present invention.
A DRAM is shown. DDR-SDRA shown in FIG.
M is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a known MOS semiconductor integrated circuit manufacturing technique.

The DDR-SDRAM 1 has, although not particularly limited, four memory banks BNK0 to BNK3. Although not shown, each of the memory banks BNK0 to BNK0
Although not particularly limited, the BNK 3 has four memory mats, and each memory mat is constituted by two memory arrays. One memory array is allocated to a data storage area where the least significant bit of the column address signal corresponds to a logical value "0", and the other memory array is a data storage area where the least significant bit of the column address signal corresponds to a logical value "1". Allocated to storage area. The memory mats of the memory banks and the divisional structure of the memory array are not limited to the above, and therefore, in this specification, unless otherwise specified, each memory bank is configured as a single memory mat. explain.

The respective memory banks BNK0 to BNK
3 has dynamic memory cells MC arranged in a matrix. According to the drawing, the selection terminals of the memory cells MC arranged in the same column are connected to the word line W for each column.
L, and the data input / output terminals of the memory cells arranged in the same row are coupled to one of the complementary bit lines BL, BL for each row. Although only a part of the word line WL and the complementary bit line BL is shown as a representative in the figure, a large number of word lines WL and complementary bit lines BL are actually arranged in a matrix and have a folded bit line structure centered on a sense amplifier. I have.

For each of the memory banks BNK0 to BNK3, row decoders RDEC0 to RDEC3, data input / output circuits DIO0 to DIO3, and column decoder CDEC0
To CDEC3.

The word line WL of the memory mat is selected and driven to a selected level in accordance with a result of decoding of a row address signal by row decoders RDEC0 to RDEC3 provided for each of the memory banks BNK0 to BNK3.

The data input / output circuits DIO0-DIO3
Has a sense amplifier, a column selection circuit, and a write amplifier. The sense amplifier is an amplifier circuit that detects and amplifies a small potential difference appearing on each of the complementary bit lines BL, BL by reading data from the memory cell MC. The column selection circuit is a switch circuit for selecting the complementary bit lines BL and BL to conduct to the input / output bus 2 such as a complementary common data line. The column selection circuit is selectively operated according to the result of decoding of the column address signal by the corresponding one of the column decoders CDEC0 to CDEC3. The write amplifier is a circuit that differentially amplifies the complementary bit lines BL, BL via a column switch circuit according to write data.

A data input circuit 3 and a data output circuit 4 are connected to the input / output bus 2. The data input circuit 3 inputs write data supplied from the outside in the write mode and transmits the write data to the input / output bus 2. The data output circuit 4 inputs the read data transmitted from the memory cell MC to the input / output bus 2 in the read mode and outputs the read data to the outside. An input terminal of the data input circuit 3 and an output terminal of the data output circuit 4 are coupled to, but not limited to, 16-bit data input / output terminals DQ0 to DQ15. For convenience, data that the SDRAM 1 inputs / outputs from / to the outside may be described with reference characters DQ0 to DQ15.

Although not particularly limited, the DDR-SDRAM 1 has 15-bit address input terminals A0 to A14. Address input terminals A0 to A14 are coupled to address buffer 5. Of the address information supplied to the address buffer 5 in a multiplex form, the row address signals AX0 to AX12 are supplied to the row address latch 6, the column address signals AY0 to AY11 are supplied to the column address latch 7, and the bank regarded as a bank selection signal. The select signals AX13 and AX14 are supplied to the bank selector 8, and the mode register setting information A0 to A14 are supplied to the mode register 9.

The operation of the four memory banks BNK0 to BNK3 is selected by the bank selector 8 according to the logical values of the 2-bit bank selection signals AX13 and AX14. That is, only the memory bank whose operation has been selected is enabled for memory operation. For example, a sense amplifier, a write amplifier, a column decoder, and the like are not activated in a memory bank whose operation is not selected.

The row address signals AX0 to AX12 latched by the row address latch 6 are supplied to row address decoders RDEC0 to RDEC3.

The column address signals AY0 to AY11 latched by the column address latch 7 are preset in the column address counter 10 and supplied to the column address decoders CDEC0 to CDEC3. When a burst access, which is a continuous memory access, is instructed, the column address counter 10 is incremented by the number of consecutive times (the number of bursts), and a column address signal is generated internally.

The refresh counter 11 is an address counter that generates a row address for refreshing stored information. When a refresh operation is instructed, word line WL is selected in accordance with a row address signal output from refresh counter 11, and stored information is refreshed.

The control circuit 12 includes, but is not limited to, the clock signals CLK and CLKb, the clock enable signal CKE, and the chip select signal CSb (the suffix b is a low enable signal or a level inversion signal. ), Column address strobe signal CASb, row address strobe signal RA
Predetermined information is input from the mode register 9 together with external control signals such as Sb, a write enable signal WEb, data mask signals DMU and DML, and a data strobe signal DQS. The operation of the DDR-SDRAM 1 is determined by a command defined by a combination of the states of the input signals, and the control circuit 12 has control logic for forming an internal timing signal according to the operation specified by the command.

The clock signals CLK and CLKb are SDRA
The master clock is M and other external input signals are made significant in synchronization with the rising edge of the clock signal CLK.

The chip select signal CSb indicates the start of a command input cycle by its low level. When the chip select signal is at a high level (chip unselected state), other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state.

Each of the signals RASb, CASb, and WEb has a function different from that of a corresponding signal in a normal DRAM, and is a significant signal when defining a command cycle described later.

The clock enable signal CKE is a control signal for the power-down mode and the self-refresh mode. When the power-down mode (which is also the data retention mode in the SDRAM) is set, the clock enable signal CKE is at a low level.

The data mask signals DMU and DML are mask data in units of bytes with respect to the input write data. The high level of the data mask signal DMU instructs the suppression of writing by the upper byte of the write data, and the high level of the data mask signal DML. Indicates that writing is inhibited by the lower byte of the writing data.

The data strobe signal DQS is externally supplied as a write strobe signal during a write operation. That is, when a write operation is instructed in synchronization with the clock signal CLK, supply of data synchronized with the data strobe signal DQS from a clock signal cycle after the clock signal cycle in which the write operation is performed is specified. .
During a read operation, the data strobe signal DQS is output to the outside as a read strobe signal. That is,
In a data read operation, a data strobe signal changes in synchronization with an external output of read data. Therefore, a DLL (Delayed Lock Loop) circuit 1
3 and a DQS output buffer 14 are provided. DL
L circuit 13 receives clock signal CL received by semiconductor device 1.
K and a data output operation control clock signal (data strobe signal DQS at the time of read operation) in order to synchronize the data output timing by data output circuit 4 with K.
And the phase of the control clock signal) 15 which is in phase with the control clock signal. The DLL circuit 13 includes, but is not limited to, an internal clock signal 15 capable of compensating a signal propagation delay time characteristic of an internal circuit by using a replica circuit technique and a phase synchronization technique.
Thus, the data output circuit 4 that is operated to output based on the internal clock signal 15 can output data at a timing reliably synchronized with the external clock signal CLK. The DQS buffer 14 has a data strobe signal DQS in phase with the internal clock signal 15.
Is output to the outside.

The row address signals (AX0 to AX1)
2) is defined by the levels of the address input terminals A0 to A12 in a later-described row address strobe / bank active command (active command) cycle synchronized with the rising edge of the clock signal CLK. In this active command cycle, the signal AX1 input from the address input terminals A13 and A14
3, AX14 are regarded as bank selection signals, and A13 = A
When 14 = “0”, the banks BNK0 and A13 =
When "1" and A14 = "0", banks BNK1 and A1
When 3 = "0" and A14 = "1", the bank BNK2,
When A13 = "1" and A14 = "1", bank BNK
3 is selected. The memory bank selected in this way is subjected to data read by a read command, data write by a write command, and precharge by a precharge command.

The column address signals (AY0 to AY1)
1) Terminals A0 to A11 in a column address read command (read command) cycle and a column address write command (write command) cycle, which will be described later, synchronized with the rising edge of the clock signal CLK.
Is defined by the level of The designated column address is used as the start address of the burst access.

In the DDR-SDRAM 1, the clock signal CLK, the inverted clock signal CLKb, the clock enable signal CKE, the chip select signal CSb, the RAS signal RASb, the CAS signal CASb, the write enable signal WEb, and the address input are not particularly limited. Signals A0 to A14, data mask signals DMU, DML,
The interface of an input buffer receiving the data strobe signal DQS, a data input buffer (first input buffer) of the data input circuit 3, and a data output buffer (last output buffer) of the data output circuit 4 is, for example, a known SSTL2 (class II). Compliant with standards. SS
According to the TL2 standard, a reference potential (V
A level of 1.6 volts or more higher than REF) by 0.35 V or more is regarded as an H level, and a level of 0.35 V or less with respect to the reference potential, that is, a level of 0.90 volt or less is regarded as an L level. . The external interface specification is not limited to SSTL2, and may be, for example, the SSTL3 standard.

Although the DDR-SDRAM 1 is not particularly limited, the following [1]-

Commands such as [9] are defined in advance.

[1] The mode register set command is
This is a command for setting the mode register 9. This command is used for CSb, RASb, CASb, W
Data to be set (register set data) is specified by Eb = low level, and given via A0 to A14. The register set data is not particularly limited, but has a burst length, a CAS latency, a burst type, and the like. The configurable burst length is
Although not particularly limited, it is set to 2, 4, 8, and the configurable CAS latency is not particularly limited.
5 is assumed.

The above-mentioned CAS latency is determined by the data output circuit 4 from the fall of CASb in the read operation specified by a column address read command described later.
Specifies how many cycles of the clock signal CLK are to be consumed before the output operation. Until the read data is determined, an internal operation time for data read is required, and this is set in accordance with the operating frequency of the clock signal CLK. In other words, when using a clock signal CLK with a high frequency, the CAS latency is set to a relatively large value, and when using a clock signal CLK with a low frequency, the CAS latency is set to a relatively small value.

[2] The row address strobe / bank active command determines whether a row address strobe is
13 and A14 are commands for validating the memory bank selection. CSb, RASb = low level (“0”), CASb, WEb = high level (“1”).
At this time, addresses supplied to A0 to A12 are taken as row address signals, and signals supplied to A13 and A14 are taken in as memory bank selection signals. The capture operation is performed by the clock signal CL as described above.
This is performed in synchronization with the rising edge of K. For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

[3] The column address read command is a command necessary for starting the burst read operation and a command for giving a column address strobe instruction. CSb, CASb, = low level, RASb, WEb = Directed by high level,
At this time, the addresses supplied to A0 to A11 are captured as column address signals. The fetched column address signal is preset in the column address counter 10 as a burst start address.
In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is supplied with the clock signal CLK. In accordance with the address signal output from the column address counter 10 in synchronization with the data strobe signal DQS, the data is sequentially selected in the memory bank in units of 32 bits, and continuously externally in units of 16 bits in synchronization with the rise and fall of the data strobe signal DQS. Is output. The number of data (the number of words) read continuously is set to the number specified by the burst length. The start of data reading from the data output circuit 4 is determined by the above C
This is performed after waiting for the number of cycles of the clock signal CLK defined by the AS latency.

[4] The column address write command is a command necessary to start the burst write operation when the burst write is set in the mode register 9 as the mode of the write operation. Further, the command gives an instruction of a column address strobe in burst write. The command is CSb, C
ASb, WEb, = low level, RASb = high level. At this time, the addresses supplied to A0 to A11 are taken in as column address signals. The column address signal thus captured is supplied to the column address counter 10 as a burst start address in burst write. The procedure of the burst write operation instructed in this way is performed in the same manner as the burst read operation. However, there is no CAS latency setting in the write operation, and the capture of the write data is delayed by one cycle of the clock signal CLK from the column address / write command cycle.
Started in synchronization with QS.

[5] The precharge command is A13,
A command to start the precharge operation for the memory bank selected by A14 is issued, and CSb, RASb,
WEb, = low level, CASb = high level.

[6] The auto refresh command is a command required to start auto refresh, and CSb, RASb, CASb = low level,
Indicated by WEb, CKE = high level. The refresh operation by this is the same as the CBR refresh.

[7] When the self-refresh entry command is set, the self-refresh function operates while CKE is kept at the low level. During this time, a predetermined interval is automatically set even if no external refresh instruction is given. Performs a refresh operation.

[8] The burst stop command is a command necessary to stop the burst read operation, and is ignored in the burst write operation. This command is performed when CASb, WEb = low level, RASb, CAS
Indicated by b = high level.

[0064]

[9] The no operation command is a command for not performing a substantial operation,
Instructed by CSb = low level and RASb, CASb, WEb = high level.

In the DDR-SDRAM 1, when a burst operation is being performed in one memory bank, another memory bank is designated during the burst operation and a row address strobe / bank active command is supplied. The operation of the row address system in the other memory bank is enabled without affecting the operation in the other memory bank. That is, a row address operation specified by a bank active command or the like and a column address operation specified by a column address / write command or the like can be performed in parallel between different memory banks. Therefore, unless data collision occurs at the data input / output terminals DQ0 to DQ15,
During execution of a command whose processing has not been completed, a precharge command and a row address strobe / bank active command are issued to a memory bank different from the memory bank to be processed by the command being executed,
It is possible to start the internal operation in advance.

As is clear from the above description, DDR-
The SDRAM 1 can input and output data in synchronization with both rising and falling edges of the data strobe signal DQS in synchronization with the clock signal CLK, and can input and output addresses and control signals in synchronization with the clock signal CLK. It is possible to operate a large-capacity memory similar to that described above at a high speed comparable to that of an SRAM. In addition, by specifying how many data to access to one selected word line by burst length, A plurality of data can be read or written continuously by sequentially switching the selection state of the column system by the built-in column address counter 10.

<< Data Input Circuit >> FIG. 2 shows a DDR-SD
One example of the data input circuit 3 of the RAM 1 is shown. In the first stage, an input first stage buffer 20 of the SSTL specification is arranged.
The input first-stage buffer 20 receives the data strobe signal DQS
Write data supplied in synchronization with the rising edge and falling edge of is input. Input first stage buffer 20
Although not shown, has a current mirror load, a data terminal is connected to the gate of one differential input MOS transistor, a reference voltage is input to the gate of the other differential input MOS transistor, and an enable signal DIEN The active / inactive state is controlled via a power switch MOS transistor that is switch-controlled by the switch.

In the next stage of the differential input buffer 20, the serial path of the latch circuits 21A to 21C and the latch circuits 21D, 21D,
21E are connected in parallel, and when a write operation is instructed, the data supplied in half cycle units of the data strobe signal DQS is shifted by a half cycle, and the serial path of the latch circuits 21A to 21C, and the latch circuit 21D,
21E and serially latched. As a result, the write data supplied in half-cycle units of the data strobe signal DQS becomes the data strobe signal DQS.
And transmitted to the subsequent stage in units of one cycle. That is, each of the latch circuits 20A to 20E includes clocked inverters CIV1 and CIV2 and an inverter IV, and is latched and controlled by complementary clock signals DSCKT and DSCKB whose edge change timings are aligned. Each of the clocked inverters CIV1 and CIV2 is constituted by a series circuit of p-channel type MOS transistors Mp1 and Mp2 and n-channel type MOS transistors Mn3 and Mn4 as illustrated in FIG. DSCKT and DSCKB are supplied, and as illustrated in FIG.
21C and 21E perform a latch operation in synchronization with the fall of the clock signal DSCKB, and latch circuits 21B and 21E.
D performs a latch operation in synchronization with the fall of the clock signal DSCKT.

FIG. 5 shows the clock signals DSCKT, D
A generation circuit of the SCKB is exemplified. This signal generation circuit 2
2 is configured by mutually connecting input terminals having different polarities of a pair of differential amplifier circuits. That is, one differential amplifier circuit is composed of p-channel MOS transistors Mp11 and Mp11.
12, a n-channel type differential input MOS transistor Mn13, Mn14, and n
Channel type power switch MOS transistor Mn1
5 The gate of the MOS transistor Mn13 is an inverting input terminal, and the gate of the MOS transistor Mn14 is a non-inverting input terminal. The other differential amplifier circuit has a current mirror load composed of p-channel MOS transistors Mp21 and Mp22 and an n-channel differential input MO.
It comprises S transistors Mn23 and Mn24 and an n-channel power switch MOS transistor Mn25. The gate of the MOS transistor Mn23 is an inverting input terminal, and the gate of the MOS transistor Mn24 is a non-inverting input terminal.

The differential input MOS transistor Mn13
And the gate of Mn24 receive the data strobe signal DQS, and the gates of the differential input MOS transistors Mn14 and Mn23 receive the reference voltage VREF, so that the single-ended output nodes of the respective differential amplifier circuits Internal clock signals DSCLKT and DSCLKB of complementary levels to data strobe signal DQS can be obtained from connected CMOS inverters 51 and 52.

DSEN is an enable control signal for the signal generation circuit 22 and is supplied to the gates of the power switch MOS transistors Mn15 and MN25. The signal generation circuit 22 is activated by the high level of the enable control signal DSEN. In this active state, an operating current flows through the differential amplifier circuit, and a minute potential difference from the signal level of the terminal DQS is immediately amplified around the reference voltage VREF.
The signal input operation from the terminal DQS is fast due to the differential amplification.

As can be understood from the description of the data input circuit 3, in the DDR-SDRAM 1, write data is input from the outside in synchronization with both the rise and fall of the data strobe signal DQS in synchronization with the clock signal CLK. You. The write operation inside the DDR-SDRAM 1 is performed using the cycle of the clock signal CLK as a minimum unit.

Next, the latch circuit 21A shown in FIG. 6 will be described in detail as a latch circuit that is latched and controlled by a complementary clock signal having the same edge change timing. FIG. 7A shows that when the latch circuit 21A of FIG. 6 latches the data of the logical value "1", FIG.
(B) shows the operation timing when the latch circuit 21A latches the data of the logical value "0", respectively. As is clear from FIG. 7, the clock signal IT =
When 0 and IB = 1, the input operation of the clocked inverter CIV1 is enabled and the input operation of the clocked inverter CIV2 is disabled, so that the latch circuit 21A
Goes through. On the other hand, the clock signal IT = 1, I
When B = 0, the input operation of the clocked inverter CIV1 is disabled, and the input operation of the clocked inverter CIV2 is enabled, so that the latch circuit 21A enters the latch state.

7A and 7B, the latch circuit 21A transitions from the through state to the latch state at time t3. When input data D is inverted at time t0, the change is transmitted to output Q at time t1 (operation delay time td
1, td3) and reflected at the output of the inverter IV at time t2 (operation delay times td2, td4). Latch circuit 2
1A clock signals DSCKB, DSCKT (IT, I
In B), since the clock edges are aligned, a transient response period in which both the first and second clocked inverters CIV1 and CIV2 are deactivated due to a shift in edge change timing is substantially ignored. Short enough to be
As in the comparative example described below, there is substantially no period in which the change in the input is not reflected in the output during such a transient response period. Therefore, in both cases of latching “1” data and latching “0” data, the setup time may be considered at the same timing.

On the other hand, in the case of a latch circuit using clock signals IT and IB having different edge change timings as illustrated in FIG. 8, the through state is changed as shown in FIGS. 9A and 9B. When transitioning from
A transient response period of T = 1 and IB = 1 occurs. In this period, in the “1” data latch operation of (A), the change of the input D is reflected on the output Q even in the transient response period.
In the "0" data latch operation of (B), the change of the input D during the transient response period is not reflected on the output Q, and there is a possibility that the change will be missed. Therefore, in the case of (A), the setup time S1 is considered based on the time tI1 at which the latch state of the latch circuit is achieved, and in the case of (B), the time tI0 at which the change of the through state of the latch circuit is started is determined. The setup time S3 must be considered as a reference. In such a case, it is practically impossible to properly use the setup time in accordance with the logical value of the latch data, and the longer setup time must be adopted uniformly, resulting in high-speed operation. It becomes difficult to deal with. On the other hand, if a latch circuit using a complementary clock signal with uniform edge changes as described with reference to FIG. 6 is employed, it is easy to cope with a high-speed operation. FIG.
The same applies to the other latch circuits shown in FIG.

<< Data Output Circuit >> FIG. 10 shows the DDR-S
An example of the data output circuit 4 of the DRAM 1 is shown. During data read operation, data R
DAT and FDAT are read in parallel. This read operation is performed in cycle units in synchronization with the clock signal CLK. One data RDAT is stored in the latch circuit 30.
A, 30B, and the other data FDA
T is transmitted to the series path of the latch circuits 30C, 30D, and 30E. One final-stage latch circuit 30B is connected to an inverter 3 via an output gate 31A composed of a clocked inverter.
2 and reaches the output buffer 33. The other end-stage latch circuit 30E is connected to the inverter 32 via an output gate 31B formed of a clocked inverter and reaches the output buffer 33.

The latch circuits 30A and 30C latch the input in synchronization with the clock signal L1CK, and the latch circuit 30D
Is synchronized with the clock signal L2CK.
Latch the output of C. Clock signals L1CK, L2C
K is an internal clock signal generated based on the clock signals CLK and CLKb and synchronized with complementary clock signals ICKT and ICKB described later. Data RDAT and FDAT read in parallel from the memory bank in synchronization with the cycle of clock signal CLK are applied to clock signal CLK (I
CKT), and are latched by the latch circuits 30A and 30C, and the latch data FL1D of the latch circuit 30C is latched by the latch circuit 3 in synchronization with the clock signal CLKb (ICKB).
Latched to 0D.

The latch circuits 30A to 30D have the configuration shown in FIG.
It is possible to employ the master-slave logic exemplified in FIG. The master stage and the slave stage are respectively constituted by clocked inverters CIV1 and CIV2 and an inverter IV. Clocked inverter CIV1, CIV
2 has the circuit configuration of FIG.

The circuit for generating the clock signals ICKT and ICKB has the same configuration as the input buffer of the data strobe signal DQS in FIG. 5, as exemplified in FIG. However, the inverted clock signal CLKb is used instead of the reference voltage VREF. In FIG. 12, Mp16, M
p17, Mp26 and Mp27 are p-channel MOS transistors. Mn18, Mn19, Mn20, M
n28, Mn29 and Mn30 are n-channel MOS transistors. CKEN is an activation control signal.
The L1CK and L2CK are clock signals ICKT and IC
The clock signal is synchronized with the KB.

The latch circuit 30B shown in FIG.
30E is constituted by clocked inverters CIV1 and CIN2 and an inverter IV, and outputs a clock signal L3C
In synchronization with KT and L3CKB, one of them is controlled to a through state and the other is controlled to a latch state. Output gate 3
1A and 31B are clock signals L3CKT and L3CKB
And the latch circuit 30B or 3 in the latched state
Those connected to the subsequent stage of 0E are enabled for output operation, and those connected to the subsequent stage of the latch circuit 30B or 30E in the through state are controlled to the high impedance state.

The clock signals L3CKT, L3CKB
Is a timing signal generated by the DLL circuit 13 performing a predetermined delay adjustment on the clock signals ICKT and ICKB as shown in FIG. This delay adjustment is performed by synchronizing the clock signals ICKT and ICKB with the output gates 31A and 31B alternately and outputting the data output timing appearing at the data terminal DQj via the inverter 32 and the output buffer 33 to the edge of the data strobe signal DQS. This is a process for setting a delay time necessary to synchronize with the change timing.

As illustrated in FIG. 13, the output buffer 33 has a CMOS inverter at the final stage using a power supply voltage VDDQ that conforms to the SSTL2 interface specification as an operation power supply. This CMOS inverter has a NAND gate N
Activation is controlled by an output enable signal DOEN via an AND and a NOR gate NOR.
When EN is at a high level, output operation is enabled in accordance with data DATA, and when output enable signal DOEN is at a low level, the output is controlled to a high output impedance state.

FIG. 14 illustrates the output operation timing of the output circuit of FIG. As can be understood from the description of the data output circuit 4, the internal data read operation of the DDR-SDRAM 1 is performed using the cycle of the clock signal CLK as a minimum unit, and the data read by this is output to the clock signal CLK. The data is output from the data terminal DQj in synchronization with both the rise and fall of the synchronized data strobe signal DQS.

Next, a detailed description will be given of the latch circuit 30B shown in FIG. 15 as a representative example of an output latch circuit that is latched and controlled by a complementary clock signal whose edge change timing is aligned. Locked inverter CIV of FIG.
1 and CIV2 have the same circuit configuration as FIG.

FIG. 16A shows the latch circuit 3 shown in FIG.
When 0B latches the data of logical value "1", FIG.
(B) shows the operation timing when the latch circuit 30B latches the data of the logical value "0", respectively. As apparent from FIG. 16, the clock signal OT
= 0 and OB = 1, the clocked inverter CIV1
Is disabled for input and the clocked inverter CIV
2 is enabled for input, whereby the latch circuit 30
B enters the latch state. On the other hand, the clock signal OT = 1,
When OB = 0, the clocked inverter CIV1 is enabled for input, and the clocked inverter CIV2 is disabled for input, whereby the latch circuit 30B enters a through state.

In FIGS. 16A and 16B, the latch circuit 30B transitions from the latch state to the through state at time t0. Data I has been determined before time t0. Therefore, when the latch circuit 30B is changed from the latched state to the through state at time t0, in the case of "1" data output, the output O is determined after the elapse of the operation delay time tdo1, and
In the case of "0" data output, the output O is determined after the elapse of the operation delay time tdo0. Since clock edges of the clock signals L3CKT and L3CKB (OT, OB) of the latch circuit 30B are aligned, the transient response period during which the first clocked inverter CIV1 is inactivated due to the shift of the edge change timing is set. It is substantially negligible, and there is substantially no period in which the change in the input is not reflected in the output during such a transient response period as in the comparative example described below. Therefore, output of "1" data,
In any case of output of “0” data, the output timing as viewed from t0 is the same.

On the other hand, in the case of a latch circuit using clock signals OT and OB having different edge change timings as illustrated in FIG. 17, the latch state is changed as shown in FIGS. A transition from IT to the through state causes a transient response period of IT = 1 and IB = 1. In this period, in the “0” data output operation of FIG. However, in the “1” data latch operation of (A), the change in the data I during the transient response period is not reflected on the output O.
Therefore, the output timing based on the time t0 is “1”.
In the case of data output, tOd0 + tdo1,
In case of "0" data output, it becomes tdo0. As described above, when the output timing is different according to the logical value of the output data, the period during which all the bits output in parallel are all valid becomes shorter, and as a result, it becomes difficult to cope with high-speed operation. Would. In contrast, FIG.
If a latch circuit using a complementary clock signal with uniform edge changes as described above is employed, it is easy to cope with a high-speed operation. The same applies to other latch circuits shown in FIG.

<< Layout of Interface Circuit >> FIG.
9 shows a chip appearance of the DDR-SDRAM 1.
A large number of bonding pads 42 are arranged in a control system circuit area 41 allocated to the central portion of the semiconductor chip 40. A power supply system control circuit 43, an address system control circuit 44, a command system control circuit 45, an input / output control Circuit 46,
And a power supply system control circuit 47. Outside the control circuit area 41, the memory banks BNK0 to BN
K3 is formed. The power supply system control circuits 43 and 47 include circuits for forming a word line drive voltage, a substrate bias voltage, and the like based on the power supply voltage VDD and the like. The address system control circuit 44 includes the address latches 6, 7 and the column address counter 10. The command-related control circuit 45 controls the CSb, RASb, CASb, W
It includes logic for controlling the operation mode based on command signals such as Eb. The input / output control circuit 46 includes a signal input / output control circuit typified by the data input circuit 3 and the data output circuit 4. The large number of bonding pads 42 are classified into an address system, a command system, and a data system, and are arranged collectively.

FIG. 20 illustrates the external appearance of the package of the DDR-SDRAM 1, in particular, the arrangement of external connection terminals such as lead pins of the package. Pins indicated by NC in FIG. 20 are unused terminals. In the figure, the data strobe signal is shown separately for DQSU and DQSL. Although the description so far has been made with the data strobe signal DQS as a representative, in practice, the upper byte data terminals DQ15 to DQ8 and the lower byte data terminals DQ7 to DQ7
This is because different data strobe signals are assigned to DQ0. Data terminals DQ15 to DQ10
Are also written as DQF to DQA.

FIG. 21 shows a specific layout configuration of the input / output control circuit 46. The corresponding external terminal name such as DQ0 is added to the bonding pad 42.

The input / output control circuit 46 includes data strobe signal output circuits QSU and QSL formed in the unit area L1 as interface circuits, and data output circuits O8, O7, O9, O6, OA and O5 formed in the unit area L2. ,
OB column (data output circuit column OAL), mask data input circuits MU, ML formed in unit area L3, and data input circuits I8, I7, I9, I formed in unit area L4.
6, IA, I5, IB (data input circuit row IA
L), data strobe signal input circuits DSU, DSL formed in unit area L5, and data input circuits I4, IC, I3, ID, I2, IE, I formed in unit area L4.
1, IF, I0 column (data input circuit column IAR), data output circuits O4, OC, O formed in unit area L2.
3, OD, O2, OE, O1, OF, and O0 (data output circuit array OAR).

The data output circuit and the data input circuit are commonly connected to corresponding data terminals. For example, data output circuit O0 is connected to corresponding data terminal DQ0 by data wiring W5, and data input circuit I0 is connected to corresponding data terminal DQ0 by data wiring W4.
The data strobe signal output circuit and the data strobe signal input circuit are also connected to the corresponding data strobe terminals. For example, the data strobe signal output circuit QSU connects the wiring W2 to the corresponding data strobe terminal DQSU.
And the data strobe signal input circuit DSU is connected to the corresponding data strobe terminal DQSU by the wiring W3.
Connected by In FIG. 21, the mask data input circuit M
U is connected to the corresponding terminal DMU by a wiring W1. Other circuits whose wirings are not shown are also connected to corresponding terminals.

Although not particularly shown, the W for connecting the data output circuit and the data input circuit to the corresponding data terminals is not shown.
5. Regarding the interface signal wiring such as W4, at least the interface signal wiring in the group of the interface circuits such as the data output circuit rows and the data input circuit rows is adjusted to the delay time of the path requiring the longest delay time. If a common delay component (time constant) is set, it is possible to easily reduce a situation in which the input data valid window and the output data valid window are adversely affected by the delay variation due to the interface signal wiring.

The unit area L2 includes the unit bit configuration of the data output circuit 4 shown in FIG. At this time, the final output stage buffer 33 may be arranged near the corresponding bonding pad 42. The unit storage area L
4 includes the configuration of the unit bit of the data input circuit 3 shown in FIG. At this time, the first-stage buffer 20 may be arranged near the corresponding bonding pad 42. The unit storage area L5 includes the configuration of the unit bits of the input buffer 22 shown in FIG.

As is clear from the arrangement of the interface circuit in FIG. 21, the data output circuit for performing data output in parallel is divided into left and right into two data output circuit rows OAL and OAR, and the data input circuit for performing data input in parallel. The circuit is divided into left and right parts into data input circuit rows IAL and IAR.

W7 shown along the data input circuit rows IAL and IAR applies the timing signals DSCKT and DSCKB (see FIG. 2) to the input circuits formed in the respective unit areas L4 sequentially and serially. This is the timing control wiring to be transmitted. Timing signals DSCKT and DSCKB (see FIG. 2) are transmitted from one side to the left and right timing control lines W7 via the clock driver B2.
FIG. 22 shows a portion of the data input circuit rows IAL and IAR extracted.

FIG. 23 shows data input circuit rows IAL and IA.
The data input operation timing by R is shown. After passing through the clock driver B2, the timing control signals DSCKT and DSCKB have different propagation delays on the timing control wiring W7 between the far end and the near end of the clock driver B2. In order that each data input circuit can secure necessary setup time ts1 and hold time ht1 with respect to a change point of timing control signals DSCKT and DSCKB which are respectively propagated, it is necessary to set up all input circuits. Input data valid window tiw1, which is a time range including time and hold time
, At least the parallel input data must be determined. At this time, the data input circuit row is IA
L and IAR are divided into two and the data input circuit rows IAL, IA
Since the timing control signals DSCKT and DSCKB are propagated for each R, and the individual data input circuits are intensively arranged adjacent to the data input circuit rows IAL and IAR.
The input data valid window tiw1 is compared with a case where the data input circuit column is not divided or a case where the data input circuit is sequentially arranged adjacent to the data output circuit.
Time range becomes narrower.

FIG. 26 shows, as a comparative example, a layout in which the data input circuit rows are not divided as described above, and the data input circuits in the area L4 are sequentially arranged adjacent to the data output circuits in the area L2. In this case, as is clear from FIG. 27 in which the portion of the data input circuit row is extracted, the timing control wiring W7 becomes longer. Therefore, FIG. 2 shows the data input operation timing of the data input circuit row.
As shown in FIG. 8, the propagation delay at the far end and near end of the clock driver B2 on the timing control wiring W7 increases, and accordingly, the time range of the input data valid window tiw2 also increases.

Therefore, by adopting the layout of FIG. 21, the input data valid window is reduced, and it is easy to cope with an increase in the operation speed of the DDR-SDRAM 1.

In FIG. 21, data output circuit row OA
W6 shown along L and OAR is a timing control wiring for sequentially transmitting the timing signals L3CKT and L3CKB (see FIG. 10) to output circuits formed in the respective unit areas L2 in series. . Timing signals L3CKT and L3CKB are transmitted from one side to the left and right timing control lines W6 via the clock driver B1. FIG. 24 shows only the data output circuit rows OAL and OAR. Data output circuit row OA
The path lengths for transmitting the timing signals L3CKT and L3CKB to the respective clock drivers B1 for L and OAR are different. The driver CD1 assigned to the wiring LN1 having a longer propagation path is set to have a larger driving capability than the driver CD2 assigned to the wiring LN2 having a shorter propagation path, and has a larger driving signal L3CKT and L3CKB supplied to the respective clock drivers B1. Skew does not occur.

FIG. 25 shows a data output circuit row OAL, OA
The data output operation timing by R is shown. The timing control signals L3CKT and L3CKB are transmitted through the line LN.
1 and LN2, there is a difference in signal propagation delay, and after passing through the clock driver B1, the timing control wiring W6
There is a difference in signal propagation delay between the far end and the near end of the clock driver B1 above. In FIG. 25, the difference between the delay times is represented by tcd0, tcd1, tcd2, and tcd3. Output data appears at the data terminal after a lapse of time to2 with respect to a change point of the timing control signals L3CKT and L3CKB propagated to the respective data output circuits. The time range in which the output data from the data output circuit is determined at all the data terminals is the time range of the output data valid window tow1. At this time, the data output circuit row is divided into OAL and OAR, and the timing control signal L3CK is provided for each of the data output circuit rows OAL and OAR.
T, L3CKB is propagated, and the data output circuit row OA
Since individual data output circuits are concentrated and arranged adjacent to each other in L and OAR, compared to a case where the data output circuit columns are not divided or a case where the data output circuits are sequentially arranged adjacent to the data input circuits. , The time range of the output data valid window tow1 is widened.

FIG. 26 shows, as a comparative example, a layout in which the data output circuit rows are not divided as described above and the data input circuits in the area L4 are sequentially arranged adjacent to the data output circuits in the area L2. In this case, as is apparent from FIG. 29 in which a portion of the data output circuit row is extracted, the timing control wiring W6 becomes longer. Therefore,
As is clear from FIG. 30 showing the data output operation timing of the data output circuit row, the timing control wiring W6
In addition, the propagation delay at the far end and near end of the clock driver B1 increases, and accordingly, the time range of the output data valid window tow2 also narrows.

Therefore, by adopting the layout of FIG. 21, the output data valid window is widened, and it is easy to cope with an increase in the operation speed of the DDR-SDRAM 1.

FIGS. 31 to 38 illustrate another layout configuration such as a data input circuit row and a data output circuit row. As shown in FIG. 31, the data output circuit rows OAL and OAR may be arranged at the center of the area of the input / output control circuit 46. As shown in FIG. 32, the clock drivers B1 of the data output circuit rows OAL and OAR may be arranged at the center. FIG.
3. As shown in FIG. 34, the data input circuit columns IAL and IAR
May be adjacent to each other, and the data output circuit rows OAL and OAR may be adjacent to each other. 35 and 36, in the area of the input / output control circuit 46, the data output circuit rows 100 to 104 and the data input circuit row 1
05 to 108 can also be arranged separately in the upper and lower areas. Further, as shown in FIG. 37, the data output circuit row OAL and the data input circuit row IAL are adjacent to each other,
The data output circuit row OAR and the data input circuit row IAR may be adjacent to each other. Similarly, as illustrated in FIG. 38, the data output circuit row OAL and the data input circuit row IALa may be adjacent to each other, and the data output circuit row OAR and the data input circuit row IARa may be adjacent to each other.

The invention made by the present inventor has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the grouping of the interface circuits that are operated in parallel output operation or parallel input operation is not limited to the above-described division into two, and may be more.
The number of data input / output terminals of the SDRAM is not limited to 16 bits, but may be 8 bits, 4 bits, or the like. Also,
The number of memory banks of the SDRAM, the memory mats of the memory banks, and the configurations of the memory arrays are not limited to those described above, and can be appropriately changed.

Further, the data output circuit and the data input circuit constituting the interface circuit are not limited to the above configuration. When the interface circuit includes a buffer circuit and a latch circuit, the buffer circuit and the latch circuit may be arranged separately. In this case, at least the latch circuits are to be grouped.

In the above description, the invention made mainly by the present inventor is based on the DDR which
-The present invention is not limited thereto, but the present invention is not limited thereto. Semiconductors called on-chip microcomputers such as SRAMs, DDR-SDRAMs, and the like, microcomputers, system LSIs, accelerators, and the like. It can be widely applied to equipment.

[0109]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of interface circuits interfaced with the outside in parallel are divided into a plurality of groups, and a timing signal for controlling the interface operation is serially supplied to the interface circuits of each group from a timing control line in units of groups. Since a plurality of interface circuits used for a parallel interface with the outside are not grouped but are grouped together and a timing signal is serially supplied through a common timing control wiring,
The difference (skew) in the propagation delay of the timing signal between the base end and the end of the timing control wiring can be reduced. As a result, variations in data input timing in a plurality of data input circuits to which data is input in parallel, and variations in data output timing in a plurality of data output circuits to output data in parallel, Can be distributed. In short, it is possible to reduce the skew of the timing signal for each group.
As a result, it is possible to reduce the input data valid window as compared with the case where no grouping is performed, and it is possible to increase the output data valid window.

The more the interface circuits of each group are collectively arranged for each group, the smaller the difference between the propagation delay of the timing signal at the base end and the end of the timing control wiring in the group becomes, and Skew can be reduced.

The activation and deactivation of the clocked inverters constituting the latch circuit on the interface circuit operated in parallel are controlled using complementary clock signals whose edge change timings are aligned. By adopting such a clocked inverter for the input stage and the latch stage of the data input latch circuit, a transient response period in which both clocked inverters are inactivated due to a shift in edge change timing. Can be shortened, and the period during which a change in the input is not reflected on the output during such a transient response period can be shortened. As a result, it is possible to suppress a situation where the input data valid window undesirably widens.

If the clocked inverter is used as the input gate of the data output latch circuit, a complementary clock signal having the same edge change timing is used.
The transient response period in which the clocked inverter is changed from the inactive state to the active state is shortened, thereby making it possible to suppress a situation where the output data valid window is undesirably narrowed.

[Brief description of the drawings]

FIG. 1 illustrates a DDR- which is an example of a semiconductor device according to the present invention.
It is a block diagram of SDRAM.

FIG. 2 is a circuit diagram illustrating an example of a data input circuit of the DDR-SDRAM.

FIG. 3 is a circuit diagram illustrating a clocked inverter.

FIG. 4 is a timing chart illustrating an operation timing of the data input circuit;

FIG. 5 is a circuit diagram illustrating a circuit for generating clock signals DSCKT and DSCKB;

FIG. 6 is a circuit diagram illustrating an input latch circuit that is latched and controlled by a complementary clock signal whose edge change timing is aligned.

7A shows an operation when the latch circuit of FIG. 6 latches data of logical value “1”, and FIG. 7A shows an operation when the latch circuit of FIG. 6 latches data of logical value “0”. B)
3 is a timing chart shown in FIG.

FIG. 8 shows clock signals I having different edge change timings.
FIG. 9 is a circuit diagram showing a latch circuit using T and IB as a comparative example.

9A shows an operation when the latch circuit of FIG. 8 latches data of logical value “1”, and FIG. 9A shows an operation when the latch circuit of FIG. 8 latches data of logical value “0”. B)
3 is a timing chart shown in FIG.

FIG. 10 is a circuit diagram showing an example of a data output circuit of the DDR-SDRAM.

FIG. 11 is a circuit diagram illustrating a master / slave latch circuit included in the data output circuit;

FIG. 12 is a circuit diagram illustrating a circuit for generating clock signals ICKT and ICKB.

FIG. 13 is a logic circuit diagram illustrating an output buffer of the data output circuit.

FIG. 14 is a timing chart showing the output operation timing of the data output circuit.

FIG. 15 is a circuit diagram illustrating an output latch circuit that is latched and controlled by a complementary clock signal whose edge change timing is aligned.

16A shows an operation when the latch circuit of FIG. 15 latches data of a logical value “1”, and FIG. 16A shows an operation when the latch circuit of FIG. 15 latches data of a logical value “0”. 6B is a timing chart shown in each of FIGS.

FIG. 17 is an explanatory diagram showing, as a comparative example, a latch circuit using clock signals OT and OB having different edge change timings.

18A shows an operation when the latch circuit of FIG. 17 latches data of a logical value “1”, and FIG. 18A shows an operation when the latch circuit of FIG. 17 latches data of a logical value “0”. 6B is a timing chart shown in each of FIGS.

FIG. 19 is a plan view showing a chip appearance of the DDR-SDRAM 1;

FIG. 20 is a plan view illustrating an arrangement of external connection terminals such as lead pins of a package of the DDR-SDRAM 1;

FIG. 21 illustrates a first example of an input / output control circuit of a DDR-SDRAM.
FIG. 3 is a plan view illustrating the layout configuration of FIG.

FIG. 22 is an explanatory diagram extracting and showing a data input circuit column in FIG. 21;

FIG. 23 is a timing chart illustrating the data input operation timing by the data input circuit row in FIG. 22;

FIG. 24 is an explanatory diagram extracting and showing a data output circuit column in FIG. 21;

FIG. 25 is a timing chart illustrating the data output operation timing by the data output circuit row in FIG. 24;

FIG. 26 is a plan view illustrating, as a comparative example, a layout in which a data input circuit column is not divided and sequentially arranged adjacent to a data output circuit.

FIG. 27 is an explanatory diagram showing a data input circuit column portion extracted from FIG. 26;

FIG. 28 is a timing chart illustrating the data input operation timing of the data input circuit row in FIG. 27;

FIG. 29 is an explanatory drawing showing a data output circuit column in FIG. 26;

30 is a timing chart showing a data output operation timing of the data output circuit row in FIG. 29;

FIG. 31 shows a second example of the input / output control circuit of the DDR-SDRAM.
FIG. 3 is a plan view illustrating the layout configuration of FIG.

FIG. 32 shows a third input / output control circuit of the DDR-SDRAM.
FIG. 3 is a plan view illustrating the layout configuration of FIG.

FIG. 33 shows a fourth input / output control circuit of the DDR-SDRAM.
FIG. 3 is a plan view illustrating the layout configuration of FIG.

FIG. 34 shows a fifth input / output control circuit of the DDR-SDRAM;
FIG. 3 is a plan view illustrating the layout configuration of FIG.

FIG. 35 shows a sixth input / output control circuit of the DDR-SDRAM.
FIG. 3 is a plan view illustrating the layout configuration of FIG.

FIG. 36 shows a seventh input / output control circuit of the DDR-SDRAM;
FIG. 3 is a plan view illustrating the layout configuration of FIG.

FIG. 37 shows an eighth input / output control circuit of the DDR-SDRAM;
FIG. 3 is a plan view illustrating the layout configuration of FIG.

FIG. 38 shows a ninth input / output control circuit of the DDR-SDRAM.
FIG. 3 is a plan view illustrating the layout configuration of FIG.

[Explanation of symbols]

 1 DDR-SDRAM BNK0-BNK3 Memory bank MC Memory cell WL Word line BL Bit line DIO0-DIO3 Data input / output circuit RDEC0-RDEC3 Row decoder CDEC0-CDEC3 Column decoder 2 Input / output bus 3 Data input circuit 4 Data output circuit DQ0-DQ15 Data input / output terminals A0 to A14 Address input terminal 5 Address buffer 6 Row address latch 7 Column address latch 8 Bank selector 9 Mode register 10 Column address counter 12 Control circuit 20 Input first stage buffer 21A to 21E Latch circuit CLK, CLKb Clock signal DQS data Strobe signal CIV1, CIV2 Clocked inverter IV inverter DSCKT, DSCKB Complementary clock signal 30A-30E Circuit L3CKT, L3CKB complementary clock signal 33 output final stage buffer 41 control system circuit area 46 output control circuit OAL, OAR data output circuit array IAL, IAR data input circuit series W6, W7 timing control lines B1, B2 driver

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroki Miyashita 5-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. 5-20-1, Hitachi Semiconductor Co., Ltd. (72) Inventor Masashi Horiguchi 5-20-1, Josuihoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Co., Ltd. 5B024 AA04 AA15 BA29 CA16 CA21 5F038 BE07 CA03 CA05 CA06 CA10 CD06 CD08 CD09 DF01 DF05 DF14 EZ20

Claims (17)

[Claims] 1. A semiconductor chip comprising: a plurality of interface terminals for interfacing a plurality of bits of information in parallel with the outside; and a plurality of interface circuits provided corresponding to each of the plurality of interface terminals. Wherein the plurality of interface circuits are arranged in a plurality of groups, and each group of interface circuits is connected to a timing control line for supplying a timing signal for controlling an interface operation in a group unit in series. A semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein the interface circuits of each group are arranged collectively for each group. 3. The semiconductor device according to claim 1, wherein said interface terminal includes a data terminal, and said interface circuit includes a data output circuit connected to said data terminal. 4. The semiconductor device according to claim 3, wherein said interface circuit includes a data input circuit connected to said data terminal. 5. The timing control wiring for each group has a driver at a base end, and the driver having a relatively large driving ability is connected to a timing control line having a relatively large load. Claim 3 characterized by the following:
Or the semiconductor device according to 4. 6. The timing signal includes: a buffer circuit connected to a corresponding interface terminal; and a latch circuit connected to the corresponding buffer circuit and performing an operation of latching information to be interfaced. 5. The semiconductor device according to claim 3, wherein は is a latch control signal of said latch circuit. 7. The interface signal line connecting the buffer circuit and the interface terminal, the interface signal line having at least substantially equal delay components in each of the groups. Semiconductor device. 8. The data read operation further includes a plurality of memory cells for storing data input from the data terminal and enabling the stored data to be output from the data terminal. Data read from a memory cell selected from the cells is latched by a latch circuit of the data output circuit and applied to the data terminal. In a data write operation, a data input circuit of the data input circuit receives data from the plurality of data terminals. 7. The data latched in the latch circuit is written in a memory cell selected from a plurality of memory cells.
13. The semiconductor device according to claim 1. 9. A data strobe signal is output in synchronization with a timing signal for latching the latch circuit of the output circuit in response to a data read operation, and the latch circuit of the input circuit is latched in response to a data write operation. 9. The semiconductor device according to claim 8, further comprising an external signal terminal for inputting a data strobe signal for synchronizing a timing signal to be operated as said interface terminal. 10. A plurality of input circuits are arranged on a semiconductor chip, each of which has an input buffer and an input latch circuit connected thereto, wherein said input latch circuit is connected to an input buffer. An input gate; and a static latch connected to the input gate, wherein the input gate comprises a first clocked inverter that is activated and controlled in response to a complementary clock signal whose edge change timing is aligned. A semiconductor device, wherein the latch includes a second clocked inverter that receives the complementary clock signal and is activated and controlled in a phase opposite to that of the first clocked inverter. 11. A semiconductor chip having a plurality of output circuits disposed therein, each output circuit including an output latch circuit and an output buffer connected thereto, wherein the output latch circuit has an input gate and an input gate. A static latch having an input connected thereto and an output connected to the output buffer, wherein the input gate is formed of a clocked inverter that is activated and controlled by receiving a complementary clock signal whose edge change timing is aligned. A semiconductor device characterized by the above-mentioned. 12. A signal generation circuit for generating a complementary clock signal having the same edge change timing, wherein the signal generation circuit has a pair of differential amplifier circuits, and includes a pair of differential amplifier circuits. A clock terminal is commonly connected to one differential input terminal having different polarities, and a reference voltage terminal is connected to the other differential input terminal having different polarities between the pair of differential amplifier circuits. 12. The semiconductor device according to claim 10, wherein complementary clock signals whose edge change timings are aligned are output from output nodes of the same polarity of the amplifier circuit. 13. A plurality of data terminals, a plurality of input circuits and a plurality of output circuits provided corresponding to the plurality of data terminals, respectively, wherein each of the plurality of input circuits is Operating in response to a first timing signal, each of the plurality of output circuits operating in response to a second timing signal, wherein the plurality of input circuits are concentratedly arranged in a first region; The semiconductor device according to claim 1, wherein the output circuits are arranged intensively in the second region. 14. The semiconductor device according to claim 13, wherein said first region and said second region are rectangular. 15. Each of the plurality of input circuits includes a first latch circuit, wherein the first latch circuit retains data input to a data terminal in response to the first timing signal. Each include a second latch circuit,
14. The semiconductor device according to claim 13, wherein the second latch circuit outputs the held data in response to the second timing signal. 16. A semiconductor device, comprising: a plurality of buffer circuits coupled between the plurality of output circuits and a corresponding plurality of data terminals, wherein each of the buffer circuits receives data received from the second latch circuit. 16. The semiconductor device according to claim 15, wherein the data is output to a corresponding data terminal. 17. The semiconductor device further includes a plurality of memory cells, and in a read operation from the memory cells, data read from a memory cell selected from the plurality of memory cells is stored in the memory device. In the write operation to the plurality of memory cells, the data held in the first latch circuit is written to a memory cell selected from the plurality of memory cells. 16. The semiconductor device according to claim 15, wherein: